armreg.h revision 1.28
1 /* $NetBSD: armreg.h,v 1.28 2019/09/15 15:16:30 tnn Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AARCH64_ARMREG_H_ 33 #define _AARCH64_ARMREG_H_ 34 35 #include <arm/cputypes.h> 36 #include <sys/types.h> 37 38 #define AARCH64REG_READ_INLINE2(regname, regdesc) \ 39 static __inline uint64_t \ 40 reg_##regname##_read(void) \ 41 { \ 42 uint64_t __rv; \ 43 __asm __volatile("mrs %0, " #regdesc : "=r"(__rv)); \ 44 return __rv; \ 45 } 46 47 #define AARCH64REG_WRITE_INLINE2(regname, regdesc) \ 48 static __inline void \ 49 reg_##regname##_write(uint64_t __val) \ 50 { \ 51 __asm __volatile("msr " #regdesc ", %0" :: "r"(__val)); \ 52 } 53 54 #define AARCH64REG_WRITEIMM_INLINE2(regname, regdesc) \ 55 static __inline void \ 56 reg_##regname##_write(uint64_t __val) \ 57 { \ 58 __asm __volatile("msr " #regdesc ", %0" :: "n"(__val)); \ 59 } 60 61 #define AARCH64REG_READ_INLINE(regname) \ 62 AARCH64REG_READ_INLINE2(regname, regname) 63 64 #define AARCH64REG_WRITE_INLINE(regname) \ 65 AARCH64REG_WRITE_INLINE2(regname, regname) 66 67 #define AARCH64REG_WRITEIMM_INLINE(regname) \ 68 AARCH64REG_WRITEIMM_INLINE2(regname, regname) 69 70 #define AARCH64REG_READWRITE_INLINE2(regname, regdesc) \ 71 AARCH64REG_READ_INLINE2(regname, regdesc) \ 72 AARCH64REG_WRITE_INLINE2(regname, regdesc) 73 74 #define AARCH64REG_ATWRITE_INLINE2(regname, regdesc) \ 75 static __inline void \ 76 reg_##regname##_write(uint64_t __val) \ 77 { \ 78 __asm __volatile("at " #regdesc ", %0" :: "r"(__val)); \ 79 } 80 81 #define AARCH64REG_ATWRITE_INLINE(regname) \ 82 AARCH64REG_ATWRITE_INLINE2(regname, regname) 83 84 /* 85 * System registers available at EL0 (user) 86 */ 87 AARCH64REG_READ_INLINE(ctr_el0) // Cache Type Register 88 89 #define CTR_EL0_CWG_LINE __BITS(27,24) // Cacheback Writeback Granule 90 #define CTR_EL0_ERG_LINE __BITS(23,20) // Exclusives Reservation Granule 91 #define CTR_EL0_DMIN_LINE __BITS(19,16) // Dcache MIN LINE size (log2 - 2) 92 #define CTR_EL0_L1IP_MASK __BITS(15,14) 93 #define CTR_EL0_L1IP_AIVIVT 1 // ASID-tagged Virtual Index, Virtual Tag 94 #define CTR_EL0_L1IP_VIPT 2 // Virtual Index, Physical Tag 95 #define CTR_EL0_L1IP_PIPT 3 // Physical Index, Physical Tag 96 #define CTR_EL0_IMIN_LINE __BITS(3,0) // Icache MIN LINE size (log2 - 2) 97 98 AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register 99 100 #define DCZID_DZP __BIT(4) // Data Zero Prohibited 101 #define DCZID_BS __BITS(3,0) // Block Size (log2 - 2) 102 103 AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register 104 AARCH64REG_WRITE_INLINE(fpcr) 105 106 #define FPCR_AHP __BIT(26) // Alternative Half Precision 107 #define FPCR_DN __BIT(25) // Default Nan Control 108 #define FPCR_FZ __BIT(24) // Flush-To-Zero 109 #define FPCR_RMODE __BITS(23,22) // Rounding Mode 110 #define FPCR_RN 0 // Round Nearest 111 #define FPCR_RP 1 // Round towards Plus infinity 112 #define FPCR_RM 2 // Round towards Minus infinity 113 #define FPCR_RZ 3 // Round towards Zero 114 #define FPCR_STRIDE __BITS(21,20) 115 #define FPCR_FZ16 __BIT(19) // Flush-To-Zero for FP16 116 #define FPCR_LEN __BITS(18,16) 117 #define FPCR_IDE __BIT(15) // Input Denormal Exception enable 118 #define FPCR_IXE __BIT(12) // IneXact Exception enable 119 #define FPCR_UFE __BIT(11) // UnderFlow Exception enable 120 #define FPCR_OFE __BIT(10) // OverFlow Exception enable 121 #define FPCR_DZE __BIT(9) // Divide by Zero Exception enable 122 #define FPCR_IOE __BIT(8) // Invalid Operation Exception enable 123 #define FPCR_ESUM 0x1F00 124 125 AARCH64REG_READ_INLINE(fpsr) // Floating Point Status Register 126 AARCH64REG_WRITE_INLINE(fpsr) 127 128 #define FPSR_N32 __BIT(31) // AARCH32 Negative 129 #define FPSR_Z32 __BIT(30) // AARCH32 Zero 130 #define FPSR_C32 __BIT(29) // AARCH32 Carry 131 #define FPSR_V32 __BIT(28) // AARCH32 Overflow 132 #define FPSR_QC __BIT(27) // SIMD Saturation 133 #define FPSR_IDC __BIT(7) // Input Denormal Cumulative status 134 #define FPSR_IXC __BIT(4) // IneXact Cumulative status 135 #define FPSR_UFC __BIT(3) // UnderFlow Cumulative status 136 #define FPSR_OFC __BIT(2) // OverFlow Cumulative status 137 #define FPSR_DZC __BIT(1) // Divide by Zero Cumulative status 138 #define FPSR_IOC __BIT(0) // Invalid Operation Cumulative status 139 #define FPSR_CSUM 0x1F 140 141 AARCH64REG_READ_INLINE(nzcv) // condition codes 142 AARCH64REG_WRITE_INLINE(nzcv) 143 144 #define NZCV_N __BIT(31) // Negative 145 #define NZCV_Z __BIT(30) // Zero 146 #define NZCV_C __BIT(29) // Carry 147 #define NZCV_V __BIT(28) // Overflow 148 149 AARCH64REG_READ_INLINE(tpidr_el0) // Thread Pointer ID Register (RW) 150 AARCH64REG_WRITE_INLINE(tpidr_el0) 151 152 AARCH64REG_READ_INLINE(tpidrro_el0) // Thread Pointer ID Register (RO) 153 154 /* 155 * From here on, these can only be accessed at EL1 (kernel) 156 */ 157 158 /* 159 * These are readonly registers 160 */ 161 AARCH64REG_READ_INLINE(aidr_el1) 162 163 AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57 164 165 #define CBAR_PA __BITS(47,18) 166 167 AARCH64REG_READ_INLINE(ccsidr_el1) 168 169 #define CCSIDR_WT __BIT(31) // Write-through supported 170 #define CCSIDR_WB __BIT(30) // Write-back supported 171 #define CCSIDR_RA __BIT(29) // Read-allocation supported 172 #define CCSIDR_WA __BIT(28) // Write-allocation supported 173 #define CCSIDR_NUMSET __BITS(27,13) // (Number of sets in cache) - 1 174 #define CCSIDR_ASSOC __BITS(12,3) // (Associativity of cache) - 1 175 #define CCSIDR_LINESIZE __BITS(2,0) // Number of bytes in cache line 176 177 AARCH64REG_READ_INLINE(clidr_el1) 178 179 #define CLIDR_LOUU __BITS(29,27) // Level of Unification Uniprocessor 180 #define CLIDR_LOC __BITS(26,24) // Level of Coherency 181 #define CLIDR_LOUIS __BITS(23,21) // Level of Unification InnerShareable*/ 182 #define CLIDR_CTYPE7 __BITS(20,18) // Cache Type field for level7 183 #define CLIDR_CTYPE6 __BITS(17,15) // Cache Type field for level6 184 #define CLIDR_CTYPE5 __BITS(14,12) // Cache Type field for level5 185 #define CLIDR_CTYPE4 __BITS(11,9) // Cache Type field for level4 186 #define CLIDR_CTYPE3 __BITS(8,6) // Cache Type field for level3 187 #define CLIDR_CTYPE2 __BITS(5,3) // Cache Type field for level2 188 #define CLIDR_CTYPE1 __BITS(2,0) // Cache Type field for level1 189 #define CLIDR_TYPE_NOCACHE 0 // No cache 190 #define CLIDR_TYPE_ICACHE 1 // Instruction cache only 191 #define CLIDR_TYPE_DCACHE 2 // Data cache only 192 #define CLIDR_TYPE_IDCACHE 3 // Separate inst and data caches 193 #define CLIDR_TYPE_UNIFIEDCACHE 4 // Unified cache 194 195 AARCH64REG_READ_INLINE(currentel) 196 AARCH64REG_READ_INLINE(id_aa64afr0_el1) 197 AARCH64REG_READ_INLINE(id_aa64afr1_el1) 198 AARCH64REG_READ_INLINE(id_aa64dfr0_el1) 199 200 #define ID_AA64DFR0_EL1_CTX_CMPS __BITS(31,28) 201 #define ID_AA64DFR0_EL1_WRPS __BITS(20,23) 202 #define ID_AA64DFR0_EL1_BRPS __BITS(12,15) 203 #define ID_AA64DFR0_EL1_PMUVER __BITS(8,11) 204 #define ID_AA64DFR0_EL1_PMUVER_NONE 0 205 #define ID_AA64DFR0_EL1_PMUVER_V3 1 206 #define ID_AA64DFR0_EL1_PMUVER_NOV3 2 207 #define ID_AA64DFR0_EL1_TRACEVER __BITS(4,7) 208 #define ID_AA64DFR0_EL1_TRACEVER_NONE 0 209 #define ID_AA64DFR0_EL1_TRACEVER_IMPL 1 210 #define ID_AA64DFR0_EL1_DEBUGVER __BITS(0,3) 211 #define ID_AA64DFR0_EL1_DEBUGVER_V8A 6 212 213 AARCH64REG_READ_INLINE(id_aa64dfr1_el1) 214 215 AARCH64REG_READ_INLINE(id_aa64isar0_el1) 216 217 #define ID_AA64ISAR0_EL1_CRC32 __BITS(19,16) 218 #define ID_AA64ISAR0_EL1_CRC32_NONE 0 219 #define ID_AA64ISAR0_EL1_CRC32_CRC32X 1 220 #define ID_AA64ISAR0_EL1_SHA2 __BITS(15,12) 221 #define ID_AA64ISAR0_EL1_SHA2_NONE 0 222 #define ID_AA64ISAR0_EL1_SHA2_SHA256HSU 1 223 #define ID_AA64ISAR0_EL1_SHA1 __BITS(11,8) 224 #define ID_AA64ISAR0_EL1_SHA1_NONE 0 225 #define ID_AA64ISAR0_EL1_SHA1_SHA1CPMHSU 1 226 #define ID_AA64ISAR0_EL1_AES __BITS(7,4) 227 #define ID_AA64ISAR0_EL1_AES_NONE 0 228 #define ID_AA64ISAR0_EL1_AES_AES 1 229 #define ID_AA64ISAR0_EL1_AES_PMUL 2 230 231 AARCH64REG_READ_INLINE(id_aa64isar1_el1) 232 AARCH64REG_READ_INLINE(id_aa64mmfr0_el1) 233 234 #define ID_AA64MMFR0_EL1_TGRAN4 __BITS(31,28) 235 #define ID_AA64MMFR0_EL1_TGRAN4_4KB 0 236 #define ID_AA64MMFR0_EL1_TGRAN4_NONE 15 237 #define ID_AA64MMFR0_EL1_TGRAN64 __BITS(24,27) 238 #define ID_AA64MMFR0_EL1_TGRAN64_64KB 0 239 #define ID_AA64MMFR0_EL1_TGRAN64_NONE 15 240 #define ID_AA64MMFR0_EL1_TGRAN16 __BITS(20,23) 241 #define ID_AA64MMFR0_EL1_TGRAN16_NONE 0 242 #define ID_AA64MMFR0_EL1_TGRAN16_16KB 1 243 #define ID_AA64MMFR0_EL1_BIGENDEL0 __BITS(16,19) 244 #define ID_AA64MMFR0_EL1_BIGENDEL0_NONE 0 245 #define ID_AA64MMFR0_EL1_BIGENDEL0_MIX 1 246 #define ID_AA64MMFR0_EL1_SNSMEM __BITS(12,15) 247 #define ID_AA64MMFR0_EL1_SNSMEM_NONE 0 248 #define ID_AA64MMFR0_EL1_SNSMEM_SNSMEM 1 249 #define ID_AA64MMFR0_EL1_BIGEND __BITS(8,11) 250 #define ID_AA64MMFR0_EL1_BIGEND_NONE 0 251 #define ID_AA64MMFR0_EL1_BIGEND_MIX 1 252 #define ID_AA64MMFR0_EL1_ASIDBITS __BITS(4,7) 253 #define ID_AA64MMFR0_EL1_ASIDBITS_8BIT 0 254 #define ID_AA64MMFR0_EL1_ASIDBITS_16BIT 2 255 #define ID_AA64MMFR0_EL1_PARANGE __BITS(0,3) 256 #define ID_AA64MMFR0_EL1_PARANGE_4G 0 257 #define ID_AA64MMFR0_EL1_PARANGE_64G 1 258 #define ID_AA64MMFR0_EL1_PARANGE_1T 2 259 #define ID_AA64MMFR0_EL1_PARANGE_4T 3 260 #define ID_AA64MMFR0_EL1_PARANGE_16T 4 261 #define ID_AA64MMFR0_EL1_PARANGE_256T 5 262 263 AARCH64REG_READ_INLINE2(a72_cpuactlr_el1, s3_1_c15_c2_0) 264 AARCH64REG_READ_INLINE(id_aa64mmfr1_el1) 265 AARCH64REG_READ_INLINE(id_aa64mmfr2_el1) 266 AARCH64REG_READ_INLINE(id_aa64pfr0_el1) 267 AARCH64REG_READ_INLINE(id_aa64pfr1_el1) 268 AARCH64REG_READ_INLINE(id_aa64zfr0_el1) 269 AARCH64REG_READ_INLINE(id_pfr1_el1) 270 AARCH64REG_READ_INLINE(isr_el1) 271 AARCH64REG_READ_INLINE(midr_el1) 272 AARCH64REG_READ_INLINE(mpidr_el1) 273 274 #define MIDR_EL1_IMPL __BITS(31,24) // Implementor 275 #define MIDR_EL1_VARIANT __BITS(23,20) // CPU Variant 276 #define MIDR_EL1_ARCH __BITS(19,16) // Architecture 277 #define MIDR_EL1_PARTNUM __BITS(15,4) // PartNum 278 #define MIDR_EL1_REVISION __BITS(3,0) // Revision 279 280 #define MPIDR_AFF3 __BITS(32,39) 281 #define MPIDR_U __BIT(30) // 1 = Uni-Processor System 282 #define MPIDR_MT __BIT(24) // 1 = SMT(AFF0 is logical) 283 #define MPIDR_AFF2 __BITS(16,23) 284 #define MPIDR_AFF1 __BITS(8,15) 285 #define MPIDR_AFF0 __BITS(0,7) 286 287 AARCH64REG_READ_INLINE(mvfr0_el1) 288 289 #define MVFR0_FPROUND __BITS(31,28) 290 #define MVFR0_FPROUND_NEAREST 0 291 #define MVFR0_FPROUND_ALL 1 292 #define MVFR0_FPSHVEC __BITS(27,24) 293 #define MVFR0_FPSHVEC_NONE 0 294 #define MVFR0_FPSHVEC_SHVEC 1 295 #define MVFR0_FPSQRT __BITS(23,20) 296 #define MVFR0_FPSQRT_NONE 0 297 #define MVFR0_FPSQRT_VSQRT 1 298 #define MVFR0_FPDIVIDE __BITS(19,16) 299 #define MVFR0_FPDIVIDE_NONE 0 300 #define MVFR0_FPDIVIDE_VDIV 1 301 #define MVFR0_FPTRAP __BITS(15,12) 302 #define MVFR0_FPTRAP_NONE 0 303 #define MVFR0_FPTRAP_TRAP 1 304 #define MVFR0_FPDP __BITS(11,8) 305 #define MVFR0_FPDP_NONE 0 306 #define MVFR0_FPDP_VFPV2 1 307 #define MVFR0_FPDP_VFPV3 2 308 #define MVFR0_FPSP __BITS(7,4) 309 #define MVFR0_FPSP_NONE 0 310 #define MVFR0_FPSP_VFPV2 1 311 #define MVFR0_FPSP_VFPV3 2 312 #define MVFR0_SIMDREG __BITS(3,0) 313 #define MVFR0_SIMDREG_NONE 0 314 #define MVFR0_SIMDREG_16x64 1 315 #define MVFR0_SIMDREG_32x64 2 316 317 AARCH64REG_READ_INLINE(mvfr1_el1) 318 319 #define MVFR1_SIMDFMAC __BITS(31,28) 320 #define MVFR1_SIMDFMAC_NONE 0 321 #define MVFR1_SIMDFMAC_FMAC 1 322 #define MVFR1_FPHP __BITS(27,24) 323 #define MVFR1_FPHP_NONE 0 324 #define MVFR1_FPHP_HALF_SINGLE 1 325 #define MVFR1_FPHP_HALF_DOUBLE 2 326 #define MVFR1_FPHP_HALF_ARITH 3 327 #define MVFR1_SIMDHP __BITS(23,20) 328 #define MVFR1_SIMDHP_NONE 0 329 #define MVFR1_SIMDHP_HALF 1 330 #define MVFR1_SIMDHP_HALF_ARITH 3 331 #define MVFR1_SIMDSP __BITS(19,16) 332 #define MVFR1_SIMDSP_NONE 0 333 #define MVFR1_SIMDSP_SINGLE 1 334 #define MVFR1_SIMDINT __BITS(15,12) 335 #define MVFR1_SIMDINT_NONE 0 336 #define MVFR1_SIMDINT_INTEGER 1 337 #define MVFR1_SIMDLS __BITS(11,8) 338 #define MVFR1_SIMDLS_NONE 0 339 #define MVFR1_SIMDLS_LOADSTORE 1 340 #define MVFR1_FPDNAN __BITS(7,4) 341 #define MVFR1_FPDNAN_NONE 0 342 #define MVFR1_FPDNAN_NAN 1 343 #define MVFR1_FPFTZ __BITS(3,0) 344 #define MVFR1_FPFTZ_NONE 0 345 #define MVFR1_FPFTZ_DENORMAL 1 346 347 AARCH64REG_READ_INLINE(mvfr2_el1) 348 349 #define MVFR2_FPMISC __BITS(7,4) 350 #define MVFR2_FPMISC_NONE 0 351 #define MVFR2_FPMISC_SEL 1 352 #define MVFR2_FPMISC_DROUND 2 353 #define MVFR2_FPMISC_ROUNDINT 3 354 #define MVFR2_FPMISC_MAXMIN 4 355 #define MVFR2_SIMDMISC __BITS(3,0) 356 #define MVFR2_SIMDMISC_NONE 0 357 #define MVFR2_SIMDMISC_DROUND 1 358 #define MVFR2_SIMDMISC_ROUNDINT 2 359 #define MVFR2_SIMDMISC_MAXMIN 3 360 361 AARCH64REG_READ_INLINE(revidr_el1) 362 363 /* 364 * These are read/write registers 365 */ 366 AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Regiser 367 AARCH64REG_WRITE_INLINE(cpacr_el1) 368 369 #define CPACR_TTA __BIT(28) // System Register Access Traps 370 #define CPACR_FPEN __BITS(21,20) 371 #define CPACR_FPEN_NONE __SHIFTIN(0, CPACR_FPEN) 372 #define CPACR_FPEN_EL1 __SHIFTIN(1, CPACR_FPEN) 373 #define CPACR_FPEN_NONE_2 __SHIFTIN(2, CPACR_FPEN) 374 #define CPACR_FPEN_ALL __SHIFTIN(3, CPACR_FPEN) 375 376 AARCH64REG_READ_INLINE(csselr_el1) // Cache Size Selection Register 377 AARCH64REG_WRITE_INLINE(csselr_el1) 378 379 #define CSSELR_LEVEL __BITS(3,1) // Cache level of required cache 380 #define CSSELR_IND __BIT(0) // Instruction not Data bit 381 382 AARCH64REG_READ_INLINE(daif) // Debug Async Irq Fiq mask register 383 AARCH64REG_WRITE_INLINE(daif) 384 AARCH64REG_WRITEIMM_INLINE(daifclr) 385 AARCH64REG_WRITEIMM_INLINE(daifset) 386 387 #define DAIF_D __BIT(9) // Debug Exception Mask 388 #define DAIF_A __BIT(8) // SError Abort Mask 389 #define DAIF_I __BIT(7) // IRQ Mask 390 #define DAIF_F __BIT(6) // FIQ Mask 391 #define DAIF_SETCLR_SHIFT 6 // for daifset/daifclr #imm shift 392 393 AARCH64REG_READ_INLINE(elr_el1) // Exception Link Register 394 AARCH64REG_WRITE_INLINE(elr_el1) 395 396 AARCH64REG_READ_INLINE(esr_el1) // Exception Symdrone Register 397 AARCH64REG_WRITE_INLINE(esr_el1) 398 399 #define ESR_EC __BITS(31,26) // Exception Cause 400 #define ESR_EC_UNKNOWN 0x00 // AXX: Unknown Reason 401 #define ESR_EC_WFX 0x01 // AXX: WFI or WFE instruction execution 402 #define ESR_EC_CP15_RT 0x03 // A32: MCR/MRC access to CP15 !EC=0 403 #define ESR_EC_CP15_RRT 0x04 // A32: MCRR/MRRC access to CP15 !EC=0 404 #define ESR_EC_CP14_RT 0x05 // A32: MCR/MRC access to CP14 405 #define ESR_EC_CP14_DT 0x06 // A32: LDC/STC access to CP14 406 #define ESR_EC_FP_ACCESS 0x07 // AXX: Access to SIMD/FP Registers 407 #define ESR_EC_FPID 0x08 // A32: MCR/MRC access to CP10 !EC=7 408 #define ESR_EC_CP14_RRT 0x0c // A32: MRRC access to CP14 409 #define ESR_EC_ILL_STATE 0x0e // AXX: Illegal Execution State 410 #define ESR_EC_SVC_A32 0x11 // A32: SVC Instruction Execution 411 #define ESR_EC_HVC_A32 0x12 // A32: HVC Instruction Execution 412 #define ESR_EC_SMC_A32 0x13 // A32: SMC Instruction Execution 413 #define ESR_EC_SVC_A64 0x15 // A64: SVC Instruction Execution 414 #define ESR_EC_HVC_A64 0x16 // A64: HVC Instruction Execution 415 #define ESR_EC_SMC_A64 0x17 // A64: SMC Instruction Execution 416 #define ESR_EC_SYS_REG 0x18 // A64: MSR/MRS/SYS instruction (!EC0/1/7) 417 #define ESR_EC_INSN_ABT_EL0 0x20 // AXX: Instruction Abort (EL0) 418 #define ESR_EC_INSN_ABT_EL1 0x21 // AXX: Instruction Abort (EL1) 419 #define ESR_EC_PC_ALIGNMENT 0x22 // AXX: Misaligned PC 420 #define ESR_EC_DATA_ABT_EL0 0x24 // AXX: Data Abort (EL0) 421 #define ESR_EC_DATA_ABT_EL1 0x25 // AXX: Data Abort (EL1) 422 #define ESR_EC_SP_ALIGNMENT 0x26 // AXX: Misaligned SP 423 #define ESR_EC_FP_TRAP_A32 0x28 // A32: FP Exception 424 #define ESR_EC_FP_TRAP_A64 0x2c // A64: FP Exception 425 #define ESR_EC_SERROR 0x2f // AXX: SError Interrupt 426 #define ESR_EC_BRKPNT_EL0 0x30 // AXX: Breakpoint Exception (EL0) 427 #define ESR_EC_BRKPNT_EL1 0x31 // AXX: Breakpoint Exception (EL1) 428 #define ESR_EC_SW_STEP_EL0 0x32 // AXX: Software Step (EL0) 429 #define ESR_EC_SW_STEP_EL1 0x33 // AXX: Software Step (EL1) 430 #define ESR_EC_WTCHPNT_EL0 0x34 // AXX: Watchpoint (EL0) 431 #define ESR_EC_WTCHPNT_EL1 0x35 // AXX: Watchpoint (EL1) 432 #define ESR_EC_BKPT_INSN_A32 0x38 // A32: BKPT Instruction Execution 433 #define ESR_EC_VECTOR_CATCH 0x3a // A32: Vector Catch Exception 434 #define ESR_EC_BKPT_INSN_A64 0x3c // A64: BKPT Instruction Execution 435 #define ESR_IL __BIT(25) // Instruction Length (1=32-bit) 436 #define ESR_ISS __BITS(24,0) // Instruction Specific Syndrome 437 #define ESR_ISS_CV __BIT(24) // common 438 #define ESR_ISS_COND __BITS(23,20) // common 439 #define ESR_ISS_WFX_TRAP_INSN __BIT(0) // for ESR_EC_WFX 440 #define ESR_ISS_MRC_OPC2 __BITS(19,17) // for ESR_EC_CP15_RT 441 #define ESR_ISS_MRC_OPC1 __BITS(16,14) // for ESR_EC_CP15_RT 442 #define ESR_ISS_MRC_CRN __BITS(13,10) // for ESR_EC_CP15_RT 443 #define ESR_ISS_MRC_RT __BITS(9,5) // for ESR_EC_CP15_RT 444 #define ESR_ISS_MRC_CRM __BITS(4,1) // for ESR_EC_CP15_RT 445 #define ESR_ISS_MRC_DIRECTION __BIT(0) // for ESR_EC_CP15_RT 446 #define ESR_ISS_MCRR_OPC1 __BITS(19,16) // for ESR_EC_CP15_RRT 447 #define ESR_ISS_MCRR_RT2 __BITS(14,10) // for ESR_EC_CP15_RRT 448 #define ESR_ISS_MCRR_RT __BITS(9,5) // for ESR_EC_CP15_RRT 449 #define ESR_ISS_MCRR_CRM __BITS(4,1) // for ESR_EC_CP15_RRT 450 #define ESR_ISS_MCRR_DIRECTION __BIT(0) // for ESR_EC_CP15_RRT 451 #define ESR_ISS_HVC_IMM16 __BITS(15,0) // for ESR_EC_{SVC,HVC} 452 // ... 453 #define ESR_ISS_INSNABORT_EA __BIT(9) // for ESC_RC_INSN_ABT_EL[01] 454 #define ESR_ISS_INSNABORT_S1PTW __BIT(7) // for ESC_RC_INSN_ABT_EL[01] 455 #define ESR_ISS_INSNABORT_IFSC __BITS(0,5) // for ESC_RC_INSN_ABT_EL[01] 456 #define ESR_ISS_DATAABORT_ISV __BIT(24) // for ESC_RC_DATA_ABT_EL[01] 457 #define ESR_ISS_DATAABORT_SAS __BITS(23,22) // for ESC_RC_DATA_ABT_EL[01] 458 #define ESR_ISS_DATAABORT_SSE __BIT(21) // for ESC_RC_DATA_ABT_EL[01] 459 #define ESR_ISS_DATAABORT_SRT __BITS(19,16) // for ESC_RC_DATA_ABT_EL[01] 460 #define ESR_ISS_DATAABORT_SF __BIT(15) // for ESC_RC_DATA_ABT_EL[01] 461 #define ESR_ISS_DATAABORT_AR __BIT(14) // for ESC_RC_DATA_ABT_EL[01] 462 #define ESR_ISS_DATAABORT_EA __BIT(9) // for ESC_RC_DATA_ABT_EL[01] 463 #define ESR_ISS_DATAABORT_CM __BIT(8) // for ESC_RC_DATA_ABT_EL[01] 464 #define ESR_ISS_DATAABORT_S1PTW __BIT(7) // for ESC_RC_DATA_ABT_EL[01] 465 #define ESR_ISS_DATAABORT_WnR __BIT(6) // for ESC_RC_DATA_ABT_EL[01] 466 #define ESR_ISS_DATAABORT_DFSC __BITS(0,5) // for ESC_RC_DATA_ABT_EL[01] 467 468 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_0 0x00 469 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_1 0x01 470 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_2 0x02 471 #define ESR_ISS_FSC_ADDRESS_SIZE_FAULT_3 0x03 472 #define ESR_ISS_FSC_TRANSLATION_FAULT_0 0x04 473 #define ESR_ISS_FSC_TRANSLATION_FAULT_1 0x05 474 #define ESR_ISS_FSC_TRANSLATION_FAULT_2 0x06 475 #define ESR_ISS_FSC_TRANSLATION_FAULT_3 0x07 476 #define ESR_ISS_FSC_ACCESS_FAULT_0 0x08 477 #define ESR_ISS_FSC_ACCESS_FAULT_1 0x09 478 #define ESR_ISS_FSC_ACCESS_FAULT_2 0x0a 479 #define ESR_ISS_FSC_ACCESS_FAULT_3 0x0b 480 #define ESR_ISS_FSC_PERM_FAULT_0 0x0c 481 #define ESR_ISS_FSC_PERM_FAULT_1 0x0d 482 #define ESR_ISS_FSC_PERM_FAULT_2 0x0e 483 #define ESR_ISS_FSC_PERM_FAULT_3 0x0f 484 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT 0x10 485 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_0 0x14 486 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_1 0x15 487 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_2 0x16 488 #define ESR_ISS_FSC_SYNC_EXTERNAL_ABORT_TTWALK_3 0x17 489 #define ESR_ISS_FSC_SYNC_PARITY_ERROR 0x18 490 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_0 0x1c 491 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_1 0x1d 492 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_2 0x1e 493 #define ESR_ISS_FSC_SYNC_PARITY_ERROR_ON_TTWALK_3 0x1f 494 #define ESR_ISS_FSC_ALIGNMENT_FAULT 0x21 495 #define ESR_ISS_FSC_TLB_CONFLICT_FAULT 0x30 496 #define ESR_ISS_FSC_LOCKDOWN_ABORT 0x34 497 #define ESR_ISS_FSC_UNSUPPORTED_EXCLUSIVE 0x35 498 #define ESR_ISS_FSC_FIRST_LEVEL_DOMAIN_FAULT 0x3d 499 #define ESR_ISS_FSC_SECOND_LEVEL_DOMAIN_FAULT 0x3e 500 501 502 AARCH64REG_READ_INLINE(far_el1) // Fault Address Register 503 AARCH64REG_WRITE_INLINE(far_el1) 504 505 AARCH64REG_READ_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73 506 AARCH64REG_WRITE_INLINE2(l2ctlr_el1, s3_1_c11_c0_2) // Cortex-A53,57,72,73 507 508 #define L2CTLR_NUMOFCORE __BITS(25,24) // Number of cores 509 #define L2CTLR_CPUCACHEPROT __BIT(22) // CPU Cache Protection 510 #define L2CTLR_SCUL2CACHEPROT __BIT(21) // SCU-L2 Cache Protection 511 #define L2CTLR_L2_INPUT_LATENCY __BIT(5) // L2 Data RAM input latency 512 #define L2CTLR_L2_OUTPUT_LATENCY __BIT(0) // L2 Data RAM output latency 513 514 AARCH64REG_READ_INLINE(mair_el1) // Memory Attribute Indirection Register 515 AARCH64REG_WRITE_INLINE(mair_el1) 516 517 #define MAIR_ATTR0 __BITS(7,0) 518 #define MAIR_ATTR1 __BITS(15,8) 519 #define MAIR_ATTR2 __BITS(23,16) 520 #define MAIR_ATTR3 __BITS(31,24) 521 #define MAIR_ATTR4 __BITS(39,32) 522 #define MAIR_ATTR5 __BITS(47,40) 523 #define MAIR_ATTR6 __BITS(55,48) 524 #define MAIR_ATTR7 __BITS(63,56) 525 #define MAIR_DEVICE_nGnRnE 0x00 // NoGathering,NoReordering,NoEarlyWriteAck. 526 #define MAIR_NORMAL_NC 0x44 527 #define MAIR_NORMAL_WT 0xbb 528 #define MAIR_NORMAL_WB 0xff 529 530 AARCH64REG_READ_INLINE(par_el1) // Physical Address Register 531 AARCH64REG_WRITE_INLINE(par_el1) 532 533 #define PAR_ATTR __BITS(63,56) // F=0 memory attributes 534 #define PAR_PA __BITS(47,12) // F=0 physical address 535 #define PAR_NS __BIT(9) // F=0 non-secure 536 #define PAR_S __BIT(9) // F=1 failure stage 537 #define PAR_SHA __BITS(8,7) // F=0 shareability attribute 538 #define PAR_SHA_NONE 0 539 #define PAR_SHA_OUTER 2 540 #define PAR_SHA_INNER 3 541 #define PAR_PTW __BIT(8) // F=1 partial table walk 542 #define PAR_FST __BITS(6,1) // F=1 fault status code 543 #define PAR_F __BIT(0) // translation failed 544 545 AARCH64REG_READ_INLINE(rmr_el1) // Reset Management Register 546 AARCH64REG_WRITE_INLINE(rmr_el1) 547 548 AARCH64REG_READ_INLINE(rvbar_el1) // Reset Vector Base Address Register 549 AARCH64REG_WRITE_INLINE(rvbar_el1) 550 551 AARCH64REG_ATWRITE_INLINE(s1e0r); // Address Translate Stages 1 552 AARCH64REG_ATWRITE_INLINE(s1e0w); 553 AARCH64REG_ATWRITE_INLINE(s1e1r); 554 AARCH64REG_ATWRITE_INLINE(s1e1w); 555 556 AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register 557 AARCH64REG_WRITE_INLINE(sctlr_el1) 558 559 #define SCTLR_RES0 0xc8222400 // Reserved ARMv8.0, write 0 560 #define SCTLR_RES1 0x30d00800 // Reserved ARMv8.0, write 1 561 #define SCTLR_M __BIT(0) 562 #define SCTLR_A __BIT(1) 563 #define SCTLR_C __BIT(2) 564 #define SCTLR_SA __BIT(3) 565 #define SCTLR_SA0 __BIT(4) 566 #define SCTLR_CP15BEN __BIT(5) 567 #define SCTLR_THEE __BIT(6) 568 #define SCTLR_ITD __BIT(7) 569 #define SCTLR_SED __BIT(8) 570 #define SCTLR_UMA __BIT(9) 571 #define SCTLR_I __BIT(12) 572 #define SCTLR_DZE __BIT(14) 573 #define SCTLR_UCT __BIT(15) 574 #define SCTLR_nTWI __BIT(16) 575 #define SCTLR_nTWE __BIT(18) 576 #define SCTLR_WXN __BIT(19) 577 #define SCTLR_IESB __BIT(21) 578 #define SCTLR_SPAN __BIT(23) 579 #define SCTLR_EOE __BIT(24) 580 #define SCTLR_EE __BIT(25) 581 #define SCTLR_UCI __BIT(26) 582 #define SCTLR_nTLSMD __BIT(28) 583 #define SCTLR_LSMAOE __BIT(29) 584 585 // current EL stack pointer 586 static __inline uint64_t 587 reg_sp_read(void) 588 { 589 uint64_t __rv; 590 __asm __volatile ("mov %0, sp" : "=r"(__rv)); 591 return __rv; 592 } 593 594 AARCH64REG_READ_INLINE(sp_el0) // EL0 Stack Pointer 595 AARCH64REG_WRITE_INLINE(sp_el0) 596 597 AARCH64REG_READ_INLINE(spsel) // Stack Pointer Select 598 AARCH64REG_WRITE_INLINE(spsel) 599 600 #define SPSEL_SP __BIT(0); // use SP_EL0 at all exception levels 601 602 AARCH64REG_READ_INLINE(spsr_el1) // Saved Program Status Register 603 AARCH64REG_WRITE_INLINE(spsr_el1) 604 605 #define SPSR_NZCV __BITS(31,28) // mask of N Z C V 606 #define SPSR_N __BIT(31) // Negative 607 #define SPSR_Z __BIT(30) // Zero 608 #define SPSR_C __BIT(29) // Carry 609 #define SPSR_V __BIT(28) // oVerflow 610 #define SPSR_A32_Q __BIT(27) // A32: Overflow 611 #define SPSR_A32_J __BIT(24) // A32: Jazelle Mode 612 #define SPSR_A32_IT1 __BIT(23) // A32: IT[1] 613 #define SPSR_A32_IT0 __BIT(22) // A32: IT[0] 614 #define SPSR_SS __BIT(21) // Software Step 615 #define SPSR_SS_SHIFT 21 616 #define SPSR_IL __BIT(20) // Instruction Length 617 #define SPSR_GE __BITS(19,16) // A32: SIMD GE 618 #define SPSR_IT7 __BIT(15) // A32: IT[7] 619 #define SPSR_IT6 __BIT(14) // A32: IT[6] 620 #define SPSR_IT5 __BIT(13) // A32: IT[5] 621 #define SPSR_IT4 __BIT(12) // A32: IT[4] 622 #define SPSR_IT3 __BIT(11) // A32: IT[3] 623 #define SPSR_IT2 __BIT(10) // A32: IT[2] 624 #define SPSR_A64_D __BIT(9) // A64: Debug Exception Mask 625 #define SPSR_A32_E __BIT(9) // A32: BE Endian Mode 626 #define SPSR_A __BIT(8) // Async abort (SError) Mask 627 #define SPSR_I __BIT(7) // IRQ Mask 628 #define SPSR_F __BIT(6) // FIQ Mask 629 #define SPSR_A32_T __BIT(5) // A32 Thumb Mode 630 #define SPSR_A32 __BIT(4) // A32 Mode (a part of SPSR_M) 631 #define SPSR_M __BITS(4,0) // Execution State 632 #define SPSR_M_EL3H 0x0d 633 #define SPSR_M_EL3T 0x0c 634 #define SPSR_M_EL2H 0x09 635 #define SPSR_M_EL2T 0x08 636 #define SPSR_M_EL1H 0x05 637 #define SPSR_M_EL1T 0x04 638 #define SPSR_M_EL0T 0x00 639 #define SPSR_M_SYS32 0x1f 640 #define SPSR_M_UND32 0x1b 641 #define SPSR_M_ABT32 0x17 642 #define SPSR_M_SVC32 0x13 643 #define SPSR_M_IRQ32 0x12 644 #define SPSR_M_FIQ32 0x11 645 #define SPSR_M_USR32 0x10 646 647 AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register 648 AARCH64REG_WRITE_INLINE(tcr_el1) 649 650 651 /* TCR_EL1 - Translation Control Register */ 652 #define TCR_TBI1 __BIT(38) /* ignore Top Byte TTBR1_EL1 */ 653 #define TCR_TBI0 __BIT(37) /* ignore Top Byte TTBR0_EL1 */ 654 #define TCR_AS64K __BIT(36) /* Use 64K ASIDs */ 655 #define TCR_IPS __BITS(34,32) /* Intermediate PhysAdr Size */ 656 #define TCR_IPS_4PB __SHIFTIN(6,TCR_IPS) /* 52 bits ( 4 PB) */ 657 #define TCR_IPS_256TB __SHIFTIN(5,TCR_IPS) /* 48 bits (256 TB) */ 658 #define TCR_IPS_16TB __SHIFTIN(4,TCR_IPS) /* 44 bits (16 TB) */ 659 #define TCR_IPS_4TB __SHIFTIN(3,TCR_IPS) /* 42 bits ( 4 TB) */ 660 #define TCR_IPS_1TB __SHIFTIN(2,TCR_IPS) /* 40 bits ( 1 TB) */ 661 #define TCR_IPS_64GB __SHIFTIN(1,TCR_IPS) /* 36 bits (64 GB) */ 662 #define TCR_IPS_4GB __SHIFTIN(0,TCR_IPS) /* 32 bits (4 GB) */ 663 #define TCR_TG1 __BITS(31,30) /* TTBR1 Page Granule Size */ 664 #define TCR_TG1_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */ 665 #define TCR_TG1_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */ 666 #define TCR_TG1_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */ 667 #define TCR_SH1 __BITS(29,28) 668 #define TCR_SH1_NONE __SHIFTIN(0,TCR_SH1) 669 #define TCR_SH1_OUTER __SHIFTIN(2,TCR_SH1) 670 #define TCR_SH1_INNER __SHIFTIN(3,TCR_SH1) 671 #define TCR_ORGN1 __BITS(27,26) /* TTBR1 Outer cacheability */ 672 #define TCR_ORGN1_NC __SHIFTIN(0,TCR_ORGN1) /* Non Cacheable */ 673 #define TCR_ORGN1_WB_WA __SHIFTIN(1,TCR_ORGN1) /* WriteBack WriteAllocate */ 674 #define TCR_ORGN1_WT __SHIFTIN(2,TCR_ORGN1) /* WriteThrough */ 675 #define TCR_ORGN1_WB __SHIFTIN(3,TCR_ORGN1) /* WriteBack */ 676 #define TCR_IRGN1 __BITS(25,24) /* TTBR1 Inner cacheability */ 677 #define TCR_IRGN1_NC __SHIFTIN(0,TCR_IRGN1) /* Non Cacheable */ 678 #define TCR_IRGN1_WB_WA __SHIFTIN(1,TCR_IRGN1) /* WriteBack WriteAllocate */ 679 #define TCR_IRGN1_WT __SHIFTIN(2,TCR_IRGN1) /* WriteThrough */ 680 #define TCR_IRGN1_WB __SHIFTIN(3,TCR_IRGN1) /* WriteBack */ 681 #define TCR_EPD1 __BIT(23) /* Walk Disable for TTBR1_EL1 */ 682 #define TCR_A1 __BIT(22) /* ASID is in TTBR1_EL1 */ 683 #define TCR_T1SZ __BITS(21,16) /* Size offset for TTBR1_EL1 */ 684 #define TCR_TG0 __BITS(15,14) /* TTBR0 Page Granule Size */ 685 #define TCR_TG0_4KB __SHIFTIN(0,TCR_TG0) /* 4KB page size */ 686 #define TCR_TG0_64KB __SHIFTIN(1,TCR_TG0) /* 64KB page size */ 687 #define TCR_TG0_16KB __SHIFTIN(2,TCR_TG0) /* 16KB page size */ 688 #define TCR_SH0 __BITS(13,12) 689 #define TCR_SH0_NONE __SHIFTIN(0,TCR_SH0) 690 #define TCR_SH0_OUTER __SHIFTIN(2,TCR_SH0) 691 #define TCR_SH0_INNER __SHIFTIN(3,TCR_SH0) 692 #define TCR_ORGN0 __BITS(11,10) /* TTBR0 Outer cacheability */ 693 #define TCR_ORGN0_NC __SHIFTIN(0,TCR_ORGN0) /* Non Cacheable */ 694 #define TCR_ORGN0_WB_WA __SHIFTIN(1,TCR_ORGN0) /* WriteBack WriteAllocate */ 695 #define TCR_ORGN0_WT __SHIFTIN(2,TCR_ORGN0) /* WriteThrough */ 696 #define TCR_ORGN0_WB __SHIFTIN(3,TCR_ORGN0) /* WriteBack */ 697 #define TCR_IRGN0 __BITS(9,8) /* TTBR0 Inner cacheability */ 698 #define TCR_IRGN0_NC __SHIFTIN(0,TCR_IRGN0) /* Non Cacheable */ 699 #define TCR_IRGN0_WB_WA __SHIFTIN(1,TCR_IRGN0) /* WriteBack WriteAllocate */ 700 #define TCR_IRGN0_WT __SHIFTIN(2,TCR_IRGN0) /* WriteThrough */ 701 #define TCR_IRGN0_WB __SHIFTIN(3,TCR_IRGN0) /* WriteBack */ 702 #define TCR_EPD0 __BIT(7) /* Walk Disable for TTBR0 */ 703 #define TCR_T0SZ __BITS(5,0) /* Size offset for TTBR0_EL1 */ 704 705 AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1) 706 AARCH64REG_WRITE_INLINE(tpidr_el1) 707 708 AARCH64REG_WRITE_INLINE(tpidrro_el0) // Thread ID Register (RO for EL0) 709 710 AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL1 711 AARCH64REG_WRITE_INLINE(ttbr0_el1) 712 713 AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1 714 AARCH64REG_WRITE_INLINE(ttbr1_el1) 715 716 #define TTBR_ASID __BITS(63,48) 717 #define TTBR_BADDR __BITS(47,0) 718 719 AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register 720 AARCH64REG_WRITE_INLINE(vbar_el1) 721 722 /* 723 * From here on, these are DEBUG registers 724 */ 725 AARCH64REG_READ_INLINE(dbgbcr0_el1) // Debug Breakpoint Control Register 0 726 AARCH64REG_WRITE_INLINE(dbgbcr0_el1) 727 AARCH64REG_READ_INLINE(dbgbcr1_el1) // Debug Breakpoint Control Register 1 728 AARCH64REG_WRITE_INLINE(dbgbcr1_el1) 729 AARCH64REG_READ_INLINE(dbgbcr2_el1) // Debug Breakpoint Control Register 2 730 AARCH64REG_WRITE_INLINE(dbgbcr2_el1) 731 AARCH64REG_READ_INLINE(dbgbcr3_el1) // Debug Breakpoint Control Register 3 732 AARCH64REG_WRITE_INLINE(dbgbcr3_el1) 733 AARCH64REG_READ_INLINE(dbgbcr4_el1) // Debug Breakpoint Control Register 4 734 AARCH64REG_WRITE_INLINE(dbgbcr4_el1) 735 AARCH64REG_READ_INLINE(dbgbcr5_el1) // Debug Breakpoint Control Register 5 736 AARCH64REG_WRITE_INLINE(dbgbcr5_el1) 737 AARCH64REG_READ_INLINE(dbgbcr6_el1) // Debug Breakpoint Control Register 6 738 AARCH64REG_WRITE_INLINE(dbgbcr6_el1) 739 AARCH64REG_READ_INLINE(dbgbcr7_el1) // Debug Breakpoint Control Register 7 740 AARCH64REG_WRITE_INLINE(dbgbcr7_el1) 741 AARCH64REG_READ_INLINE(dbgbcr8_el1) // Debug Breakpoint Control Register 8 742 AARCH64REG_WRITE_INLINE(dbgbcr8_el1) 743 AARCH64REG_READ_INLINE(dbgbcr9_el1) // Debug Breakpoint Control Register 9 744 AARCH64REG_WRITE_INLINE(dbgbcr9_el1) 745 AARCH64REG_READ_INLINE(dbgbcr10_el1) // Debug Breakpoint Control Register 10 746 AARCH64REG_WRITE_INLINE(dbgbcr10_el1) 747 AARCH64REG_READ_INLINE(dbgbcr11_el1) // Debug Breakpoint Control Register 11 748 AARCH64REG_WRITE_INLINE(dbgbcr11_el1) 749 AARCH64REG_READ_INLINE(dbgbcr12_el1) // Debug Breakpoint Control Register 12 750 AARCH64REG_WRITE_INLINE(dbgbcr12_el1) 751 AARCH64REG_READ_INLINE(dbgbcr13_el1) // Debug Breakpoint Control Register 13 752 AARCH64REG_WRITE_INLINE(dbgbcr13_el1) 753 AARCH64REG_READ_INLINE(dbgbcr14_el1) // Debug Breakpoint Control Register 14 754 AARCH64REG_WRITE_INLINE(dbgbcr14_el1) 755 AARCH64REG_READ_INLINE(dbgbcr15_el1) // Debug Breakpoint Control Register 15 756 AARCH64REG_WRITE_INLINE(dbgbcr15_el1) 757 758 #define DBGBCR_BT __BITS(23,20) 759 #define DBGBCR_LBN __BITS(19,16) 760 #define DBGBCR_SSC __BITS(15,14) 761 #define DBGBCR_HMC __BIT(13) 762 #define DBGBCR_BAS __BITS(8,5) 763 #define DBGBCR_PMC __BITS(2,1) 764 #define DBGBCR_E __BIT(0) 765 766 AARCH64REG_READ_INLINE(dbgbvr0_el1) // Debug Breakpoint Value Register 0 767 AARCH64REG_WRITE_INLINE(dbgbvr0_el1) 768 AARCH64REG_READ_INLINE(dbgbvr1_el1) // Debug Breakpoint Value Register 1 769 AARCH64REG_WRITE_INLINE(dbgbvr1_el1) 770 AARCH64REG_READ_INLINE(dbgbvr2_el1) // Debug Breakpoint Value Register 2 771 AARCH64REG_WRITE_INLINE(dbgbvr2_el1) 772 AARCH64REG_READ_INLINE(dbgbvr3_el1) // Debug Breakpoint Value Register 3 773 AARCH64REG_WRITE_INLINE(dbgbvr3_el1) 774 AARCH64REG_READ_INLINE(dbgbvr4_el1) // Debug Breakpoint Value Register 4 775 AARCH64REG_WRITE_INLINE(dbgbvr4_el1) 776 AARCH64REG_READ_INLINE(dbgbvr5_el1) // Debug Breakpoint Value Register 5 777 AARCH64REG_WRITE_INLINE(dbgbvr5_el1) 778 AARCH64REG_READ_INLINE(dbgbvr6_el1) // Debug Breakpoint Value Register 6 779 AARCH64REG_WRITE_INLINE(dbgbvr6_el1) 780 AARCH64REG_READ_INLINE(dbgbvr7_el1) // Debug Breakpoint Value Register 7 781 AARCH64REG_WRITE_INLINE(dbgbvr7_el1) 782 AARCH64REG_READ_INLINE(dbgbvr8_el1) // Debug Breakpoint Value Register 8 783 AARCH64REG_WRITE_INLINE(dbgbvr8_el1) 784 AARCH64REG_READ_INLINE(dbgbvr9_el1) // Debug Breakpoint Value Register 9 785 AARCH64REG_WRITE_INLINE(dbgbvr9_el1) 786 AARCH64REG_READ_INLINE(dbgbvr10_el1) // Debug Breakpoint Value Register 10 787 AARCH64REG_WRITE_INLINE(dbgbvr10_el1) 788 AARCH64REG_READ_INLINE(dbgbvr11_el1) // Debug Breakpoint Value Register 11 789 AARCH64REG_WRITE_INLINE(dbgbvr11_el1) 790 AARCH64REG_READ_INLINE(dbgbvr12_el1) // Debug Breakpoint Value Register 12 791 AARCH64REG_WRITE_INLINE(dbgbvr12_el1) 792 AARCH64REG_READ_INLINE(dbgbvr13_el1) // Debug Breakpoint Value Register 13 793 AARCH64REG_WRITE_INLINE(dbgbvr13_el1) 794 AARCH64REG_READ_INLINE(dbgbvr14_el1) // Debug Breakpoint Value Register 14 795 AARCH64REG_WRITE_INLINE(dbgbvr14_el1) 796 AARCH64REG_READ_INLINE(dbgbvr15_el1) // Debug Breakpoint Value Register 15 797 AARCH64REG_WRITE_INLINE(dbgbvr15_el1) 798 799 AARCH64REG_READ_INLINE(dbgwcr0_el1) // Debug Watchpoint Control Register 0 800 AARCH64REG_WRITE_INLINE(dbgwcr0_el1) 801 AARCH64REG_READ_INLINE(dbgwcr1_el1) // Debug Watchpoint Control Register 1 802 AARCH64REG_WRITE_INLINE(dbgwcr1_el1) 803 AARCH64REG_READ_INLINE(dbgwcr2_el1) // Debug Watchpoint Control Register 2 804 AARCH64REG_WRITE_INLINE(dbgwcr2_el1) 805 AARCH64REG_READ_INLINE(dbgwcr3_el1) // Debug Watchpoint Control Register 3 806 AARCH64REG_WRITE_INLINE(dbgwcr3_el1) 807 AARCH64REG_READ_INLINE(dbgwcr4_el1) // Debug Watchpoint Control Register 4 808 AARCH64REG_WRITE_INLINE(dbgwcr4_el1) 809 AARCH64REG_READ_INLINE(dbgwcr5_el1) // Debug Watchpoint Control Register 5 810 AARCH64REG_WRITE_INLINE(dbgwcr5_el1) 811 AARCH64REG_READ_INLINE(dbgwcr6_el1) // Debug Watchpoint Control Register 6 812 AARCH64REG_WRITE_INLINE(dbgwcr6_el1) 813 AARCH64REG_READ_INLINE(dbgwcr7_el1) // Debug Watchpoint Control Register 7 814 AARCH64REG_WRITE_INLINE(dbgwcr7_el1) 815 AARCH64REG_READ_INLINE(dbgwcr8_el1) // Debug Watchpoint Control Register 8 816 AARCH64REG_WRITE_INLINE(dbgwcr8_el1) 817 AARCH64REG_READ_INLINE(dbgwcr9_el1) // Debug Watchpoint Control Register 9 818 AARCH64REG_WRITE_INLINE(dbgwcr9_el1) 819 AARCH64REG_READ_INLINE(dbgwcr10_el1) // Debug Watchpoint Control Register 10 820 AARCH64REG_WRITE_INLINE(dbgwcr10_el1) 821 AARCH64REG_READ_INLINE(dbgwcr11_el1) // Debug Watchpoint Control Register 11 822 AARCH64REG_WRITE_INLINE(dbgwcr11_el1) 823 AARCH64REG_READ_INLINE(dbgwcr12_el1) // Debug Watchpoint Control Register 12 824 AARCH64REG_WRITE_INLINE(dbgwcr12_el1) 825 AARCH64REG_READ_INLINE(dbgwcr13_el1) // Debug Watchpoint Control Register 13 826 AARCH64REG_WRITE_INLINE(dbgwcr13_el1) 827 AARCH64REG_READ_INLINE(dbgwcr14_el1) // Debug Watchpoint Control Register 14 828 AARCH64REG_WRITE_INLINE(dbgwcr14_el1) 829 AARCH64REG_READ_INLINE(dbgwcr15_el1) // Debug Watchpoint Control Register 15 830 AARCH64REG_WRITE_INLINE(dbgwcr15_el1) 831 832 #define DBGWCR_MASK __BITS(28,24) 833 #define DBGWCR_WT __BIT(20) 834 #define DBGWCR_LBN __BITS(19,16) 835 #define DBGWCR_SSC __BITS(15,14) 836 #define DBGWCR_HMC __BIT(13) 837 #define DBGWCR_BAS __BITS(12,5) 838 #define DBGWCR_LSC __BITS(4,3) 839 #define DBGWCR_PAC __BITS(2,1) 840 #define DBGWCR_E __BIT(0) 841 842 AARCH64REG_READ_INLINE(dbgwvr0_el1) // Debug Watchpoint Value Register 0 843 AARCH64REG_WRITE_INLINE(dbgwvr0_el1) 844 AARCH64REG_READ_INLINE(dbgwvr1_el1) // Debug Watchpoint Value Register 1 845 AARCH64REG_WRITE_INLINE(dbgwvr1_el1) 846 AARCH64REG_READ_INLINE(dbgwvr2_el1) // Debug Watchpoint Value Register 2 847 AARCH64REG_WRITE_INLINE(dbgwvr2_el1) 848 AARCH64REG_READ_INLINE(dbgwvr3_el1) // Debug Watchpoint Value Register 3 849 AARCH64REG_WRITE_INLINE(dbgwvr3_el1) 850 AARCH64REG_READ_INLINE(dbgwvr4_el1) // Debug Watchpoint Value Register 4 851 AARCH64REG_WRITE_INLINE(dbgwvr4_el1) 852 AARCH64REG_READ_INLINE(dbgwvr5_el1) // Debug Watchpoint Value Register 5 853 AARCH64REG_WRITE_INLINE(dbgwvr5_el1) 854 AARCH64REG_READ_INLINE(dbgwvr6_el1) // Debug Watchpoint Value Register 6 855 AARCH64REG_WRITE_INLINE(dbgwvr6_el1) 856 AARCH64REG_READ_INLINE(dbgwvr7_el1) // Debug Watchpoint Value Register 7 857 AARCH64REG_WRITE_INLINE(dbgwvr7_el1) 858 AARCH64REG_READ_INLINE(dbgwvr8_el1) // Debug Watchpoint Value Register 8 859 AARCH64REG_WRITE_INLINE(dbgwvr8_el1) 860 AARCH64REG_READ_INLINE(dbgwvr9_el1) // Debug Watchpoint Value Register 9 861 AARCH64REG_WRITE_INLINE(dbgwvr9_el1) 862 AARCH64REG_READ_INLINE(dbgwvr10_el1) // Debug Watchpoint Value Register 10 863 AARCH64REG_WRITE_INLINE(dbgwvr10_el1) 864 AARCH64REG_READ_INLINE(dbgwvr11_el1) // Debug Watchpoint Value Register 11 865 AARCH64REG_WRITE_INLINE(dbgwvr11_el1) 866 AARCH64REG_READ_INLINE(dbgwvr12_el1) // Debug Watchpoint Value Register 12 867 AARCH64REG_WRITE_INLINE(dbgwvr12_el1) 868 AARCH64REG_READ_INLINE(dbgwvr13_el1) // Debug Watchpoint Value Register 13 869 AARCH64REG_WRITE_INLINE(dbgwvr13_el1) 870 AARCH64REG_READ_INLINE(dbgwvr14_el1) // Debug Watchpoint Value Register 14 871 AARCH64REG_WRITE_INLINE(dbgwvr14_el1) 872 AARCH64REG_READ_INLINE(dbgwvr15_el1) // Debug Watchpoint Value Register 15 873 AARCH64REG_WRITE_INLINE(dbgwvr15_el1) 874 875 #define DBGWVR_MASK __BITS(64,3) 876 877 878 AARCH64REG_READ_INLINE(mdscr_el1) // Monitor Debug System Control Register 879 AARCH64REG_WRITE_INLINE(mdscr_el1) 880 881 #define MDSCR_RXFULL __BIT(30) // for EDSCR.RXfull 882 #define MDSCR_TXFULL __BIT(29) // for EDSCR.TXfull 883 #define MDSCR_RXO __BIT(27) // for EDSCR.RXO 884 #define MDSCR_TXU __BIT(26) // for EDSCR.TXU 885 #define MDSCR_INTDIS __BITS(32,22) // for EDSCR.INTdis 886 #define MDSCR_TDA __BIT(21) // for EDSCR.TDA 887 #define MDSCR_MDE __BIT(15) // Monitor debug events 888 #define MDSCR_HDE __BIT(14) // for EDSCR.HDE 889 #define MDSCR_KDE __BIT(13) // Local debug enable 890 #define MDSCR_TDCC __BIT(12) // Trap Debug CommCh access 891 #define MDSCR_ERR __BIT(6) // for EDSCR.ERR 892 #define MDSCR_SS __BIT(0) // Software step 893 894 AARCH64REG_WRITE_INLINE(oslar_el1) // OS Lock Access Register 895 896 AARCH64REG_READ_INLINE(oslsr_el1) // OS Lock Status Register 897 898 /* 899 * From here on, these are PMC registers 900 */ 901 902 AARCH64REG_READ_INLINE(pmccfiltr_el0) 903 AARCH64REG_WRITE_INLINE(pmccfiltr_el0) 904 905 #define PMCCFILTR_P __BIT(31) // Don't count cycles in EL1 906 #define PMCCFILTR_U __BIT(30) // Don't count cycles in EL0 907 #define PMCCFILTR_NSK __BIT(29) // Don't count cycles in NS EL1 908 #define PMCCFILTR_NSU __BIT(28) // Don't count cycles in NS EL0 909 #define PMCCFILTR_NSH __BIT(27) // Don't count cycles in NS EL2 910 #define PMCCFILTR_M __BIT(26) // Don't count cycles in EL3 911 912 AARCH64REG_READ_INLINE(pmccntr_el0) 913 914 AARCH64REG_READ_INLINE(pmceid0_el0) 915 AARCH64REG_READ_INLINE(pmceid1_el0) 916 917 AARCH64REG_WRITE_INLINE(pmcntenclr_el0) 918 AARCH64REG_WRITE_INLINE(pmcntenset_el0) 919 920 AARCH64REG_READ_INLINE(pmcr_el0) 921 AARCH64REG_WRITE_INLINE(pmcr_el0) 922 923 #define PMCR_IMP __BITS(31,24) // Implementor code 924 #define PMCR_IDCODE __BITS(23,16) // Identification code 925 #define PMCR_N __BITS(15,11) // Number of event counters 926 #define PMCR_LC __BIT(6) // Long cycle counter enable 927 #define PMCR_DP __BIT(5) // Disable cycle counter when event 928 // counting is prohibited 929 #define PMCR_X __BIT(4) // Enable export of events 930 #define PMCR_D __BIT(3) // Clock divider 931 #define PMCR_C __BIT(2) // Cycle counter reset 932 #define PMCR_P __BIT(1) // Event counter reset 933 #define PMCR_E __BIT(0) // Enable 934 935 936 AARCH64REG_READ_INLINE(pmevcntr1_el0) 937 AARCH64REG_WRITE_INLINE(pmevcntr1_el0) 938 939 AARCH64REG_READ_INLINE(pmevtyper1_el0) 940 AARCH64REG_WRITE_INLINE(pmevtyper1_el0) 941 942 #define PMEVTYPER_P __BIT(31) // Don't count events in EL1 943 #define PMEVTYPER_U __BIT(30) // Don't count events in EL0 944 #define PMEVTYPER_NSK __BIT(29) // Don't count events in NS EL1 945 #define PMEVTYPER_NSU __BIT(28) // Don't count events in NS EL0 946 #define PMEVTYPER_NSH __BIT(27) // Count events in NS EL2 947 #define PMEVTYPER_M __BIT(26) // Don't count events in EL3 948 #define PMEVTYPER_MT __BIT(25) // Count events on all CPUs with same 949 // aff1 level 950 #define PMEVTYPER_EVTCOUNT __BITS(15,0) // Event to count 951 952 AARCH64REG_WRITE_INLINE(pmintenclr_el1) 953 AARCH64REG_WRITE_INLINE(pmintenset_el1) 954 955 AARCH64REG_WRITE_INLINE(pmovsclr_el0) 956 AARCH64REG_READ_INLINE(pmovsset_el0) 957 AARCH64REG_WRITE_INLINE(pmovsset_el0) 958 959 AARCH64REG_WRITE_INLINE(pmselr_el0) 960 961 AARCH64REG_WRITE_INLINE(pmswinc_el0) 962 963 AARCH64REG_READ_INLINE(pmuserenr_el0) 964 AARCH64REG_WRITE_INLINE(pmuserenr_el0) 965 966 AARCH64REG_READ_INLINE(pmxevcntr_el0) 967 AARCH64REG_WRITE_INLINE(pmxevcntr_el0) 968 969 AARCH64REG_READ_INLINE(pmxevtyper_el0) 970 AARCH64REG_WRITE_INLINE(pmxevtyper_el0) 971 972 /* 973 * Generic timer registers 974 */ 975 976 AARCH64REG_READ_INLINE(cntfrq_el0) 977 978 AARCH64REG_READ_INLINE(cnthctl_el2) 979 AARCH64REG_WRITE_INLINE(cnthctl_el2) 980 981 #define CNTHCTL_EVNTDIR __BIT(3) 982 #define CNTHCTL_EVNTEN __BIT(2) 983 #define CNTHCTL_EL1PCEN __BIT(1) 984 #define CNTHCTL_EL1PCTEN __BIT(0) 985 986 AARCH64REG_READ_INLINE(cntkctl_el1) 987 AARCH64REG_WRITE_INLINE(cntkctl_el1) 988 989 #define CNTKCTL_EL0PTEN __BIT(9) // EL0 access for CNTP CVAL/TVAL/CTL 990 #define CNTKCTL_PL0PTEN CNTKCTL_EL0PTEN 991 #define CNTKCTL_EL0VTEN __BIT(8) // EL0 access for CNTV CVAL/TVAL/CTL 992 #define CNTKCTL_PL0VTEN CNTKCTL_EL0VTEN 993 #define CNTKCTL_ELNTI __BITS(7,4) 994 #define CNTKCTL_EVNTDIR __BIT(3) 995 #define CNTKCTL_EVNTEN __BIT(2) 996 #define CNTKCTL_EL0VCTEN __BIT(1) // EL0 access for CNTVCT and CNTFRQ 997 #define CNTKCTL_PL0VCTEN CNTKCTL_EL0VCTEN 998 #define CNTKCTL_EL0PCTEN __BIT(0) // EL0 access for CNTPCT and CNTFRQ 999 #define CNTKCTL_PL0PCTEN CNTKCTL_EL0PCTEN 1000 1001 AARCH64REG_READ_INLINE(cntp_ctl_el0) 1002 AARCH64REG_WRITE_INLINE(cntp_ctl_el0) 1003 AARCH64REG_READ_INLINE(cntp_cval_el0) 1004 AARCH64REG_WRITE_INLINE(cntp_cval_el0) 1005 AARCH64REG_READ_INLINE(cntp_tval_el0) 1006 AARCH64REG_WRITE_INLINE(cntp_tval_el0) 1007 AARCH64REG_READ_INLINE(cntpct_el0) 1008 AARCH64REG_WRITE_INLINE(cntpct_el0) 1009 1010 AARCH64REG_READ_INLINE(cntps_ctl_el1) 1011 AARCH64REG_WRITE_INLINE(cntps_ctl_el1) 1012 AARCH64REG_READ_INLINE(cntps_cval_el1) 1013 AARCH64REG_WRITE_INLINE(cntps_cval_el1) 1014 AARCH64REG_READ_INLINE(cntps_tval_el1) 1015 AARCH64REG_WRITE_INLINE(cntps_tval_el1) 1016 1017 AARCH64REG_READ_INLINE(cntv_ctl_el0) 1018 AARCH64REG_WRITE_INLINE(cntv_ctl_el0) 1019 AARCH64REG_READ_INLINE(cntv_cval_el0) 1020 AARCH64REG_WRITE_INLINE(cntv_cval_el0) 1021 AARCH64REG_READ_INLINE(cntv_tval_el0) 1022 AARCH64REG_WRITE_INLINE(cntv_tval_el0) 1023 AARCH64REG_READ_INLINE(cntvct_el0) 1024 AARCH64REG_WRITE_INLINE(cntvct_el0) 1025 1026 #define CNTCTL_ISTATUS __BIT(2) // Interrupt Asserted 1027 #define CNTCTL_IMASK __BIT(1) // Timer Interrupt is Masked 1028 #define CNTCTL_ENABLE __BIT(0) // Timer Enabled 1029 1030 // ID_AA64PFR0_EL1: AArch64 Processor Feature Register 0 1031 #define ID_AA64PFR0_EL1_GIC __BITS(24,27) // GIC CPU IF 1032 #define ID_AA64PFR0_EL1_GIC_SHIFT 24 1033 #define ID_AA64PFR0_EL1_GIC_CPUIF_EN 1 1034 #define ID_AA64PFR0_EL1_GIC_CPUIF_NONE 0 1035 #define ID_AA64PFR0_EL1_ADVSIMD __BITS(23,20) // SIMD 1036 #define ID_AA64PFR0_EL1_ADV_SIMD_IMPL 0x0 1037 #define ID_AA64PFR0_EL1_ADV_SIMD_NONE 0xf 1038 #define ID_AA64PFR0_EL1_FP __BITS(19,16) // FP 1039 #define ID_AA64PFR0_EL1_FP_IMPL 0x0 1040 #define ID_AA64PFR0_EL1_FP_NONE 0xf 1041 #define ID_AA64PFR0_EL1_EL3 __BITS(15,12) // EL3 handling 1042 #define ID_AA64PFR0_EL1_EL3_NONE 0 1043 #define ID_AA64PFR0_EL1_EL3_64 1 1044 #define ID_AA64PFR0_EL1_EL3_64_32 2 1045 #define ID_AA64PFR0_EL1_EL2 __BITS(11,8) // EL2 handling 1046 #define ID_AA64PFR0_EL1_EL2_NONE 0 1047 #define ID_AA64PFR0_EL1_EL2_64 1 1048 #define ID_AA64PFR0_EL1_EL2_64_32 2 1049 #define ID_AA64PFR0_EL1_EL1 __BITS(7,4) // EL1 handling 1050 #define ID_AA64PFR0_EL1_EL1_64 1 1051 #define ID_AA64PFR0_EL1_EL1_64_32 2 1052 #define ID_AA64PFR0_EL1_EL0 __BITS(3,0) // EL0 handling 1053 #define ID_AA64PFR0_EL1_EL0_64 1 1054 #define ID_AA64PFR0_EL1_EL0_64_32 2 1055 1056 /* 1057 * GICv3 system registers 1058 */ 1059 AARCH64REG_READWRITE_INLINE2(icc_sre_el1, s3_0_c12_c12_5) 1060 AARCH64REG_READWRITE_INLINE2(icc_ctlr_el1, s3_0_c12_c12_4) 1061 AARCH64REG_READWRITE_INLINE2(icc_pmr_el1, s3_0_c4_c6_0) 1062 AARCH64REG_READWRITE_INLINE2(icc_bpr0_el1, s3_0_c12_c8_3) 1063 AARCH64REG_READWRITE_INLINE2(icc_bpr1_el1, s3_0_c12_c12_3) 1064 AARCH64REG_READWRITE_INLINE2(icc_igrpen0_el1, s3_0_c12_c12_6) 1065 AARCH64REG_READWRITE_INLINE2(icc_igrpen1_el1, s3_0_c12_c12_7) 1066 AARCH64REG_READWRITE_INLINE2(icc_eoir0_el1, s3_0_c12_c8_1) 1067 AARCH64REG_READWRITE_INLINE2(icc_eoir1_el1, s3_0_c12_c12_1) 1068 AARCH64REG_READWRITE_INLINE2(icc_sgi1r_el1, s3_0_c12_c11_5) 1069 AARCH64REG_READ_INLINE2(icc_iar1_el1, s3_0_c12_c12_0) 1070 1071 // ICC_SRE_EL1: Interrupt Controller System Register Enable register 1072 #define ICC_SRE_EL1_DIB __BIT(2) 1073 #define ICC_SRE_EL1_DFB __BIT(1) 1074 #define ICC_SRE_EL1_SRE __BIT(0) 1075 1076 // ICC_SRE_EL2: Interrupt Controller System Register Enable register 1077 #define ICC_SRE_EL2_EN __BIT(3) 1078 #define ICC_SRE_EL2_DIB __BIT(2) 1079 #define ICC_SRE_EL2_DFB __BIT(1) 1080 #define ICC_SRE_EL2_SRE __BIT(0) 1081 1082 // ICC_BPR[01]_EL1: Interrupt Controller Binary Point Register 0/1 1083 #define ICC_BPR_EL1_BinaryPoint __BITS(2,0) 1084 1085 // ICC_CTLR_EL1: Interrupt Controller Control Register 1086 #define ICC_CTLR_EL1_A3V __BIT(15) 1087 #define ICC_CTLR_EL1_SEIS __BIT(14) 1088 #define ICC_CTLR_EL1_IDbits __BITS(13,11) 1089 #define ICC_CTLR_EL1_PRIbits __BITS(10,8) 1090 #define ICC_CTLR_EL1_PMHE __BIT(6) 1091 #define ICC_CTLR_EL1_EOImode __BIT(1) 1092 #define ICC_CTLR_EL1_CBPR __BIT(0) 1093 1094 // ICC_IGRPEN[01]_EL1: Interrupt Controller Interrupt Group 0/1 Enable register 1095 #define ICC_IGRPEN_EL1_Enable __BIT(0) 1096 1097 // ICC_SGI[01]R_EL1: Interrupt Controller Software Generated Interrupt Group 0/1 Register 1098 #define ICC_SGIR_EL1_Aff3 __BITS(55,48) 1099 #define ICC_SGIR_EL1_IRM __BIT(40) 1100 #define ICC_SGIR_EL1_Aff2 __BITS(39,32) 1101 #define ICC_SGIR_EL1_INTID __BITS(27,24) 1102 #define ICC_SGIR_EL1_Aff1 __BITS(23,16) 1103 #define ICC_SGIR_EL1_TargetList __BITS(15,0) 1104 #define ICC_SGIR_EL1_Aff (ICC_SGIR_EL1_Aff3|ICC_SGIR_EL1_Aff2|ICC_SGIR_EL1_Aff1) 1105 1106 // ICC_IAR[01]_EL1: Interrupt Controller Interrupt Acknowledge Register 0/1 1107 #define ICC_IAR_INTID __BITS(23,0) 1108 #define ICC_IAR_INTID_SPURIOUS 1023 1109 1110 /* 1111 * GICv3 REGISTER ACCESS 1112 */ 1113 1114 #define icc_sre_read reg_icc_sre_el1_read 1115 #define icc_sre_write reg_icc_sre_el1_write 1116 #define icc_pmr_read reg_icc_pmr_el1_read 1117 #define icc_pmr_write reg_icc_pmr_el1_write 1118 #define icc_bpr0_write reg_icc_bpr0_el1_write 1119 #define icc_bpr1_write reg_icc_bpr1_el1_write 1120 #define icc_ctlr_read reg_icc_ctlr_el1_read 1121 #define icc_ctlr_write reg_icc_ctlr_el1_write 1122 #define icc_igrpen1_write reg_icc_igrpen1_el1_write 1123 #define icc_sgi1r_write reg_icc_sgi1r_el1_write 1124 #define icc_iar1_read reg_icc_iar1_el1_read 1125 #define icc_eoi1r_write reg_icc_eoir1_el1_write 1126 1127 #if defined(_KERNEL) 1128 1129 /* 1130 * CPU REGISTER ACCESS 1131 */ 1132 static __inline register_t 1133 cpu_mpidr_aff_read(void) 1134 { 1135 1136 return reg_mpidr_el1_read() & 1137 (MPIDR_AFF3|MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0); 1138 } 1139 1140 /* 1141 * GENERIC TIMER REGISTER ACCESS 1142 */ 1143 static __inline uint32_t 1144 gtmr_cntfrq_read(void) 1145 { 1146 1147 return reg_cntfrq_el0_read(); 1148 } 1149 1150 static __inline uint32_t 1151 gtmr_cntk_ctl_read(void) 1152 { 1153 1154 return reg_cntkctl_el1_read(); 1155 } 1156 1157 static __inline void 1158 gtmr_cntk_ctl_write(uint32_t val) 1159 { 1160 1161 reg_cntkctl_el1_write(val); 1162 } 1163 1164 /* 1165 * Counter-timer Virtual Count timer 1166 */ 1167 static __inline uint64_t 1168 gtmr_cntpct_read(void) 1169 { 1170 1171 return reg_cntpct_el0_read(); 1172 } 1173 1174 static __inline uint64_t 1175 gtmr_cntvct_read(void) 1176 { 1177 1178 return reg_cntvct_el0_read(); 1179 } 1180 1181 /* 1182 * Counter-timer Virtual Timer Control register 1183 */ 1184 static __inline uint32_t 1185 gtmr_cntv_ctl_read(void) 1186 { 1187 1188 return reg_cntv_ctl_el0_read(); 1189 } 1190 1191 static __inline void 1192 gtmr_cntv_ctl_write(uint32_t val) 1193 { 1194 1195 reg_cntv_ctl_el0_write(val); 1196 } 1197 1198 /* 1199 * Counter-timer Physical Timer Control register 1200 */ 1201 static __inline uint32_t 1202 gtmr_cntp_ctl_read(void) 1203 { 1204 1205 return reg_cntp_ctl_el0_read(); 1206 } 1207 1208 static __inline void 1209 gtmr_cntp_ctl_write(uint32_t val) 1210 { 1211 1212 reg_cntp_ctl_el0_write(val); 1213 } 1214 1215 /* 1216 * Counter-timer Physical Timer TimerValue register 1217 */ 1218 static __inline uint32_t 1219 gtmr_cntp_tval_read(void) 1220 { 1221 1222 return reg_cntp_tval_el0_read(); 1223 } 1224 1225 static __inline void 1226 gtmr_cntp_tval_write(uint32_t val) 1227 { 1228 1229 reg_cntp_tval_el0_write(val); 1230 } 1231 1232 /* 1233 * Counter-timer Virtual Timer TimerValue register 1234 */ 1235 static __inline uint32_t 1236 gtmr_cntv_tval_read(void) 1237 { 1238 1239 return reg_cntv_tval_el0_read(); 1240 } 1241 1242 static __inline void 1243 gtmr_cntv_tval_write(uint32_t val) 1244 { 1245 1246 reg_cntv_tval_el0_write(val); 1247 } 1248 1249 /* 1250 * Counter-timer Physical Timer CompareValue register 1251 */ 1252 static __inline uint64_t 1253 gtmr_cntp_cval_read(void) 1254 { 1255 1256 return reg_cntp_cval_el0_read(); 1257 } 1258 1259 static __inline void 1260 gtmr_cntp_cval_write(uint64_t val) 1261 { 1262 1263 reg_cntp_cval_el0_write(val); 1264 } 1265 1266 /* 1267 * Counter-timer Virtual Timer CompareValue register 1268 */ 1269 static __inline uint64_t 1270 gtmr_cntv_cval_read(void) 1271 { 1272 1273 return reg_cntv_cval_el0_read(); 1274 } 1275 1276 static __inline void 1277 gtmr_cntv_cval_write(uint64_t val) 1278 { 1279 1280 reg_cntv_cval_el0_write(val); 1281 } 1282 #endif /* _KERNEL */ 1283 1284 /* 1285 * Structure attached to machdep.cpuN.cpu_id sysctl node. 1286 * Always add new members to the end, and avoid arrays. 1287 */ 1288 struct aarch64_sysctl_cpu_id { 1289 uint64_t ac_midr; /* Main ID Register */ 1290 uint64_t ac_revidr; /* Revision ID Register */ 1291 uint64_t ac_mpidr; /* Multiprocessor Affinity Register */ 1292 1293 uint64_t ac_aa64dfr0; /* A64 Debug Feature Register 0 */ 1294 uint64_t ac_aa64dfr1; /* A64 Debug Feature Register 1 */ 1295 1296 uint64_t ac_aa64isar0; /* A64 Instruction Set Attribute Register 0 */ 1297 uint64_t ac_aa64isar1; /* A64 Instruction Set Attribute Register 1 */ 1298 1299 uint64_t ac_aa64mmfr0; /* A64 Memroy Model Feature Register 0 */ 1300 uint64_t ac_aa64mmfr1; /* A64 Memroy Model Feature Register 1 */ 1301 uint64_t ac_aa64mmfr2; /* A64 Memroy Model Feature Register 2 */ 1302 1303 uint64_t ac_aa64pfr0; /* A64 Processor Feature Register 0 */ 1304 uint64_t ac_aa64pfr1; /* A64 Processor Feature Register 1 */ 1305 1306 uint64_t ac_aa64zfr0; /* A64 SVE Feature ID Register 0 */ 1307 1308 uint32_t ac_mvfr0; /* Media and VFP Feature Register 0 */ 1309 uint32_t ac_mvfr1; /* Media and VFP Feature Register 1 */ 1310 uint32_t ac_mvfr2; /* Media and VFP Feature Register 2 */ 1311 }; 1312 1313 #endif /* _AARCH64_ARMREG_H_ */ 1314
Indexes created Sat Oct 11 14:09:46 GMT 2025