armreg.h revision 1.7
1 /* $NetBSD: armreg.h,v 1.7 2018/03/06 08:20:22 skrll Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AARCH64_ARMREG_H_ 33 #define _AARCH64_ARMREG_H_ 34 35 #ifdef __aarch64__ 36 37 #include <sys/types.h> 38 39 #define AARCH64REG_READ_INLINE2(regname, regdesc) \ 40 static uint64_t inline \ 41 reg_##regname##_read(void) \ 42 { \ 43 uint64_t __rv; \ 44 __asm __volatile("mrs %0, " #regdesc : "=r"(__rv)); \ 45 return __rv; \ 46 } 47 48 #define AARCH64REG_WRITE_INLINE2(regname, regdesc) \ 49 static void inline \ 50 reg_##regname##_write(uint64_t __val) \ 51 { \ 52 __asm __volatile("msr " #regdesc ", %0" :: "r"(__val)); \ 53 } 54 55 #define AARCH64REG_WRITEIMM_INLINE2(regname, regdesc) \ 56 static void inline \ 57 reg_##regname##_write(uint64_t __val) \ 58 { \ 59 __asm __volatile("msr " #regdesc ", %0" :: "n"(__val)); \ 60 } 61 62 #define AARCH64REG_READ_INLINE(regname) \ 63 AARCH64REG_READ_INLINE2(regname, regname) 64 65 #define AARCH64REG_WRITE_INLINE(regname) \ 66 AARCH64REG_WRITE_INLINE2(regname, regname) 67 68 #define AARCH64REG_WRITEIMM_INLINE(regname) \ 69 AARCH64REG_WRITEIMM_INLINE2(regname, regname) 70 /* 71 * System registers available at EL0 (user) 72 */ 73 AARCH64REG_READ_INLINE(ctr_el0) // Cache Type Register 74 75 static const uintmax_t 76 CTR_EL0_CWG_LINE = __BITS(27,24), // Cacheback Writeback Granule 77 CTR_EL0_ERG_LINE = __BITS(23,20), // Exclusives Reservation Granule 78 CTR_EL0_DMIN_LINE = __BITS(19,16), // Dcache MIN LINE size (log2 - 2) 79 CTR_EL0_L1IP_MASK = __BITS(15,14), 80 CTR_EL0_L1IP_AIVIVT = 1, // ASID-tagged Virtual Index, Virtual Tag 81 CTR_EL0_L1IP_VIPT = 2, // Virtual Index, Physical Tag 82 CTR_EL0_L1IP_PIPT = 3, // Physical Index, Physical Tag 83 CTR_EL0_IMIN_LINE = __BITS(3,0); // Icache MIN LINE size (log2 - 2) 84 85 AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register 86 87 static const uintmax_t 88 DCZID_DZP = __BIT(4), // Data Zero Prohibited 89 DCZID_BS = __BITS(3,0); // Block Size (log2 - 2) 90 91 AARCH64REG_READ_INLINE(tpidrro_el0) // Thread Pointer ID Register (RO) 92 93 AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register 94 AARCH64REG_WRITE_INLINE(fpcr) 95 96 static const uintmax_t 97 FPCR_AHP = __BIT(26), // Alternative Half Precision 98 FPCR_DN = __BIT(25), // Default Nan Control 99 FPCR_FZ = __BIT(24), // Flush-To-Zero 100 FPCR_RMODE = __BITS(23,22),// Rounding Mode 101 FPCR_RN = 0, // Round Nearest 102 FPCR_RP = 1, // Round towards Plus infinity 103 FPCR_RM = 2, // Round towards Minus infinity 104 FPCR_RZ = 3, // Round towards Zero 105 FPCR_STRIDE = __BITS(21,20), 106 FPCR_LEN = __BITS(18,16), 107 FPCR_IDE = __BIT(15), // Input Denormal Exception enable 108 FPCR_IXE = __BIT(12), // IneXact Exception enable 109 FPCR_UFE = __BIT(11), // UnderFlow Exception enable 110 FPCR_OFE = __BIT(10), // OverFlow Exception enable 111 FPCR_DZE = __BIT(9), // Divide by Zero Exception enable 112 FPCR_IOE = __BIT(8), // Invalid Operation Exception enable 113 FPCR_ESUM = 0x1F00; 114 115 AARCH64REG_READ_INLINE(fpsr) // Floating Point Status Register 116 AARCH64REG_WRITE_INLINE(fpsr) 117 118 static const uintmax_t 119 FPSR_N32 = __BIT(31), // AARCH32 Negative 120 FPSR_Z32 = __BIT(30), // AARCH32 Zero 121 FPSR_C32 = __BIT(29), // AARCH32 Carry 122 FPSR_V32 = __BIT(28), // AARCH32 Overflow 123 FPSR_QC = __BIT(27), // SIMD Saturation 124 FPSR_IDC = __BIT(7), // Input Denormal Cumulative status 125 FPSR_IXC = __BIT(4), // IneXact Cumulative status 126 FPSR_UFC = __BIT(3), // UnderFlow Cumulative status 127 FPSR_OFC = __BIT(2), // OverFlow Cumulative status 128 FPSR_DZC = __BIT(1), // Divide by Zero Cumulative status 129 FPSR_IOC = __BIT(0), // Invalid Operation Cumulative status 130 FPSR_CSUM = 0x1F; 131 132 AARCH64REG_READ_INLINE(nzcv) // condition codes 133 AARCH64REG_WRITE_INLINE(nzcv) 134 135 static const uintmax_t 136 NZCV_N = __BIT(31), // Negative 137 NZCV_Z = __BIT(30), // Zero 138 NZCV_C = __BIT(29), // Carry 139 NZCV_V = __BIT(28); // Overflow 140 141 AARCH64REG_READ_INLINE(tpidr_el0) // Thread Pointer ID Register (RW) 142 AARCH64REG_WRITE_INLINE(tpidr_el0) 143 144 /* 145 * From here on, these can only be accessed at EL1 (kernel) 146 */ 147 148 /* 149 * These are readonly registers 150 */ 151 AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57 152 153 static const uintmax_t CBAR_PA = __BITS(47,18); 154 155 AARCH64REG_READ_INLINE(clidr_el1) 156 AARCH64REG_READ_INLINE(ccsidr_el1) 157 AARCH64REG_READ_INLINE(id_afr0_el1) 158 AARCH64REG_READ_INLINE(id_adr0_el1) 159 AARCH64REG_READ_INLINE(id_isar0_el1) 160 AARCH64REG_READ_INLINE(id_isar1_el1) 161 AARCH64REG_READ_INLINE(id_isar2_el1) 162 AARCH64REG_READ_INLINE(id_isar3_el1) 163 AARCH64REG_READ_INLINE(id_isar4_el1) 164 AARCH64REG_READ_INLINE(id_isar5_el1) 165 AARCH64REG_READ_INLINE(id_mmfr0_el1) 166 AARCH64REG_READ_INLINE(id_mmfr1_el1) 167 AARCH64REG_READ_INLINE(id_mmfr2_el1) 168 AARCH64REG_READ_INLINE(id_mmfr3_el1) 169 AARCH64REG_READ_INLINE(id_prf0_el1) 170 AARCH64REG_READ_INLINE(id_prf1_el1) 171 AARCH64REG_READ_INLINE(isr_el1) 172 AARCH64REG_READ_INLINE(midr_el1) 173 AARCH64REG_READ_INLINE(mpidr_el1) 174 AARCH64REG_READ_INLINE(mvfr0_el1) 175 AARCH64REG_READ_INLINE(mvfr1_el1) 176 AARCH64REG_READ_INLINE(mvfr2_el1) 177 AARCH64REG_READ_INLINE(revidr_el1) 178 179 /* 180 * These are read/write registers 181 */ 182 AARCH64REG_READ_INLINE(ccselr_el1) // Cache Size Selection Register 183 AARCH64REG_WRITE_INLINE(ccselr_el1) 184 185 AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Regiser 186 AARCH64REG_WRITE_INLINE(cpacr_el1) 187 188 static const uintmax_t 189 CPACR_TTA = __BIT(28), // System Register Access Traps 190 CPACR_FPEN = __BITS(21,20), 191 CPACR_FPEN_NONE = __SHIFTIN(0, CPACR_FPEN), 192 CPACR_FPEN_EL1 = __SHIFTIN(1, CPACR_FPEN), 193 CPACR_FPEN_NONE_2 = __SHIFTIN(2, CPACR_FPEN), 194 CPACR_FPEN_ALL = __SHIFTIN(3, CPACR_FPEN); 195 196 AARCH64REG_READ_INLINE(elr_el1) // Exception Link Register 197 AARCH64REG_WRITE_INLINE(elr_el1) 198 199 AARCH64REG_READ_INLINE(esr_el1) // Exception Symdrone Register 200 AARCH64REG_WRITE_INLINE(esr_el1) 201 202 static const uintmax_t 203 ESR_EC = __BITS(31,26), // Exception Cause 204 ESR_EC_UNKNOWN = 0x00, // AXX: Unknown Reason 205 ESR_EC_WFX = 0x01, // AXX: WFI or WFE instruction execution 206 ESR_EC_CP15_RT = 0x03, // A32: MCR/MRC access to CP15 !EC=0 207 ESR_EC_CP15_RRT = 0x04, // A32: MCRR/MRRC access to CP15 !EC=0 208 ESR_EC_CP14_RT = 0x05, // A32: MCR/MRC access to CP14 209 ESR_EC_CP14_DT = 0x06, // A32: LDC/STC access to CP14 210 ESR_EC_FP_ACCESS = 0x07, // AXX: Access to SIMD/FP Registers 211 ESR_EC_FPID = 0x08, // A32: MCR/MRC access to CP10 !EC=7 212 ESR_EC_CP14_RRT = 0x0c, // A32: MRRC access to CP14 213 ESR_EC_ILL_STATE = 0x0e, // AXX: Illegal Execution State 214 ESR_EC_SVC_A32 = 0x11, // A32: SVC Instruction Execution 215 ESR_EC_HVC_A32 = 0x12, // A32: HVC Instruction Execution 216 ESR_EC_SMC_A32 = 0x13, // A32: SMC Instruction Execution 217 ESR_EC_SVC_A64 = 0x15, // A64: SVC Instruction Execution 218 ESR_EC_HVC_A64 = 0x16, // A64: HVC Instruction Execution 219 ESR_EC_SMC_A64 = 0x17, // A64: SMC Instruction Execution 220 ESR_EC_SYS_REG = 0x18, // A64: MSR/MRS/SYS instruction (!EC0/1/7) 221 ESR_EC_INSN_ABT_EL0 = 0x20, // AXX: Instruction Abort (EL0) 222 ESR_EC_INSN_ABT_EL1 = 0x21, // AXX: Instruction Abort (EL1) 223 ESR_EC_PC_ALIGNMENT = 0x22, // AXX: Misaligned PC 224 ESR_EC_DATA_ABT_EL0 = 0x24, // AXX: Data Abort (EL0) 225 ESR_EC_DATA_ABT_EL1 = 0x25, // AXX: Data Abort (EL1) 226 ESR_EC_SP_ALIGNMENT = 0x26, // AXX: Misaligned SP 227 ESR_EC_FP_TRAP_A32 = 0x28, // A32: FP Exception 228 ESR_EC_FP_TRAP_A64 = 0x2c, // A64: FP Exception 229 ESR_EC_SERROR = 0x2f, // AXX: SError Interrupt 230 ESR_EC_BRKPNT_EL0 = 0x30, // AXX: Breakpoint Exception (EL0) 231 ESR_EC_BRKPNT_EL1 = 0x31, // AXX: Breakpoint Exception (EL1) 232 ESR_EC_SW_STEP_EL0 = 0x32, // AXX: Software Step (EL0) 233 ESR_EC_SW_STEP_EL1 = 0x33, // AXX: Software Step (EL1) 234 ESR_EC_WTCHPNT_EL0 = 0x34, // AXX: Watchpoint (EL0) 235 ESR_EC_WTCHPNT_EL1 = 0x35, // AXX: Watchpoint (EL1) 236 ESR_EC_BKPT_INSN_A32 = 0x38, // A32: BKPT Instruction Execution 237 ESR_EC_VECTOR_CATCH = 0x3a, // A32: Vector Catch Exception 238 ESR_EC_BKPT_INSN_A64 = 0x3c, // A64: BKPT Instruction Execution 239 ESR_IL = __BIT(25), // Instruction Length (1=32-bit) 240 ESR_ISS = __BITS(24,0); // Instruction Specific Syndrome 241 242 243 AARCH64REG_READ_INLINE(far_el1) // Fault Address Register 244 AARCH64REG_WRITE_INLINE(far_el1) 245 246 AARCH64REG_READ_INLINE(mair_el1) // Main Id Register 247 AARCH64REG_WRITE_INLINE(mair_el1) 248 249 AARCH64REG_READ_INLINE(par_el1) // Physical Address Register 250 AARCH64REG_WRITE_INLINE(par_el1) 251 252 static const uintmax_t 253 PAR_ATTR = __BITS(63,56),// F=0 memory attributes 254 PAR_PA = __BITS(47,12),// F=0 physical address 255 PAR_NS = __BIT(9), // F=0 non-secure 256 PAR_S = __BIT(9), // F=1 failure stage 257 PAR_SHA = __BITS(8,7), // F=0 shareability attribute 258 PAR_SHA_NONE = 0, 259 PAR_SHA_OUTER = 2, 260 PAR_SHA_INNER = 3, 261 PAR_PTW = __BIT(8), // F=1 partial table walk 262 PAR_FST = __BITS(6,1), // F=1 fault status code 263 PAR_F = __BIT(0); // translation failed 264 265 AARCH64REG_READ_INLINE(rmr_el1) // Reset Management Register 266 AARCH64REG_WRITE_INLINE(rmr_el1) 267 268 AARCH64REG_READ_INLINE(rvbar_el1) // Reset Vector Base Address Register 269 AARCH64REG_WRITE_INLINE(rvbar_el1) 270 271 AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register 272 AARCH64REG_WRITE_INLINE(sctlr_el1) 273 274 AARCH64REG_READ_INLINE(sp_el0) // Stack Pointer 275 AARCH64REG_WRITE_INLINE(sp_el0) 276 277 AARCH64REG_READ_INLINE(daif) // Debug Async Irq Fiq mask register 278 AARCH64REG_WRITE_INLINE(daif) 279 AARCH64REG_WRITEIMM_INLINE(daifclr) 280 AARCH64REG_WRITEIMM_INLINE(daifset) 281 282 static const uintmax_t 283 DAIF_D = __BIT(3), // Debug Exception Mask 284 DAIF_A = __BIT(2), // SError Abort Mask 285 DAIF_I = __BIT(1), // IRQ Mask 286 DAIF_F = __BIT(0); // FIQ Mask 287 288 AARCH64REG_READ_INLINE(spsr_el1) // Saved Program Status Register 289 AARCH64REG_WRITE_INLINE(spsr_el1) 290 291 static const uintmax_t 292 SPSR_NZCV = __BITS(31,28), // mask of N Z C V 293 SPSR_N = __BIT(31), // Negative 294 SPSR_Z = __BIT(30), // Zero 295 SPSR_C = __BIT(29), // Carry 296 SPSR_V = __BIT(28), // oVerflow 297 SPSR_A32_Q = __BIT(27), // A32: Overflow 298 SPSR_A32_J = __BIT(24), // A32: Jazelle Mode 299 SPSR_A32_IT1 = __BIT(23), // A32: IT[1] 300 SPSR_A32_IT0 = __BIT(22), // A32: IT[0] 301 SPSR_SS = __BIT(21), // Software Step 302 SPSR_IL = __BIT(20), // Instruction Length 303 SPSR_GE = __BITS(19,16), // A32: SIMD GE 304 SPSR_IT7 = __BIT(15), // A32: IT[7] 305 SPSR_IT6 = __BIT(14), // A32: IT[6] 306 SPSR_IT5 = __BIT(13), // A32: IT[5] 307 SPSR_IT4 = __BIT(12), // A32: IT[4] 308 SPSR_IT3 = __BIT(11), // A32: IT[3] 309 SPSR_IT2 = __BIT(10), // A32: IT[2] 310 SPSR_A64_D = __BIT(9), // A64: Debug Exception Mask 311 SPSR_A32_E = __BIT(9), // A32: BE Endian Mode 312 SPSR_A = __BIT(8), // Async abort (SError) Mask 313 SPSR_I = __BIT(7), // IRQ Mask 314 SPSR_F = __BIT(6), // FIQ Mask 315 SPSR_A32_T = __BIT(5), // A32 Thumb Mode 316 SPSR_M = __BITS(4,0), // Execution State 317 SPSR_M_EL3H = 0x0d, 318 SPSR_M_EL3T = 0x0c, 319 SPSR_M_EL2H = 0x09, 320 SPSR_M_EL2T = 0x08, 321 SPSR_M_EL1H = 0x05, 322 SPSR_M_EL1T = 0x04, 323 SPSR_M_EL0T = 0x00, 324 SPSR_M_SYS32 = 0x1f, 325 SPSR_M_UND32 = 0x1b, 326 SPSR_M_ABT32 = 0x17, 327 SPSR_M_SVC32 = 0x13, 328 SPSR_M_IRQ32 = 0x12, 329 SPSR_M_FIQ32 = 0x11, 330 SPSR_M_USR32 = 0x10; 331 332 AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register 333 AARCH64REG_WRITE_INLINE(tcr_el1) 334 335 static const uintmax_t 336 TCR_TBI1 = __BIT(38), // ignore Top Byte for TTBR1_EL1 337 TCR_TBI0 = __BIT(37), // ignore Top Byte for TTBR0_EL1 338 TCR_AS64K = __BIT(36), // Use 64K ASIDs 339 TCR_IPS = __BITS(34,32), // Intermediate Phys Addr Size 340 TCR_IPS_256TB = 5, // 48 bits (256 TB) 341 TCR_IPS_64TB = 4, // 44 bits (16 TB) 342 TCR_IPS_4TB = 3, // 42 bits ( 4 TB) 343 TCR_IPS_1TB = 2, // 40 bits ( 1 TB) 344 TCR_IPS_64GB = 1, // 36 bits (64 GB) 345 TCR_IPS_4GB = 0, // 32 bits (4 GB) 346 TCR_TG1 = __BITS(31,30), // Page Granule Size 347 TCR_TG_4KB = 1, // 4KB page size 348 TCR_TG_16KB = 2, // 16KB page size 349 TCR_TG_64KB = 3, // 64KB page size 350 TCR_SH1 = __BITS(29,28), 351 TCR_SH_NONE = 0, 352 TCR_SH_OUTER = 1, 353 TCR_SH_INNER = 2, 354 TCR_ORGN1 = __BITS(27,26), 355 TCR_XRGN_NC = 0, // Non Cacheable 356 TCR_XRGN_WB_WA = 1, // WriteBack WriteAllocate 357 TCR_XRGN_WT = 2, // WriteThrough 358 TCR_XRGN_WB = 3, // WriteBack 359 TCR_IRGN1 = __BITS(25,24), 360 TCR_EPD1 = __BIT(23), // Walk Disable for TTBR1_EL1 361 TCR_A1 = __BIT(22), // ASID is in TTBR1_EL1 362 TCR_T1SZ = __BITS(21,16), // Size offset for TTBR1_EL1 363 TCR_TG0 = __BITS(15,14), 364 TCR_SH0 = __BITS(13,12), 365 TCR_ORGN0 = __BITS(11,10), 366 TCR_IRGN0 = __BITS(9,8), 367 TCR_EPD0 = __BIT(7), // Walk Disable for TTBR0 368 TCR_T0SZ = __BITS(5,0); // Size offset for TTBR0_EL1 369 370 #define TCR_PAGE_SIZE1(tcr) (1L << (__SHIFTOUT(tcr, TCR_TG1) * 2 + 10)) 371 372 AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1) 373 AARCH64REG_WRITE_INLINE(tpidr_el1) 374 375 AARCH64REG_WRITE_INLINE(tpidrro_el0) // Thread ID Register (RO for EL0) 376 377 AARCH64REG_READ_INLINE(ttbr0_el0) // Translation Table Base Register 0 EL0 378 AARCH64REG_WRITE_INLINE(ttbr0_el0) 379 380 AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL0 381 AARCH64REG_WRITE_INLINE(ttbr0_el1) 382 383 AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1 384 AARCH64REG_WRITE_INLINE(ttbr1_el1) 385 386 static const uint64_t 387 TTBR_ASID = __BITS(63, 48), 388 TTBR_BADDR = __BITS(47, 0); 389 390 AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register 391 AARCH64REG_WRITE_INLINE(vbar_el1) 392 393 AARCH64REG_READ_INLINE(pmccfiltr_el0) 394 AARCH64REG_WRITE_INLINE(pmccfiltr_el0) 395 396 static const uintmax_t 397 PMCCFILTR_P = __BIT(31), // Don't count cycles in EL1 398 PMCCFILTR_U = __BIT(30), // Don't count cycles in EL0 399 PMCCFILTR_NSK = __BIT(29), // Don't count cycles in NS EL1 400 PMCCFILTR_NSU = __BIT(28), // Don't count cycles in NS EL0 401 PMCCFILTR_NSH = __BIT(27), // Don't count cycles in NS EL2 402 PMCCFILTR_M = __BIT(26); // Don't count cycles in EL3 403 404 AARCH64REG_READ_INLINE(pmccntr_el0) 405 406 AARCH64REG_READ_INLINE(cntfrq_el0) 407 408 AARCH64REG_READ_INLINE(cntkctl_el1) 409 AARCH64REG_WRITE_INLINE(cntkctl_el1) 410 411 static const uintmax_t 412 CNTKCTL_EL0PTEN = __BIT(9), // EL0 access for CNTP CVAL/TVAL/CTL 413 CNTKCTL_EL0VTEN = __BIT(8), // EL0 access for CNTV CVAL/TVAL/CTL 414 CNTKCTL_ELNTI = __BITS(7,4), 415 CNTKCTL_EVNTDIR = __BIT(3), 416 CNTKCTL_EVNTEN = __BIT(2), 417 CNTKCTL_EL0VCTEN = __BIT(1), // EL0 access for CNTVCT and CNTFRQ 418 CNTKCTL_EL0PCTEN = __BIT(0); // EL0 access for CNTPCT and CNTFRQ 419 420 AARCH64REG_READ_INLINE(cntp_ctl_el0) 421 AARCH64REG_WRITE_INLINE(cntp_ctl_el0) 422 AARCH64REG_READ_INLINE(cntp_cval_el0) 423 AARCH64REG_WRITE_INLINE(cntp_cval_el0) 424 AARCH64REG_READ_INLINE(cntp_tval_el0) 425 AARCH64REG_WRITE_INLINE(cntp_tval_el0) 426 AARCH64REG_READ_INLINE(cntpct_el0) 427 AARCH64REG_WRITE_INLINE(cntpct_el0) 428 429 AARCH64REG_READ_INLINE(cntps_ctl_el1) 430 AARCH64REG_WRITE_INLINE(cntps_ctl_el1) 431 AARCH64REG_READ_INLINE(cntps_cval_el1) 432 AARCH64REG_WRITE_INLINE(cntps_cval_el1) 433 AARCH64REG_READ_INLINE(cntps_tval_el1) 434 AARCH64REG_WRITE_INLINE(cntps_tval_el1) 435 436 AARCH64REG_READ_INLINE(cntv_ctl_el0) 437 AARCH64REG_WRITE_INLINE(cntv_ctl_el0) 438 AARCH64REG_READ_INLINE(cntv_cval_el0) 439 AARCH64REG_WRITE_INLINE(cntv_cval_el0) 440 AARCH64REG_READ_INLINE(cntv_tval_el0) 441 AARCH64REG_WRITE_INLINE(cntv_tval_el0) 442 AARCH64REG_READ_INLINE(cntvct_el0) 443 AARCH64REG_WRITE_INLINE(cntvct_el0) 444 445 static const uintmax_t 446 CNTCTL_ISTATUS = __BIT(2), // Interrupt Asserted 447 CNTCTL_IMASK = __BIT(1), // Timer Interrupt is Masked 448 CNTCTL_ENABLE = __BIT(0); // Timer Enabled 449 450 #elif defined(__arm__) 451 452 #include <arm/armreg.h> 453 454 #endif /* __aarch64__/__arm__ */ 455 456 #endif /* _AARCH64_ARMREG_H_ */ 457
Indexes created Thu Oct 02 07:10:07 GMT 2025