armreg.h revision 1.8
1 /* $NetBSD: armreg.h,v 1.8 2018/03/20 10:14:29 ryo Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AARCH64_ARMREG_H_ 33 #define _AARCH64_ARMREG_H_ 34 35 #ifdef __aarch64__ 36 37 #include <arm/cputypes.h> 38 #include <sys/types.h> 39 40 #define AARCH64REG_READ_INLINE2(regname, regdesc) \ 41 static uint64_t inline \ 42 reg_##regname##_read(void) \ 43 { \ 44 uint64_t __rv; \ 45 __asm __volatile("mrs %0, " #regdesc : "=r"(__rv)); \ 46 return __rv; \ 47 } 48 49 #define AARCH64REG_WRITE_INLINE2(regname, regdesc) \ 50 static void inline \ 51 reg_##regname##_write(uint64_t __val) \ 52 { \ 53 __asm __volatile("msr " #regdesc ", %0" :: "r"(__val)); \ 54 } 55 56 #define AARCH64REG_WRITEIMM_INLINE2(regname, regdesc) \ 57 static void inline \ 58 reg_##regname##_write(uint64_t __val) \ 59 { \ 60 __asm __volatile("msr " #regdesc ", %0" :: "n"(__val)); \ 61 } 62 63 #define AARCH64REG_READ_INLINE(regname) \ 64 AARCH64REG_READ_INLINE2(regname, regname) 65 66 #define AARCH64REG_WRITE_INLINE(regname) \ 67 AARCH64REG_WRITE_INLINE2(regname, regname) 68 69 #define AARCH64REG_WRITEIMM_INLINE(regname) \ 70 AARCH64REG_WRITEIMM_INLINE2(regname, regname) 71 /* 72 * System registers available at EL0 (user) 73 */ 74 AARCH64REG_READ_INLINE(ctr_el0) // Cache Type Register 75 76 static const uintmax_t 77 CTR_EL0_CWG_LINE = __BITS(27,24), // Cacheback Writeback Granule 78 CTR_EL0_ERG_LINE = __BITS(23,20), // Exclusives Reservation Granule 79 CTR_EL0_DMIN_LINE = __BITS(19,16), // Dcache MIN LINE size (log2 - 2) 80 CTR_EL0_L1IP_MASK = __BITS(15,14), 81 CTR_EL0_L1IP_AIVIVT = 1, // ASID-tagged Virtual Index, Virtual Tag 82 CTR_EL0_L1IP_VIPT = 2, // Virtual Index, Physical Tag 83 CTR_EL0_L1IP_PIPT = 3, // Physical Index, Physical Tag 84 CTR_EL0_IMIN_LINE = __BITS(3,0); // Icache MIN LINE size (log2 - 2) 85 86 AARCH64REG_READ_INLINE(dczid_el0) // Data Cache Zero ID Register 87 88 static const uintmax_t 89 DCZID_DZP = __BIT(4), // Data Zero Prohibited 90 DCZID_BS = __BITS(3,0); // Block Size (log2 - 2) 91 92 AARCH64REG_READ_INLINE(tpidrro_el0) // Thread Pointer ID Register (RO) 93 94 AARCH64REG_READ_INLINE(fpcr) // Floating Point Control Register 95 AARCH64REG_WRITE_INLINE(fpcr) 96 97 static const uintmax_t 98 FPCR_AHP = __BIT(26), // Alternative Half Precision 99 FPCR_DN = __BIT(25), // Default Nan Control 100 FPCR_FZ = __BIT(24), // Flush-To-Zero 101 FPCR_RMODE = __BITS(23,22),// Rounding Mode 102 FPCR_RN = 0, // Round Nearest 103 FPCR_RP = 1, // Round towards Plus infinity 104 FPCR_RM = 2, // Round towards Minus infinity 105 FPCR_RZ = 3, // Round towards Zero 106 FPCR_STRIDE = __BITS(21,20), 107 FPCR_LEN = __BITS(18,16), 108 FPCR_IDE = __BIT(15), // Input Denormal Exception enable 109 FPCR_IXE = __BIT(12), // IneXact Exception enable 110 FPCR_UFE = __BIT(11), // UnderFlow Exception enable 111 FPCR_OFE = __BIT(10), // OverFlow Exception enable 112 FPCR_DZE = __BIT(9), // Divide by Zero Exception enable 113 FPCR_IOE = __BIT(8), // Invalid Operation Exception enable 114 FPCR_ESUM = 0x1F00; 115 116 AARCH64REG_READ_INLINE(fpsr) // Floating Point Status Register 117 AARCH64REG_WRITE_INLINE(fpsr) 118 119 static const uintmax_t 120 FPSR_N32 = __BIT(31), // AARCH32 Negative 121 FPSR_Z32 = __BIT(30), // AARCH32 Zero 122 FPSR_C32 = __BIT(29), // AARCH32 Carry 123 FPSR_V32 = __BIT(28), // AARCH32 Overflow 124 FPSR_QC = __BIT(27), // SIMD Saturation 125 FPSR_IDC = __BIT(7), // Input Denormal Cumulative status 126 FPSR_IXC = __BIT(4), // IneXact Cumulative status 127 FPSR_UFC = __BIT(3), // UnderFlow Cumulative status 128 FPSR_OFC = __BIT(2), // OverFlow Cumulative status 129 FPSR_DZC = __BIT(1), // Divide by Zero Cumulative status 130 FPSR_IOC = __BIT(0), // Invalid Operation Cumulative status 131 FPSR_CSUM = 0x1F; 132 133 AARCH64REG_READ_INLINE(nzcv) // condition codes 134 AARCH64REG_WRITE_INLINE(nzcv) 135 136 static const uintmax_t 137 NZCV_N = __BIT(31), // Negative 138 NZCV_Z = __BIT(30), // Zero 139 NZCV_C = __BIT(29), // Carry 140 NZCV_V = __BIT(28); // Overflow 141 142 AARCH64REG_READ_INLINE(tpidr_el0) // Thread Pointer ID Register (RW) 143 AARCH64REG_WRITE_INLINE(tpidr_el0) 144 145 /* 146 * From here on, these can only be accessed at EL1 (kernel) 147 */ 148 149 /* 150 * These are readonly registers 151 */ 152 AARCH64REG_READ_INLINE2(cbar_el1, s3_1_c15_c3_0) // Cortex-A57 153 154 static const uintmax_t CBAR_PA = __BITS(47,18); 155 156 AARCH64REG_READ_INLINE(clidr_el1) 157 AARCH64REG_READ_INLINE(ccsidr_el1) 158 AARCH64REG_READ_INLINE(id_afr0_el1) 159 AARCH64REG_READ_INLINE(id_adr0_el1) 160 AARCH64REG_READ_INLINE(id_isar0_el1) 161 AARCH64REG_READ_INLINE(id_isar1_el1) 162 AARCH64REG_READ_INLINE(id_isar2_el1) 163 AARCH64REG_READ_INLINE(id_isar3_el1) 164 AARCH64REG_READ_INLINE(id_isar4_el1) 165 AARCH64REG_READ_INLINE(id_isar5_el1) 166 AARCH64REG_READ_INLINE(id_mmfr0_el1) 167 AARCH64REG_READ_INLINE(id_mmfr1_el1) 168 AARCH64REG_READ_INLINE(id_mmfr2_el1) 169 AARCH64REG_READ_INLINE(id_mmfr3_el1) 170 AARCH64REG_READ_INLINE(id_prf0_el1) 171 AARCH64REG_READ_INLINE(id_prf1_el1) 172 AARCH64REG_READ_INLINE(isr_el1) 173 AARCH64REG_READ_INLINE(midr_el1) 174 AARCH64REG_READ_INLINE(mpidr_el1) 175 AARCH64REG_READ_INLINE(mvfr0_el1) 176 AARCH64REG_READ_INLINE(mvfr1_el1) 177 AARCH64REG_READ_INLINE(mvfr2_el1) 178 AARCH64REG_READ_INLINE(revidr_el1) 179 180 /* 181 * These are read/write registers 182 */ 183 AARCH64REG_READ_INLINE(ccselr_el1) // Cache Size Selection Register 184 AARCH64REG_WRITE_INLINE(ccselr_el1) 185 186 AARCH64REG_READ_INLINE(cpacr_el1) // Coprocessor Access Control Regiser 187 AARCH64REG_WRITE_INLINE(cpacr_el1) 188 189 static const uintmax_t 190 CPACR_TTA = __BIT(28), // System Register Access Traps 191 CPACR_FPEN = __BITS(21,20), 192 CPACR_FPEN_NONE = __SHIFTIN(0, CPACR_FPEN), 193 CPACR_FPEN_EL1 = __SHIFTIN(1, CPACR_FPEN), 194 CPACR_FPEN_NONE_2 = __SHIFTIN(2, CPACR_FPEN), 195 CPACR_FPEN_ALL = __SHIFTIN(3, CPACR_FPEN); 196 197 AARCH64REG_READ_INLINE(elr_el1) // Exception Link Register 198 AARCH64REG_WRITE_INLINE(elr_el1) 199 200 AARCH64REG_READ_INLINE(esr_el1) // Exception Symdrone Register 201 AARCH64REG_WRITE_INLINE(esr_el1) 202 203 static const uintmax_t 204 ESR_EC = __BITS(31,26), // Exception Cause 205 ESR_EC_UNKNOWN = 0x00, // AXX: Unknown Reason 206 ESR_EC_WFX = 0x01, // AXX: WFI or WFE instruction execution 207 ESR_EC_CP15_RT = 0x03, // A32: MCR/MRC access to CP15 !EC=0 208 ESR_EC_CP15_RRT = 0x04, // A32: MCRR/MRRC access to CP15 !EC=0 209 ESR_EC_CP14_RT = 0x05, // A32: MCR/MRC access to CP14 210 ESR_EC_CP14_DT = 0x06, // A32: LDC/STC access to CP14 211 ESR_EC_FP_ACCESS = 0x07, // AXX: Access to SIMD/FP Registers 212 ESR_EC_FPID = 0x08, // A32: MCR/MRC access to CP10 !EC=7 213 ESR_EC_CP14_RRT = 0x0c, // A32: MRRC access to CP14 214 ESR_EC_ILL_STATE = 0x0e, // AXX: Illegal Execution State 215 ESR_EC_SVC_A32 = 0x11, // A32: SVC Instruction Execution 216 ESR_EC_HVC_A32 = 0x12, // A32: HVC Instruction Execution 217 ESR_EC_SMC_A32 = 0x13, // A32: SMC Instruction Execution 218 ESR_EC_SVC_A64 = 0x15, // A64: SVC Instruction Execution 219 ESR_EC_HVC_A64 = 0x16, // A64: HVC Instruction Execution 220 ESR_EC_SMC_A64 = 0x17, // A64: SMC Instruction Execution 221 ESR_EC_SYS_REG = 0x18, // A64: MSR/MRS/SYS instruction (!EC0/1/7) 222 ESR_EC_INSN_ABT_EL0 = 0x20, // AXX: Instruction Abort (EL0) 223 ESR_EC_INSN_ABT_EL1 = 0x21, // AXX: Instruction Abort (EL1) 224 ESR_EC_PC_ALIGNMENT = 0x22, // AXX: Misaligned PC 225 ESR_EC_DATA_ABT_EL0 = 0x24, // AXX: Data Abort (EL0) 226 ESR_EC_DATA_ABT_EL1 = 0x25, // AXX: Data Abort (EL1) 227 ESR_EC_SP_ALIGNMENT = 0x26, // AXX: Misaligned SP 228 ESR_EC_FP_TRAP_A32 = 0x28, // A32: FP Exception 229 ESR_EC_FP_TRAP_A64 = 0x2c, // A64: FP Exception 230 ESR_EC_SERROR = 0x2f, // AXX: SError Interrupt 231 ESR_EC_BRKPNT_EL0 = 0x30, // AXX: Breakpoint Exception (EL0) 232 ESR_EC_BRKPNT_EL1 = 0x31, // AXX: Breakpoint Exception (EL1) 233 ESR_EC_SW_STEP_EL0 = 0x32, // AXX: Software Step (EL0) 234 ESR_EC_SW_STEP_EL1 = 0x33, // AXX: Software Step (EL1) 235 ESR_EC_WTCHPNT_EL0 = 0x34, // AXX: Watchpoint (EL0) 236 ESR_EC_WTCHPNT_EL1 = 0x35, // AXX: Watchpoint (EL1) 237 ESR_EC_BKPT_INSN_A32 = 0x38, // A32: BKPT Instruction Execution 238 ESR_EC_VECTOR_CATCH = 0x3a, // A32: Vector Catch Exception 239 ESR_EC_BKPT_INSN_A64 = 0x3c, // A64: BKPT Instruction Execution 240 ESR_IL = __BIT(25), // Instruction Length (1=32-bit) 241 ESR_ISS = __BITS(24,0); // Instruction Specific Syndrome 242 243 244 AARCH64REG_READ_INLINE(far_el1) // Fault Address Register 245 AARCH64REG_WRITE_INLINE(far_el1) 246 247 AARCH64REG_READ_INLINE(mair_el1) // Main Id Register 248 AARCH64REG_WRITE_INLINE(mair_el1) 249 250 AARCH64REG_READ_INLINE(par_el1) // Physical Address Register 251 AARCH64REG_WRITE_INLINE(par_el1) 252 253 static const uintmax_t 254 PAR_ATTR = __BITS(63,56),// F=0 memory attributes 255 PAR_PA = __BITS(47,12),// F=0 physical address 256 PAR_NS = __BIT(9), // F=0 non-secure 257 PAR_S = __BIT(9), // F=1 failure stage 258 PAR_SHA = __BITS(8,7), // F=0 shareability attribute 259 PAR_SHA_NONE = 0, 260 PAR_SHA_OUTER = 2, 261 PAR_SHA_INNER = 3, 262 PAR_PTW = __BIT(8), // F=1 partial table walk 263 PAR_FST = __BITS(6,1), // F=1 fault status code 264 PAR_F = __BIT(0); // translation failed 265 266 AARCH64REG_READ_INLINE(rmr_el1) // Reset Management Register 267 AARCH64REG_WRITE_INLINE(rmr_el1) 268 269 AARCH64REG_READ_INLINE(rvbar_el1) // Reset Vector Base Address Register 270 AARCH64REG_WRITE_INLINE(rvbar_el1) 271 272 AARCH64REG_READ_INLINE(sctlr_el1) // System Control Register 273 AARCH64REG_WRITE_INLINE(sctlr_el1) 274 275 AARCH64REG_READ_INLINE(sp_el0) // Stack Pointer 276 AARCH64REG_WRITE_INLINE(sp_el0) 277 278 AARCH64REG_READ_INLINE(daif) // Debug Async Irq Fiq mask register 279 AARCH64REG_WRITE_INLINE(daif) 280 AARCH64REG_WRITEIMM_INLINE(daifclr) 281 AARCH64REG_WRITEIMM_INLINE(daifset) 282 283 static const uintmax_t 284 DAIF_D = __BIT(3), // Debug Exception Mask 285 DAIF_A = __BIT(2), // SError Abort Mask 286 DAIF_I = __BIT(1), // IRQ Mask 287 DAIF_F = __BIT(0); // FIQ Mask 288 289 AARCH64REG_READ_INLINE(spsr_el1) // Saved Program Status Register 290 AARCH64REG_WRITE_INLINE(spsr_el1) 291 292 static const uintmax_t 293 SPSR_NZCV = __BITS(31,28), // mask of N Z C V 294 SPSR_N = __BIT(31), // Negative 295 SPSR_Z = __BIT(30), // Zero 296 SPSR_C = __BIT(29), // Carry 297 SPSR_V = __BIT(28), // oVerflow 298 SPSR_A32_Q = __BIT(27), // A32: Overflow 299 SPSR_A32_J = __BIT(24), // A32: Jazelle Mode 300 SPSR_A32_IT1 = __BIT(23), // A32: IT[1] 301 SPSR_A32_IT0 = __BIT(22), // A32: IT[0] 302 SPSR_SS = __BIT(21), // Software Step 303 SPSR_IL = __BIT(20), // Instruction Length 304 SPSR_GE = __BITS(19,16), // A32: SIMD GE 305 SPSR_IT7 = __BIT(15), // A32: IT[7] 306 SPSR_IT6 = __BIT(14), // A32: IT[6] 307 SPSR_IT5 = __BIT(13), // A32: IT[5] 308 SPSR_IT4 = __BIT(12), // A32: IT[4] 309 SPSR_IT3 = __BIT(11), // A32: IT[3] 310 SPSR_IT2 = __BIT(10), // A32: IT[2] 311 SPSR_A64_D = __BIT(9), // A64: Debug Exception Mask 312 SPSR_A32_E = __BIT(9), // A32: BE Endian Mode 313 SPSR_A = __BIT(8), // Async abort (SError) Mask 314 SPSR_I = __BIT(7), // IRQ Mask 315 SPSR_F = __BIT(6), // FIQ Mask 316 SPSR_A32_T = __BIT(5), // A32 Thumb Mode 317 SPSR_M = __BITS(4,0), // Execution State 318 SPSR_M_EL3H = 0x0d, 319 SPSR_M_EL3T = 0x0c, 320 SPSR_M_EL2H = 0x09, 321 SPSR_M_EL2T = 0x08, 322 SPSR_M_EL1H = 0x05, 323 SPSR_M_EL1T = 0x04, 324 SPSR_M_EL0T = 0x00, 325 SPSR_M_SYS32 = 0x1f, 326 SPSR_M_UND32 = 0x1b, 327 SPSR_M_ABT32 = 0x17, 328 SPSR_M_SVC32 = 0x13, 329 SPSR_M_IRQ32 = 0x12, 330 SPSR_M_FIQ32 = 0x11, 331 SPSR_M_USR32 = 0x10; 332 333 AARCH64REG_READ_INLINE(tcr_el1) // Translation Control Register 334 AARCH64REG_WRITE_INLINE(tcr_el1) 335 336 static const uintmax_t 337 TCR_TBI1 = __BIT(38), // ignore Top Byte for TTBR1_EL1 338 TCR_TBI0 = __BIT(37), // ignore Top Byte for TTBR0_EL1 339 TCR_AS64K = __BIT(36), // Use 64K ASIDs 340 TCR_IPS = __BITS(34,32), // Intermediate Phys Addr Size 341 TCR_IPS_256TB = 5, // 48 bits (256 TB) 342 TCR_IPS_64TB = 4, // 44 bits (16 TB) 343 TCR_IPS_4TB = 3, // 42 bits ( 4 TB) 344 TCR_IPS_1TB = 2, // 40 bits ( 1 TB) 345 TCR_IPS_64GB = 1, // 36 bits (64 GB) 346 TCR_IPS_4GB = 0, // 32 bits (4 GB) 347 TCR_TG1 = __BITS(31,30), // Page Granule Size 348 TCR_TG_4KB = 1, // 4KB page size 349 TCR_TG_16KB = 2, // 16KB page size 350 TCR_TG_64KB = 3, // 64KB page size 351 TCR_SH1 = __BITS(29,28), 352 TCR_SH_NONE = 0, 353 TCR_SH_OUTER = 1, 354 TCR_SH_INNER = 2, 355 TCR_ORGN1 = __BITS(27,26), 356 TCR_XRGN_NC = 0, // Non Cacheable 357 TCR_XRGN_WB_WA = 1, // WriteBack WriteAllocate 358 TCR_XRGN_WT = 2, // WriteThrough 359 TCR_XRGN_WB = 3, // WriteBack 360 TCR_IRGN1 = __BITS(25,24), 361 TCR_EPD1 = __BIT(23), // Walk Disable for TTBR1_EL1 362 TCR_A1 = __BIT(22), // ASID is in TTBR1_EL1 363 TCR_T1SZ = __BITS(21,16), // Size offset for TTBR1_EL1 364 TCR_TG0 = __BITS(15,14), 365 TCR_SH0 = __BITS(13,12), 366 TCR_ORGN0 = __BITS(11,10), 367 TCR_IRGN0 = __BITS(9,8), 368 TCR_EPD0 = __BIT(7), // Walk Disable for TTBR0 369 TCR_T0SZ = __BITS(5,0); // Size offset for TTBR0_EL1 370 371 #define TCR_PAGE_SIZE1(tcr) (1L << (__SHIFTOUT(tcr, TCR_TG1) * 2 + 10)) 372 373 AARCH64REG_READ_INLINE(tpidr_el1) // Thread ID Register (EL1) 374 AARCH64REG_WRITE_INLINE(tpidr_el1) 375 376 AARCH64REG_WRITE_INLINE(tpidrro_el0) // Thread ID Register (RO for EL0) 377 378 AARCH64REG_READ_INLINE(ttbr0_el0) // Translation Table Base Register 0 EL0 379 AARCH64REG_WRITE_INLINE(ttbr0_el0) 380 381 AARCH64REG_READ_INLINE(ttbr0_el1) // Translation Table Base Register 0 EL0 382 AARCH64REG_WRITE_INLINE(ttbr0_el1) 383 384 AARCH64REG_READ_INLINE(ttbr1_el1) // Translation Table Base Register 1 EL1 385 AARCH64REG_WRITE_INLINE(ttbr1_el1) 386 387 static const uint64_t 388 TTBR_ASID = __BITS(63, 48), 389 TTBR_BADDR = __BITS(47, 0); 390 391 AARCH64REG_READ_INLINE(vbar_el1) // Vector Base Address Register 392 AARCH64REG_WRITE_INLINE(vbar_el1) 393 394 AARCH64REG_READ_INLINE(pmccfiltr_el0) 395 AARCH64REG_WRITE_INLINE(pmccfiltr_el0) 396 397 static const uintmax_t 398 PMCCFILTR_P = __BIT(31), // Don't count cycles in EL1 399 PMCCFILTR_U = __BIT(30), // Don't count cycles in EL0 400 PMCCFILTR_NSK = __BIT(29), // Don't count cycles in NS EL1 401 PMCCFILTR_NSU = __BIT(28), // Don't count cycles in NS EL0 402 PMCCFILTR_NSH = __BIT(27), // Don't count cycles in NS EL2 403 PMCCFILTR_M = __BIT(26); // Don't count cycles in EL3 404 405 AARCH64REG_READ_INLINE(pmccntr_el0) 406 407 AARCH64REG_READ_INLINE(cntfrq_el0) 408 409 AARCH64REG_READ_INLINE(cntkctl_el1) 410 AARCH64REG_WRITE_INLINE(cntkctl_el1) 411 412 static const uintmax_t 413 CNTKCTL_EL0PTEN = __BIT(9), // EL0 access for CNTP CVAL/TVAL/CTL 414 CNTKCTL_EL0VTEN = __BIT(8), // EL0 access for CNTV CVAL/TVAL/CTL 415 CNTKCTL_ELNTI = __BITS(7,4), 416 CNTKCTL_EVNTDIR = __BIT(3), 417 CNTKCTL_EVNTEN = __BIT(2), 418 CNTKCTL_EL0VCTEN = __BIT(1), // EL0 access for CNTVCT and CNTFRQ 419 CNTKCTL_EL0PCTEN = __BIT(0); // EL0 access for CNTPCT and CNTFRQ 420 421 AARCH64REG_READ_INLINE(cntp_ctl_el0) 422 AARCH64REG_WRITE_INLINE(cntp_ctl_el0) 423 AARCH64REG_READ_INLINE(cntp_cval_el0) 424 AARCH64REG_WRITE_INLINE(cntp_cval_el0) 425 AARCH64REG_READ_INLINE(cntp_tval_el0) 426 AARCH64REG_WRITE_INLINE(cntp_tval_el0) 427 AARCH64REG_READ_INLINE(cntpct_el0) 428 AARCH64REG_WRITE_INLINE(cntpct_el0) 429 430 AARCH64REG_READ_INLINE(cntps_ctl_el1) 431 AARCH64REG_WRITE_INLINE(cntps_ctl_el1) 432 AARCH64REG_READ_INLINE(cntps_cval_el1) 433 AARCH64REG_WRITE_INLINE(cntps_cval_el1) 434 AARCH64REG_READ_INLINE(cntps_tval_el1) 435 AARCH64REG_WRITE_INLINE(cntps_tval_el1) 436 437 AARCH64REG_READ_INLINE(cntv_ctl_el0) 438 AARCH64REG_WRITE_INLINE(cntv_ctl_el0) 439 AARCH64REG_READ_INLINE(cntv_cval_el0) 440 AARCH64REG_WRITE_INLINE(cntv_cval_el0) 441 AARCH64REG_READ_INLINE(cntv_tval_el0) 442 AARCH64REG_WRITE_INLINE(cntv_tval_el0) 443 AARCH64REG_READ_INLINE(cntvct_el0) 444 AARCH64REG_WRITE_INLINE(cntvct_el0) 445 446 static const uintmax_t 447 CNTCTL_ISTATUS = __BIT(2), // Interrupt Asserted 448 CNTCTL_IMASK = __BIT(1), // Timer Interrupt is Masked 449 CNTCTL_ENABLE = __BIT(0); // Timer Enabled 450 451 #elif defined(__arm__) 452 453 #include <arm/armreg.h> 454 455 #endif /* __aarch64__/__arm__ */ 456 457 #endif /* _AARCH64_ARMREG_H_ */ 458
Indexes created Thu Oct 02 01:09:59 GMT 2025