pmap.h revision 1.39 1 1.39 skrll /* $NetBSD: pmap.h,v 1.39 2020/05/14 07:59:03 skrll Exp $ */
2 1.1 matt
3 1.1 matt /*-
4 1.1 matt * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 1.1 matt * All rights reserved.
6 1.1 matt *
7 1.1 matt * This code is derived from software contributed to The NetBSD Foundation
8 1.1 matt * by Matt Thomas of 3am Software Foundry.
9 1.1 matt *
10 1.1 matt * Redistribution and use in source and binary forms, with or without
11 1.1 matt * modification, are permitted provided that the following conditions
12 1.1 matt * are met:
13 1.1 matt * 1. Redistributions of source code must retain the above copyright
14 1.1 matt * notice, this list of conditions and the following disclaimer.
15 1.1 matt * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 matt * notice, this list of conditions and the following disclaimer in the
17 1.1 matt * documentation and/or other materials provided with the distribution.
18 1.1 matt *
19 1.1 matt * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 1.1 matt * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 1.1 matt * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 1.1 matt * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 1.1 matt * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 1.1 matt * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 1.1 matt * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 1.1 matt * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 1.1 matt * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 1.1 matt * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 1.1 matt * POSSIBILITY OF SUCH DAMAGE.
30 1.1 matt */
31 1.1 matt
32 1.1 matt #ifndef _AARCH64_PMAP_H_
33 1.1 matt #define _AARCH64_PMAP_H_
34 1.1 matt
35 1.1 matt #ifdef __aarch64__
36 1.1 matt
37 1.10 jakllsch #ifdef _KERNEL
38 1.17 maxv #ifdef _KERNEL_OPT
39 1.17 maxv #include "opt_kasan.h"
40 1.17 maxv #endif
41 1.17 maxv
42 1.1 matt #include <sys/types.h>
43 1.1 matt #include <sys/pool.h>
44 1.2 ryo #include <sys/queue.h>
45 1.2 ryo #include <uvm/uvm_pglist.h>
46 1.1 matt
47 1.36 ryo #include <aarch64/armreg.h>
48 1.2 ryo #include <aarch64/pte.h>
49 1.1 matt
50 1.26 maya #define PMAP_NEED_PROCWR
51 1.1 matt #define PMAP_GROWKERNEL
52 1.1 matt #define PMAP_STEAL_MEMORY
53 1.1 matt
54 1.2 ryo #define __HAVE_VM_PAGE_MD
55 1.33 ryo #define __HAVE_PMAP_PV_TRACK 1
56 1.2 ryo
57 1.17 maxv #ifndef KASAN
58 1.15 ryo #define PMAP_MAP_POOLPAGE(pa) AARCH64_PA_TO_KVA(pa)
59 1.15 ryo #define PMAP_UNMAP_POOLPAGE(va) AARCH64_KVA_TO_PA(va)
60 1.20 jdolecek
61 1.20 jdolecek #define PMAP_DIRECT
62 1.20 jdolecek static __inline int
63 1.20 jdolecek pmap_direct_process(paddr_t pa, voff_t pgoff, size_t len,
64 1.20 jdolecek int (*process)(void *, size_t, void *), void *arg)
65 1.20 jdolecek {
66 1.20 jdolecek vaddr_t va = AARCH64_PA_TO_KVA(pa);
67 1.20 jdolecek
68 1.20 jdolecek return process((void *)(va + pgoff), len, arg);
69 1.20 jdolecek }
70 1.17 maxv #endif
71 1.15 ryo
72 1.1 matt struct pmap {
73 1.2 ryo kmutex_t pm_lock;
74 1.1 matt struct pool *pm_pvpool;
75 1.2 ryo pd_entry_t *pm_l0table; /* L0 table: 512G*512 */
76 1.2 ryo paddr_t pm_l0table_pa;
77 1.2 ryo
78 1.34 ryo LIST_HEAD(, vm_page) pm_vmlist; /* for L[0123] tables */
79 1.2 ryo
80 1.1 matt struct pmap_statistics pm_stats;
81 1.2 ryo unsigned int pm_refcnt;
82 1.24 ryo unsigned int pm_idlepdp;
83 1.2 ryo int pm_asid;
84 1.2 ryo bool pm_activated;
85 1.1 matt };
86 1.1 matt
87 1.2 ryo struct pv_entry;
88 1.32 ryo
89 1.32 ryo struct pmap_page {
90 1.32 ryo kmutex_t pp_pvlock;
91 1.34 ryo LIST_HEAD(, pv_entry) pp_pvhead;
92 1.32 ryo
93 1.32 ryo /* VM_PROT_READ means referenced, VM_PROT_WRITE means modified */
94 1.32 ryo uint32_t pp_flags;
95 1.32 ryo };
96 1.32 ryo
97 1.2 ryo struct vm_page_md {
98 1.34 ryo LIST_ENTRY(vm_page) mdpg_vmlist; /* L[0123] table vm_page list */
99 1.22 ryo pd_entry_t *mdpg_ptep_parent; /* for page descriptor page only */
100 1.22 ryo
101 1.32 ryo struct pmap_page mdpg_pp;
102 1.1 matt };
103 1.1 matt
104 1.32 ryo #define VM_MDPAGE_INIT(pg) \
105 1.32 ryo do { \
106 1.39 skrll (pg)->mdpage.mdpg_ptep_parent = NULL; \
107 1.39 skrll PMAP_PAGE_INIT(&(pg)->mdpage.mdpg_pp); \
108 1.1 matt } while (/*CONSTCOND*/ 0)
109 1.1 matt
110 1.37 ryo #define PMAP_PAGE_INIT(pp) \
111 1.37 ryo do { \
112 1.39 skrll mutex_init(&(pp)->pp_pvlock, MUTEX_NODEBUG, IPL_VM); \
113 1.39 skrll LIST_INIT(&(pp)->pp_pvhead); \
114 1.39 skrll (pp)->pp_flags = 0; \
115 1.37 ryo } while (/*CONSTCOND*/ 0)
116 1.11 ryo
117 1.11 ryo /* saved permission bit for referenced/modified emulation */
118 1.11 ryo #define LX_BLKPAG_OS_READ LX_BLKPAG_OS_0
119 1.11 ryo #define LX_BLKPAG_OS_WRITE LX_BLKPAG_OS_1
120 1.11 ryo #define LX_BLKPAG_OS_WIRED LX_BLKPAG_OS_2
121 1.11 ryo #define LX_BLKPAG_OS_BOOT LX_BLKPAG_OS_3
122 1.11 ryo #define LX_BLKPAG_OS_RWMASK (LX_BLKPAG_OS_WRITE|LX_BLKPAG_OS_READ)
123 1.11 ryo
124 1.11 ryo /* memory attributes are configured MAIR_EL1 in locore */
125 1.11 ryo #define LX_BLKPAG_ATTR_NORMAL_WB __SHIFTIN(0, LX_BLKPAG_ATTR_INDX)
126 1.11 ryo #define LX_BLKPAG_ATTR_NORMAL_NC __SHIFTIN(1, LX_BLKPAG_ATTR_INDX)
127 1.11 ryo #define LX_BLKPAG_ATTR_NORMAL_WT __SHIFTIN(2, LX_BLKPAG_ATTR_INDX)
128 1.11 ryo #define LX_BLKPAG_ATTR_DEVICE_MEM __SHIFTIN(3, LX_BLKPAG_ATTR_INDX)
129 1.28 jmcneill #define LX_BLKPAG_ATTR_DEVICE_MEM_SO __SHIFTIN(4, LX_BLKPAG_ATTR_INDX)
130 1.11 ryo #define LX_BLKPAG_ATTR_MASK LX_BLKPAG_ATTR_INDX
131 1.11 ryo
132 1.13 ryo #define lxpde_pa(pde) ((paddr_t)((pde) & LX_TBL_PA))
133 1.21 ryo #define lxpde_valid(pde) (((pde) & LX_VALID) == LX_VALID)
134 1.13 ryo #define l0pde_pa(pde) lxpde_pa(pde)
135 1.2 ryo #define l0pde_index(v) (((vaddr_t)(v) & L0_ADDR_BITS) >> L0_SHIFT)
136 1.21 ryo #define l0pde_valid(pde) lxpde_valid(pde)
137 1.2 ryo /* l0pte always contains table entries */
138 1.2 ryo
139 1.13 ryo #define l1pde_pa(pde) lxpde_pa(pde)
140 1.2 ryo #define l1pde_index(v) (((vaddr_t)(v) & L1_ADDR_BITS) >> L1_SHIFT)
141 1.21 ryo #define l1pde_valid(pde) lxpde_valid(pde)
142 1.2 ryo #define l1pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK)
143 1.2 ryo #define l1pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL)
144 1.2 ryo
145 1.13 ryo #define l2pde_pa(pde) lxpde_pa(pde)
146 1.2 ryo #define l2pde_index(v) (((vaddr_t)(v) & L2_ADDR_BITS) >> L2_SHIFT)
147 1.21 ryo #define l2pde_valid(pde) lxpde_valid(pde)
148 1.2 ryo #define l2pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK)
149 1.2 ryo #define l2pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL)
150 1.2 ryo
151 1.13 ryo #define l3pte_pa(pde) lxpde_pa(pde)
152 1.8 ryo #define l3pte_executable(pde,user) \
153 1.8 ryo (((pde) & ((user) ? LX_BLKPAG_UXN : LX_BLKPAG_PXN)) == 0)
154 1.6 ryo #define l3pte_readable(pde) ((pde) & LX_BLKPAG_AF)
155 1.6 ryo #define l3pte_writable(pde) \
156 1.6 ryo (((pde) & (LX_BLKPAG_AF|LX_BLKPAG_AP)) == (LX_BLKPAG_AF|LX_BLKPAG_AP_RW))
157 1.2 ryo #define l3pte_index(v) (((vaddr_t)(v) & L3_ADDR_BITS) >> L3_SHIFT)
158 1.21 ryo #define l3pte_valid(pde) lxpde_valid(pde)
159 1.2 ryo #define l3pte_is_page(pde) (((pde) & LX_TYPE) == L3_TYPE_PAG)
160 1.2 ryo /* l3pte contains always page entries */
161 1.2 ryo
162 1.2 ryo void pmap_bootstrap(vaddr_t, vaddr_t);
163 1.2 ryo bool pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, bool user);
164 1.7 ryo
165 1.7 ryo /* for ddb */
166 1.12 ryo void pmap_db_pteinfo(vaddr_t, void (*)(const char *, ...) __printflike(1, 2));
167 1.23 ryo void pmap_db_ttbrdump(bool, vaddr_t, void (*)(const char *, ...)
168 1.23 ryo __printflike(1, 2));
169 1.7 ryo pt_entry_t *kvtopte(vaddr_t);
170 1.7 ryo pt_entry_t pmap_kvattr(vaddr_t, vm_prot_t);
171 1.2 ryo
172 1.12 ryo /* locore.S */
173 1.12 ryo pd_entry_t *bootpage_alloc(void);
174 1.12 ryo
175 1.12 ryo /* pmap_locore.c */
176 1.12 ryo int pmapboot_enter(vaddr_t, paddr_t, psize_t, psize_t,
177 1.12 ryo pt_entry_t, uint64_t, pd_entry_t *(*)(void),
178 1.12 ryo void (*pr)(const char *, ...) __printflike(1, 2));
179 1.12 ryo #define PMAPBOOT_ENTER_NOBLOCK 0x00000001
180 1.12 ryo #define PMAPBOOT_ENTER_NOOVERWRITE 0x00000002
181 1.35 ryo int pmapboot_enter_range(vaddr_t, paddr_t, psize_t, pt_entry_t, uint64_t,
182 1.35 ryo pd_entry_t *(*)(void), void (*)(const char *, ...) __printflike(1, 2));
183 1.12 ryo int pmapboot_protect(vaddr_t, vaddr_t, vm_prot_t);
184 1.12 ryo void pmap_db_pte_print(pt_entry_t, int,
185 1.12 ryo void (*pr)(const char *, ...) __printflike(1, 2));
186 1.12 ryo
187 1.2 ryo /* Hooks for the pool allocator */
188 1.2 ryo paddr_t vtophys(vaddr_t);
189 1.2 ryo #define VTOPHYS_FAILED ((paddr_t)-1L) /* POOL_PADDR_INVALID */
190 1.2 ryo #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va))
191 1.2 ryo
192 1.2 ryo
193 1.2 ryo /* devmap */
194 1.2 ryo struct pmap_devmap {
195 1.2 ryo vaddr_t pd_va; /* virtual address */
196 1.2 ryo paddr_t pd_pa; /* physical address */
197 1.2 ryo psize_t pd_size; /* size of region */
198 1.2 ryo vm_prot_t pd_prot; /* protection code */
199 1.2 ryo u_int pd_flags; /* flags for pmap_kenter_pa() */
200 1.2 ryo };
201 1.2 ryo
202 1.2 ryo void pmap_devmap_register(const struct pmap_devmap *);
203 1.16 skrll void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *);
204 1.2 ryo const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
205 1.2 ryo const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
206 1.2 ryo vaddr_t pmap_devmap_phystov(paddr_t);
207 1.2 ryo paddr_t pmap_devmap_vtophys(paddr_t);
208 1.2 ryo
209 1.24 ryo paddr_t pmap_alloc_pdp(struct pmap *, struct vm_page **, int, bool);
210 1.9 maxv
211 1.11 ryo #define L1_TRUNC_BLOCK(x) ((x) & L1_FRAME)
212 1.11 ryo #define L1_ROUND_BLOCK(x) L1_TRUNC_BLOCK((x) + L1_SIZE - 1)
213 1.11 ryo #define L2_TRUNC_BLOCK(x) ((x) & L2_FRAME)
214 1.11 ryo #define L2_ROUND_BLOCK(x) L2_TRUNC_BLOCK((x) + L2_SIZE - 1)
215 1.29 skrll #define L3_TRUNC_BLOCK(x) ((x) & L3_FRAME)
216 1.29 skrll #define L3_ROUND_BLOCK(x) L3_TRUNC_BLOCK((x) + L3_SIZE - 1)
217 1.11 ryo
218 1.30 skrll #define DEVMAP_ALIGN(x) L3_TRUNC_BLOCK((x))
219 1.30 skrll #define DEVMAP_SIZE(x) L3_ROUND_BLOCK((x))
220 1.2 ryo
221 1.2 ryo #define DEVMAP_ENTRY(va, pa, sz) \
222 1.2 ryo { \
223 1.30 skrll .pd_va = DEVMAP_ALIGN(va), \
224 1.30 skrll .pd_pa = DEVMAP_ALIGN(pa), \
225 1.30 skrll .pd_size = DEVMAP_SIZE(sz), \
226 1.2 ryo .pd_prot = VM_PROT_READ|VM_PROT_WRITE, \
227 1.25 skrll .pd_flags = PMAP_DEV \
228 1.2 ryo }
229 1.2 ryo #define DEVMAP_ENTRY_END { 0 }
230 1.2 ryo
231 1.2 ryo /* mmap cookie and flags */
232 1.2 ryo #define AARCH64_MMAP_FLAG_SHIFT (64 - PGSHIFT)
233 1.2 ryo #define AARCH64_MMAP_FLAG_MASK 0xf
234 1.3 jmcneill #define AARCH64_MMAP_WRITEBACK 0UL
235 1.3 jmcneill #define AARCH64_MMAP_NOCACHE 1UL
236 1.3 jmcneill #define AARCH64_MMAP_WRITECOMBINE 2UL
237 1.3 jmcneill #define AARCH64_MMAP_DEVICE 3UL
238 1.2 ryo
239 1.5 jmcneill #define ARM_MMAP_MASK __BITS(63, AARCH64_MMAP_FLAG_SHIFT)
240 1.5 jmcneill #define ARM_MMAP_WRITECOMBINE __SHIFTIN(AARCH64_MMAP_WRITECOMBINE, ARM_MMAP_MASK)
241 1.5 jmcneill #define ARM_MMAP_WRITEBACK __SHIFTIN(AARCH64_MMAP_WRITEBACK, ARM_MMAP_MASK)
242 1.5 jmcneill #define ARM_MMAP_NOCACHE __SHIFTIN(AARCH64_MMAP_NOCACHE, ARM_MMAP_MASK)
243 1.5 jmcneill #define ARM_MMAP_DEVICE __SHIFTIN(AARCH64_MMAP_DEVICE, ARM_MMAP_MASK)
244 1.2 ryo
245 1.2 ryo #define PMAP_PTE 0x10000000 /* kenter_pa */
246 1.2 ryo #define PMAP_DEV 0x20000000 /* kenter_pa */
247 1.28 jmcneill #define PMAP_DEV_SO 0x40000000 /* kenter_pa */
248 1.28 jmcneill #define PMAP_DEV_MASK (PMAP_DEV | PMAP_DEV_SO)
249 1.2 ryo
250 1.2 ryo static inline u_int
251 1.2 ryo aarch64_mmap_flags(paddr_t mdpgno)
252 1.2 ryo {
253 1.2 ryo u_int nflag, pflag;
254 1.2 ryo
255 1.2 ryo /*
256 1.28 jmcneill * aarch64 arch has 5 memory attribute:
257 1.2 ryo *
258 1.2 ryo * WriteBack - write back cache
259 1.31 skrll * WriteThru - write through cache
260 1.2 ryo * NoCache - no cache
261 1.27 jmcneill * Device(nGnRE) - no Gathering, no Reordering, Early write ack
262 1.28 jmcneill * Device(nGnRnE) - no Gathering, no Reordering, no Early write ack
263 1.2 ryo *
264 1.2 ryo * but pmap has PMAP_{NOCACHE,WRITE_COMBINE,WRITE_BACK} flags.
265 1.2 ryo */
266 1.2 ryo
267 1.2 ryo nflag = (mdpgno >> AARCH64_MMAP_FLAG_SHIFT) & AARCH64_MMAP_FLAG_MASK;
268 1.2 ryo switch (nflag) {
269 1.2 ryo case AARCH64_MMAP_DEVICE:
270 1.2 ryo pflag = PMAP_DEV;
271 1.2 ryo break;
272 1.2 ryo case AARCH64_MMAP_WRITECOMBINE:
273 1.2 ryo pflag = PMAP_WRITE_COMBINE;
274 1.2 ryo break;
275 1.2 ryo case AARCH64_MMAP_WRITEBACK:
276 1.2 ryo pflag = PMAP_WRITE_BACK;
277 1.2 ryo break;
278 1.2 ryo case AARCH64_MMAP_NOCACHE:
279 1.2 ryo default:
280 1.2 ryo pflag = PMAP_NOCACHE;
281 1.2 ryo break;
282 1.2 ryo }
283 1.2 ryo return pflag;
284 1.2 ryo }
285 1.2 ryo
286 1.2 ryo #define pmap_phys_address(pa) aarch64_ptob((pa))
287 1.2 ryo #define pmap_mmap_flags(ppn) aarch64_mmap_flags((ppn))
288 1.2 ryo
289 1.2 ryo #define pmap_update(pmap) ((void)0)
290 1.2 ryo #define pmap_copy(dp,sp,d,l,s) ((void)0)
291 1.2 ryo #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
292 1.2 ryo #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
293 1.2 ryo
294 1.26 maya void pmap_procwr(struct proc *, vaddr_t, int);
295 1.2 ryo bool pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *);
296 1.14 ryo void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t);
297 1.2 ryo
298 1.33 ryo void pmap_pv_init(void);
299 1.33 ryo void pmap_pv_track(paddr_t, psize_t);
300 1.33 ryo void pmap_pv_untrack(paddr_t, psize_t);
301 1.33 ryo void pmap_pv_protect(paddr_t, vm_prot_t);
302 1.33 ryo
303 1.2 ryo #define PMAP_MAPSIZE1 L2_SIZE
304 1.2 ryo
305 1.10 jakllsch #endif /* _KERNEL */
306 1.10 jakllsch
307 1.1 matt #elif defined(__arm__)
308 1.1 matt
309 1.1 matt #include <arm/pmap.h>
310 1.1 matt
311 1.2 ryo #endif /* __arm__/__aarch64__ */
312 1.1 matt
313 1.2 ryo #endif /* !_AARCH64_PMAP_ */
314