pmap.h revision 1.11 1 /* $NetBSD: pmap.h,v 1.11 2018/10/04 09:09:29 ryo Exp $ */
2
3 /*-
4 * Copyright (c) 2014 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Matt Thomas of 3am Software Foundry.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef _AARCH64_PMAP_H_
33 #define _AARCH64_PMAP_H_
34
35 #ifdef __aarch64__
36
37 #ifdef _KERNEL
38 #include <sys/types.h>
39 #include <sys/pool.h>
40 #include <sys/queue.h>
41 #include <uvm/uvm_pglist.h>
42
43 #include <aarch64/pte.h>
44
45 #define PMAP_GROWKERNEL
46 #define PMAP_STEAL_MEMORY
47
48 #define __HAVE_VM_PAGE_MD
49
50 struct pmap {
51 kmutex_t pm_lock;
52 struct pool *pm_pvpool;
53 pd_entry_t *pm_l0table; /* L0 table: 512G*512 */
54 paddr_t pm_l0table_pa;
55
56 SLIST_HEAD(, vm_page) pm_vmlist; /* for L[0123] tables */
57
58 struct pmap_statistics pm_stats;
59 unsigned int pm_refcnt;
60 int pm_asid;
61 bool pm_activated;
62 };
63
64 struct pv_entry;
65 struct vm_page_md {
66 kmutex_t mdpg_pvlock;
67 SLIST_ENTRY(vm_page) mdpg_vmlist; /* L[0-3] table vm_page list */
68 TAILQ_HEAD(, pv_entry) mdpg_pvhead;
69
70 /* VM_PROT_READ means referenced, VM_PROT_WRITE means modified */
71 uint32_t mdpg_flags;
72 };
73
74 /* each mdpg_pvlock will be initialized in pmap_init() */
75 #define VM_MDPAGE_INIT(pg) \
76 do { \
77 TAILQ_INIT(&(pg)->mdpage.mdpg_pvhead); \
78 (pg)->mdpage.mdpg_flags = 0; \
79 } while (/*CONSTCOND*/ 0)
80
81
82 /* saved permission bit for referenced/modified emulation */
83 #define LX_BLKPAG_OS_READ LX_BLKPAG_OS_0
84 #define LX_BLKPAG_OS_WRITE LX_BLKPAG_OS_1
85 #define LX_BLKPAG_OS_WIRED LX_BLKPAG_OS_2
86 #define LX_BLKPAG_OS_BOOT LX_BLKPAG_OS_3
87 #define LX_BLKPAG_OS_RWMASK (LX_BLKPAG_OS_WRITE|LX_BLKPAG_OS_READ)
88
89 /* memory attributes are configured MAIR_EL1 in locore */
90 #define LX_BLKPAG_ATTR_NORMAL_WB __SHIFTIN(0, LX_BLKPAG_ATTR_INDX)
91 #define LX_BLKPAG_ATTR_NORMAL_NC __SHIFTIN(1, LX_BLKPAG_ATTR_INDX)
92 #define LX_BLKPAG_ATTR_NORMAL_WT __SHIFTIN(2, LX_BLKPAG_ATTR_INDX)
93 #define LX_BLKPAG_ATTR_DEVICE_MEM __SHIFTIN(3, LX_BLKPAG_ATTR_INDX)
94 #define LX_BLKPAG_ATTR_MASK LX_BLKPAG_ATTR_INDX
95
96 #define l0pde_pa(pde) ((paddr_t)((pde) & LX_TBL_PA))
97 #define l0pde_index(v) (((vaddr_t)(v) & L0_ADDR_BITS) >> L0_SHIFT)
98 #define l0pde_valid(pde) (((pde) & LX_VALID) == LX_VALID)
99 /* l0pte always contains table entries */
100
101 #define l1pde_pa(pde) ((paddr_t)((pde) & LX_TBL_PA))
102 #define l1pde_index(v) (((vaddr_t)(v) & L1_ADDR_BITS) >> L1_SHIFT)
103 #define l1pde_valid(pde) (((pde) & LX_VALID) == LX_VALID)
104 #define l1pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK)
105 #define l1pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL)
106
107 #define l2pde_pa(pde) ((paddr_t)((pde) & LX_TBL_PA))
108 #define l2pde_index(v) (((vaddr_t)(v) & L2_ADDR_BITS) >> L2_SHIFT)
109 #define l2pde_valid(pde) (((pde) & LX_VALID) == LX_VALID)
110 #define l2pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK)
111 #define l2pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL)
112
113 #define l3pte_pa(pde) ((paddr_t)((pde) & LX_TBL_PA))
114 #define l3pte_executable(pde,user) \
115 (((pde) & ((user) ? LX_BLKPAG_UXN : LX_BLKPAG_PXN)) == 0)
116 #define l3pte_readable(pde) ((pde) & LX_BLKPAG_AF)
117 #define l3pte_writable(pde) \
118 (((pde) & (LX_BLKPAG_AF|LX_BLKPAG_AP)) == (LX_BLKPAG_AF|LX_BLKPAG_AP_RW))
119 #define l3pte_index(v) (((vaddr_t)(v) & L3_ADDR_BITS) >> L3_SHIFT)
120 #define l3pte_valid(pde) (((pde) & LX_VALID) == LX_VALID)
121 #define l3pte_is_page(pde) (((pde) & LX_TYPE) == L3_TYPE_PAG)
122 /* l3pte contains always page entries */
123
124 void pmap_bootstrap(vaddr_t, vaddr_t);
125 bool pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, bool user);
126
127 /* for ddb */
128 void pmap_db_pteinfo(vaddr_t, void (*)(const char *, ...));
129 pt_entry_t *kvtopte(vaddr_t);
130 pt_entry_t pmap_kvattr(vaddr_t, vm_prot_t);
131
132 /* Hooks for the pool allocator */
133 paddr_t vtophys(vaddr_t);
134 #define VTOPHYS_FAILED ((paddr_t)-1L) /* POOL_PADDR_INVALID */
135 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va))
136
137
138 /* devmap */
139 struct pmap_devmap {
140 vaddr_t pd_va; /* virtual address */
141 paddr_t pd_pa; /* physical address */
142 psize_t pd_size; /* size of region */
143 vm_prot_t pd_prot; /* protection code */
144 u_int pd_flags; /* flags for pmap_kenter_pa() */
145 };
146
147 void pmap_devmap_register(const struct pmap_devmap *);
148 void pmap_devmap_bootstrap(const struct pmap_devmap *);
149 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
150 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
151 vaddr_t pmap_devmap_phystov(paddr_t);
152 paddr_t pmap_devmap_vtophys(paddr_t);
153
154 pd_entry_t *pmap_alloc_pdp(struct pmap *, paddr_t *);
155
156 #define L1_TRUNC_BLOCK(x) ((x) & L1_FRAME)
157 #define L1_ROUND_BLOCK(x) L1_TRUNC_BLOCK((x) + L1_SIZE - 1)
158 #define L2_TRUNC_BLOCK(x) ((x) & L2_FRAME)
159 #define L2_ROUND_BLOCK(x) L2_TRUNC_BLOCK((x) + L2_SIZE - 1)
160
161 /* devmap use L2 blocks. (2Mbyte) */
162 #define DEVMAP_TRUNC_ADDR(x) L2_TRUNC_BLOCK((x))
163 #define DEVMAP_ROUND_SIZE(x) L2_ROUND_BLOCK((x))
164
165 #define DEVMAP_ENTRY(va, pa, sz) \
166 { \
167 .pd_va = DEVMAP_TRUNC_ADDR(va), \
168 .pd_pa = DEVMAP_TRUNC_ADDR(pa), \
169 .pd_size = DEVMAP_ROUND_SIZE(sz), \
170 .pd_prot = VM_PROT_READ|VM_PROT_WRITE, \
171 .pd_flags = PMAP_NOCACHE \
172 }
173 #define DEVMAP_ENTRY_END { 0 }
174
175 /* mmap cookie and flags */
176 #define AARCH64_MMAP_FLAG_SHIFT (64 - PGSHIFT)
177 #define AARCH64_MMAP_FLAG_MASK 0xf
178 #define AARCH64_MMAP_WRITEBACK 0UL
179 #define AARCH64_MMAP_NOCACHE 1UL
180 #define AARCH64_MMAP_WRITECOMBINE 2UL
181 #define AARCH64_MMAP_DEVICE 3UL
182
183 #define ARM_MMAP_MASK __BITS(63, AARCH64_MMAP_FLAG_SHIFT)
184 #define ARM_MMAP_WRITECOMBINE __SHIFTIN(AARCH64_MMAP_WRITECOMBINE, ARM_MMAP_MASK)
185 #define ARM_MMAP_WRITEBACK __SHIFTIN(AARCH64_MMAP_WRITEBACK, ARM_MMAP_MASK)
186 #define ARM_MMAP_NOCACHE __SHIFTIN(AARCH64_MMAP_NOCACHE, ARM_MMAP_MASK)
187 #define ARM_MMAP_DEVICE __SHIFTIN(AARCH64_MMAP_DEVICE, ARM_MMAP_MASK)
188
189 #define PMAP_PTE 0x10000000 /* kenter_pa */
190 #define PMAP_DEV 0x20000000 /* kenter_pa */
191
192 static inline u_int
193 aarch64_mmap_flags(paddr_t mdpgno)
194 {
195 u_int nflag, pflag;
196
197 /*
198 * aarch64 arch has 4 memory attribute:
199 *
200 * WriteBack - write back cache
201 * WriteThru - wite through cache
202 * NoCache - no cache
203 * Device(nGnRnE) - no Gathering, no Reordering, no Early write ack
204 *
205 * but pmap has PMAP_{NOCACHE,WRITE_COMBINE,WRITE_BACK} flags.
206 */
207
208 nflag = (mdpgno >> AARCH64_MMAP_FLAG_SHIFT) & AARCH64_MMAP_FLAG_MASK;
209 switch (nflag) {
210 case AARCH64_MMAP_DEVICE:
211 pflag = PMAP_DEV;
212 break;
213 case AARCH64_MMAP_WRITECOMBINE:
214 pflag = PMAP_WRITE_COMBINE;
215 break;
216 case AARCH64_MMAP_WRITEBACK:
217 pflag = PMAP_WRITE_BACK;
218 break;
219 case AARCH64_MMAP_NOCACHE:
220 default:
221 pflag = PMAP_NOCACHE;
222 break;
223 }
224 return pflag;
225 }
226
227
228 #define pmap_phys_address(pa) aarch64_ptob((pa))
229 #define pmap_mmap_flags(ppn) aarch64_mmap_flags((ppn))
230
231 #define pmap_update(pmap) ((void)0)
232 #define pmap_copy(dp,sp,d,l,s) ((void)0)
233 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count)
234 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count)
235
236 bool pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *);
237
238 #define PMAP_MAPSIZE1 L2_SIZE
239
240 #endif /* _KERNEL */
241
242 #elif defined(__arm__)
243
244 #include <arm/pmap.h>
245
246 #endif /* __arm__/__aarch64__ */
247
248 #endif /* !_AARCH64_PMAP_ */
249