pmap.h revision 1.13
1 /* $NetBSD: pmap.h,v 1.13 2018/10/12 00:57:17 ryo Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AARCH64_PMAP_H_ 33 #define _AARCH64_PMAP_H_ 34 35 #ifdef __aarch64__ 36 37 #ifdef _KERNEL 38 #include <sys/types.h> 39 #include <sys/pool.h> 40 #include <sys/queue.h> 41 #include <uvm/uvm_pglist.h> 42 43 #include <aarch64/pte.h> 44 45 #define PMAP_GROWKERNEL 46 #define PMAP_STEAL_MEMORY 47 48 #define __HAVE_VM_PAGE_MD 49 50 struct pmap { 51 kmutex_t pm_lock; 52 struct pool *pm_pvpool; 53 pd_entry_t *pm_l0table; /* L0 table: 512G*512 */ 54 paddr_t pm_l0table_pa; 55 56 SLIST_HEAD(, vm_page) pm_vmlist; /* for L[0123] tables */ 57 58 struct pmap_statistics pm_stats; 59 unsigned int pm_refcnt; 60 int pm_asid; 61 bool pm_activated; 62 }; 63 64 struct pv_entry; 65 struct vm_page_md { 66 kmutex_t mdpg_pvlock; 67 SLIST_ENTRY(vm_page) mdpg_vmlist; /* L[0-3] table vm_page list */ 68 TAILQ_HEAD(, pv_entry) mdpg_pvhead; 69 70 /* VM_PROT_READ means referenced, VM_PROT_WRITE means modified */ 71 uint32_t mdpg_flags; 72 }; 73 74 /* each mdpg_pvlock will be initialized in pmap_init() */ 75 #define VM_MDPAGE_INIT(pg) \ 76 do { \ 77 TAILQ_INIT(&(pg)->mdpage.mdpg_pvhead); \ 78 (pg)->mdpage.mdpg_flags = 0; \ 79 } while (/*CONSTCOND*/ 0) 80 81 82 /* saved permission bit for referenced/modified emulation */ 83 #define LX_BLKPAG_OS_READ LX_BLKPAG_OS_0 84 #define LX_BLKPAG_OS_WRITE LX_BLKPAG_OS_1 85 #define LX_BLKPAG_OS_WIRED LX_BLKPAG_OS_2 86 #define LX_BLKPAG_OS_BOOT LX_BLKPAG_OS_3 87 #define LX_BLKPAG_OS_RWMASK (LX_BLKPAG_OS_WRITE|LX_BLKPAG_OS_READ) 88 89 /* memory attributes are configured MAIR_EL1 in locore */ 90 #define LX_BLKPAG_ATTR_NORMAL_WB __SHIFTIN(0, LX_BLKPAG_ATTR_INDX) 91 #define LX_BLKPAG_ATTR_NORMAL_NC __SHIFTIN(1, LX_BLKPAG_ATTR_INDX) 92 #define LX_BLKPAG_ATTR_NORMAL_WT __SHIFTIN(2, LX_BLKPAG_ATTR_INDX) 93 #define LX_BLKPAG_ATTR_DEVICE_MEM __SHIFTIN(3, LX_BLKPAG_ATTR_INDX) 94 #define LX_BLKPAG_ATTR_MASK LX_BLKPAG_ATTR_INDX 95 96 #define lxpde_pa(pde) ((paddr_t)((pde) & LX_TBL_PA)) 97 #define l0pde_pa(pde) lxpde_pa(pde) 98 #define l0pde_index(v) (((vaddr_t)(v) & L0_ADDR_BITS) >> L0_SHIFT) 99 #define l0pde_valid(pde) (((pde) & LX_VALID) == LX_VALID) 100 /* l0pte always contains table entries */ 101 102 #define l1pde_pa(pde) lxpde_pa(pde) 103 #define l1pde_index(v) (((vaddr_t)(v) & L1_ADDR_BITS) >> L1_SHIFT) 104 #define l1pde_valid(pde) (((pde) & LX_VALID) == LX_VALID) 105 #define l1pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK) 106 #define l1pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL) 107 108 #define l2pde_pa(pde) lxpde_pa(pde) 109 #define l2pde_index(v) (((vaddr_t)(v) & L2_ADDR_BITS) >> L2_SHIFT) 110 #define l2pde_valid(pde) (((pde) & LX_VALID) == LX_VALID) 111 #define l2pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK) 112 #define l2pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL) 113 114 #define l3pte_pa(pde) lxpde_pa(pde) 115 #define l3pte_executable(pde,user) \ 116 (((pde) & ((user) ? LX_BLKPAG_UXN : LX_BLKPAG_PXN)) == 0) 117 #define l3pte_readable(pde) ((pde) & LX_BLKPAG_AF) 118 #define l3pte_writable(pde) \ 119 (((pde) & (LX_BLKPAG_AF|LX_BLKPAG_AP)) == (LX_BLKPAG_AF|LX_BLKPAG_AP_RW)) 120 #define l3pte_index(v) (((vaddr_t)(v) & L3_ADDR_BITS) >> L3_SHIFT) 121 #define l3pte_valid(pde) (((pde) & LX_VALID) == LX_VALID) 122 #define l3pte_is_page(pde) (((pde) & LX_TYPE) == L3_TYPE_PAG) 123 /* l3pte contains always page entries */ 124 125 void pmap_bootstrap(vaddr_t, vaddr_t); 126 bool pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, bool user); 127 128 /* for ddb */ 129 void pmap_db_pteinfo(vaddr_t, void (*)(const char *, ...) __printflike(1, 2)); 130 pt_entry_t *kvtopte(vaddr_t); 131 pt_entry_t pmap_kvattr(vaddr_t, vm_prot_t); 132 133 /* locore.S */ 134 pd_entry_t *bootpage_alloc(void); 135 136 /* pmap_locore.c */ 137 int pmapboot_enter(vaddr_t, paddr_t, psize_t, psize_t, 138 pt_entry_t, uint64_t, pd_entry_t *(*)(void), 139 void (*pr)(const char *, ...) __printflike(1, 2)); 140 #define PMAPBOOT_ENTER_NOBLOCK 0x00000001 141 #define PMAPBOOT_ENTER_NOOVERWRITE 0x00000002 142 int pmapboot_protect(vaddr_t, vaddr_t, vm_prot_t); 143 void pmap_db_pte_print(pt_entry_t, int, 144 void (*pr)(const char *, ...) __printflike(1, 2)); 145 146 /* Hooks for the pool allocator */ 147 paddr_t vtophys(vaddr_t); 148 #define VTOPHYS_FAILED ((paddr_t)-1L) /* POOL_PADDR_INVALID */ 149 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 150 151 152 /* devmap */ 153 struct pmap_devmap { 154 vaddr_t pd_va; /* virtual address */ 155 paddr_t pd_pa; /* physical address */ 156 psize_t pd_size; /* size of region */ 157 vm_prot_t pd_prot; /* protection code */ 158 u_int pd_flags; /* flags for pmap_kenter_pa() */ 159 }; 160 161 void pmap_devmap_register(const struct pmap_devmap *); 162 void pmap_devmap_bootstrap(const struct pmap_devmap *); 163 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 164 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 165 vaddr_t pmap_devmap_phystov(paddr_t); 166 paddr_t pmap_devmap_vtophys(paddr_t); 167 168 pd_entry_t *pmap_alloc_pdp(struct pmap *, paddr_t *); 169 170 #define L1_TRUNC_BLOCK(x) ((x) & L1_FRAME) 171 #define L1_ROUND_BLOCK(x) L1_TRUNC_BLOCK((x) + L1_SIZE - 1) 172 #define L2_TRUNC_BLOCK(x) ((x) & L2_FRAME) 173 #define L2_ROUND_BLOCK(x) L2_TRUNC_BLOCK((x) + L2_SIZE - 1) 174 175 /* devmap use L2 blocks. (2Mbyte) */ 176 #define DEVMAP_TRUNC_ADDR(x) L2_TRUNC_BLOCK((x)) 177 #define DEVMAP_ROUND_SIZE(x) L2_ROUND_BLOCK((x)) 178 179 #define DEVMAP_ENTRY(va, pa, sz) \ 180 { \ 181 .pd_va = DEVMAP_TRUNC_ADDR(va), \ 182 .pd_pa = DEVMAP_TRUNC_ADDR(pa), \ 183 .pd_size = DEVMAP_ROUND_SIZE(sz), \ 184 .pd_prot = VM_PROT_READ|VM_PROT_WRITE, \ 185 .pd_flags = PMAP_NOCACHE \ 186 } 187 #define DEVMAP_ENTRY_END { 0 } 188 189 /* mmap cookie and flags */ 190 #define AARCH64_MMAP_FLAG_SHIFT (64 - PGSHIFT) 191 #define AARCH64_MMAP_FLAG_MASK 0xf 192 #define AARCH64_MMAP_WRITEBACK 0UL 193 #define AARCH64_MMAP_NOCACHE 1UL 194 #define AARCH64_MMAP_WRITECOMBINE 2UL 195 #define AARCH64_MMAP_DEVICE 3UL 196 197 #define ARM_MMAP_MASK __BITS(63, AARCH64_MMAP_FLAG_SHIFT) 198 #define ARM_MMAP_WRITECOMBINE __SHIFTIN(AARCH64_MMAP_WRITECOMBINE, ARM_MMAP_MASK) 199 #define ARM_MMAP_WRITEBACK __SHIFTIN(AARCH64_MMAP_WRITEBACK, ARM_MMAP_MASK) 200 #define ARM_MMAP_NOCACHE __SHIFTIN(AARCH64_MMAP_NOCACHE, ARM_MMAP_MASK) 201 #define ARM_MMAP_DEVICE __SHIFTIN(AARCH64_MMAP_DEVICE, ARM_MMAP_MASK) 202 203 #define PMAP_PTE 0x10000000 /* kenter_pa */ 204 #define PMAP_DEV 0x20000000 /* kenter_pa */ 205 206 static inline u_int 207 aarch64_mmap_flags(paddr_t mdpgno) 208 { 209 u_int nflag, pflag; 210 211 /* 212 * aarch64 arch has 4 memory attribute: 213 * 214 * WriteBack - write back cache 215 * WriteThru - wite through cache 216 * NoCache - no cache 217 * Device(nGnRnE) - no Gathering, no Reordering, no Early write ack 218 * 219 * but pmap has PMAP_{NOCACHE,WRITE_COMBINE,WRITE_BACK} flags. 220 */ 221 222 nflag = (mdpgno >> AARCH64_MMAP_FLAG_SHIFT) & AARCH64_MMAP_FLAG_MASK; 223 switch (nflag) { 224 case AARCH64_MMAP_DEVICE: 225 pflag = PMAP_DEV; 226 break; 227 case AARCH64_MMAP_WRITECOMBINE: 228 pflag = PMAP_WRITE_COMBINE; 229 break; 230 case AARCH64_MMAP_WRITEBACK: 231 pflag = PMAP_WRITE_BACK; 232 break; 233 case AARCH64_MMAP_NOCACHE: 234 default: 235 pflag = PMAP_NOCACHE; 236 break; 237 } 238 return pflag; 239 } 240 241 242 #define pmap_phys_address(pa) aarch64_ptob((pa)) 243 #define pmap_mmap_flags(ppn) aarch64_mmap_flags((ppn)) 244 245 #define pmap_update(pmap) ((void)0) 246 #define pmap_copy(dp,sp,d,l,s) ((void)0) 247 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 248 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 249 250 bool pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *); 251 252 #define PMAP_MAPSIZE1 L2_SIZE 253 254 #endif /* _KERNEL */ 255 256 #elif defined(__arm__) 257 258 #include <arm/pmap.h> 259 260 #endif /* __arm__/__aarch64__ */ 261 262 #endif /* !_AARCH64_PMAP_ */ 263
Indexes created Tue Sep 30 17:09:57 GMT 2025