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pmap.h revision 1.25 
      1 /* $NetBSD: pmap.h,v 1.25 2019/08/12 10:28:04 skrll Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2014 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Matt Thomas of 3am Software Foundry.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _AARCH64_PMAP_H_
     33 #define _AARCH64_PMAP_H_
     34 
     35 #ifdef __aarch64__
     36 
     37 #ifdef _KERNEL
     38 #ifdef _KERNEL_OPT
     39 #include "opt_kasan.h"
     40 #endif
     41 
     42 #include <sys/types.h>
     43 #include <sys/pool.h>
     44 #include <sys/queue.h>
     45 #include <uvm/uvm_pglist.h>
     46 
     47 #include <aarch64/pte.h>
     48 
     49 #define PMAP_GROWKERNEL
     50 #define PMAP_STEAL_MEMORY
     51 
     52 #define __HAVE_VM_PAGE_MD
     53 
     54 #ifndef KASAN
     55 #define PMAP_MAP_POOLPAGE(pa)		AARCH64_PA_TO_KVA(pa)
     56 #define PMAP_UNMAP_POOLPAGE(va)		AARCH64_KVA_TO_PA(va)
     57 
     58 #define PMAP_DIRECT
     59 static __inline int
     60 pmap_direct_process(paddr_t pa, voff_t pgoff, size_t len,
     61     int (*process)(void *, size_t, void *), void *arg)
     62 {
     63 	vaddr_t va = AARCH64_PA_TO_KVA(pa);
     64 
     65 	return process((void *)(va + pgoff), len, arg);
     66 }
     67 #endif
     68 
     69 struct pmap {
     70 	kmutex_t pm_lock;
     71 	struct pool *pm_pvpool;
     72 	pd_entry_t *pm_l0table;			/* L0 table: 512G*512 */
     73 	paddr_t pm_l0table_pa;
     74 
     75 	TAILQ_HEAD(, vm_page) pm_vmlist;	/* for L[0123] tables */
     76 
     77 	struct pmap_statistics pm_stats;
     78 	unsigned int pm_refcnt;
     79 	unsigned int pm_idlepdp;
     80 	int pm_asid;
     81 	bool pm_activated;
     82 };
     83 
     84 struct pv_entry;
     85 struct vm_page_md {
     86 	kmutex_t mdpg_pvlock;
     87 	TAILQ_ENTRY(vm_page) mdpg_vmlist;	/* L[0123] table vm_page list */
     88 	TAILQ_HEAD(, pv_entry) mdpg_pvhead;
     89 
     90 	pd_entry_t *mdpg_ptep_parent;	/* for page descriptor page only */
     91 
     92 	/* VM_PROT_READ means referenced, VM_PROT_WRITE means modified */
     93 	uint32_t mdpg_flags;
     94 };
     95 
     96 /* each mdpg_pvlock will be initialized in pmap_init() */
     97 #define VM_MDPAGE_INIT(pg)				\
     98 	do {						\
     99 		TAILQ_INIT(&(pg)->mdpage.mdpg_pvhead);	\
    100 		(pg)->mdpage.mdpg_flags = 0;		\
    101 	} while (/*CONSTCOND*/ 0)
    102 
    103 
    104 /* saved permission bit for referenced/modified emulation */
    105 #define LX_BLKPAG_OS_READ		LX_BLKPAG_OS_0
    106 #define LX_BLKPAG_OS_WRITE		LX_BLKPAG_OS_1
    107 #define LX_BLKPAG_OS_WIRED		LX_BLKPAG_OS_2
    108 #define LX_BLKPAG_OS_BOOT		LX_BLKPAG_OS_3
    109 #define LX_BLKPAG_OS_RWMASK		(LX_BLKPAG_OS_WRITE|LX_BLKPAG_OS_READ)
    110 
    111 /* memory attributes are configured MAIR_EL1 in locore */
    112 #define LX_BLKPAG_ATTR_NORMAL_WB	__SHIFTIN(0, LX_BLKPAG_ATTR_INDX)
    113 #define LX_BLKPAG_ATTR_NORMAL_NC	__SHIFTIN(1, LX_BLKPAG_ATTR_INDX)
    114 #define LX_BLKPAG_ATTR_NORMAL_WT	__SHIFTIN(2, LX_BLKPAG_ATTR_INDX)
    115 #define LX_BLKPAG_ATTR_DEVICE_MEM	__SHIFTIN(3, LX_BLKPAG_ATTR_INDX)
    116 #define LX_BLKPAG_ATTR_MASK		LX_BLKPAG_ATTR_INDX
    117 
    118 #define lxpde_pa(pde)		((paddr_t)((pde) & LX_TBL_PA))
    119 #define lxpde_valid(pde)	(((pde) & LX_VALID) == LX_VALID)
    120 #define l0pde_pa(pde)		lxpde_pa(pde)
    121 #define l0pde_index(v)		(((vaddr_t)(v) & L0_ADDR_BITS) >> L0_SHIFT)
    122 #define l0pde_valid(pde)	lxpde_valid(pde)
    123 /* l0pte always contains table entries */
    124 
    125 #define l1pde_pa(pde)		lxpde_pa(pde)
    126 #define l1pde_index(v)		(((vaddr_t)(v) & L1_ADDR_BITS) >> L1_SHIFT)
    127 #define l1pde_valid(pde)	lxpde_valid(pde)
    128 #define l1pde_is_block(pde)	(((pde) & LX_TYPE) == LX_TYPE_BLK)
    129 #define l1pde_is_table(pde)	(((pde) & LX_TYPE) == LX_TYPE_TBL)
    130 
    131 #define l2pde_pa(pde)		lxpde_pa(pde)
    132 #define l2pde_index(v)		(((vaddr_t)(v) & L2_ADDR_BITS) >> L2_SHIFT)
    133 #define l2pde_valid(pde)	lxpde_valid(pde)
    134 #define l2pde_is_block(pde)	(((pde) & LX_TYPE) == LX_TYPE_BLK)
    135 #define l2pde_is_table(pde)	(((pde) & LX_TYPE) == LX_TYPE_TBL)
    136 
    137 #define l3pte_pa(pde)		lxpde_pa(pde)
    138 #define l3pte_executable(pde,user)	\
    139     (((pde) & ((user) ? LX_BLKPAG_UXN : LX_BLKPAG_PXN)) == 0)
    140 #define l3pte_readable(pde)	((pde) & LX_BLKPAG_AF)
    141 #define l3pte_writable(pde)	\
    142     (((pde) & (LX_BLKPAG_AF|LX_BLKPAG_AP)) == (LX_BLKPAG_AF|LX_BLKPAG_AP_RW))
    143 #define l3pte_index(v)		(((vaddr_t)(v) & L3_ADDR_BITS) >> L3_SHIFT)
    144 #define l3pte_valid(pde)	lxpde_valid(pde)
    145 #define l3pte_is_page(pde)	(((pde) & LX_TYPE) == L3_TYPE_PAG)
    146 /* l3pte contains always page entries */
    147 
    148 void pmap_bootstrap(vaddr_t, vaddr_t);
    149 bool pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, bool user);
    150 
    151 /* for ddb */
    152 void pmap_db_pteinfo(vaddr_t, void (*)(const char *, ...) __printflike(1, 2));
    153 void pmap_db_ttbrdump(bool, vaddr_t, void (*)(const char *, ...)
    154     __printflike(1, 2));
    155 pt_entry_t *kvtopte(vaddr_t);
    156 pt_entry_t pmap_kvattr(vaddr_t, vm_prot_t);
    157 
    158 /* locore.S */
    159 pd_entry_t *bootpage_alloc(void);
    160 
    161 /* pmap_locore.c */
    162 int pmapboot_enter(vaddr_t, paddr_t, psize_t, psize_t,
    163     pt_entry_t, uint64_t, pd_entry_t *(*)(void),
    164     void (*pr)(const char *, ...) __printflike(1, 2));
    165 #define PMAPBOOT_ENTER_NOBLOCK		0x00000001
    166 #define PMAPBOOT_ENTER_NOOVERWRITE	0x00000002
    167 int pmapboot_protect(vaddr_t, vaddr_t, vm_prot_t);
    168 void pmap_db_pte_print(pt_entry_t, int,
    169     void (*pr)(const char *, ...) __printflike(1, 2));
    170 
    171 /* Hooks for the pool allocator */
    172 paddr_t vtophys(vaddr_t);
    173 #define VTOPHYS_FAILED		((paddr_t)-1L)	/* POOL_PADDR_INVALID */
    174 #define POOL_VTOPHYS(va)	vtophys((vaddr_t) (va))
    175 
    176 
    177 /* devmap */
    178 struct pmap_devmap {
    179 	vaddr_t pd_va;		/* virtual address */
    180 	paddr_t pd_pa;		/* physical address */
    181 	psize_t pd_size;	/* size of region */
    182 	vm_prot_t pd_prot;	/* protection code */
    183 	u_int pd_flags;		/* flags for pmap_kenter_pa() */
    184 };
    185 
    186 void pmap_devmap_register(const struct pmap_devmap *);
    187 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *);
    188 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
    189 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
    190 vaddr_t pmap_devmap_phystov(paddr_t);
    191 paddr_t pmap_devmap_vtophys(paddr_t);
    192 
    193 paddr_t pmap_alloc_pdp(struct pmap *, struct vm_page **, int, bool);
    194 
    195 #define L1_TRUNC_BLOCK(x)	((x) & L1_FRAME)
    196 #define L1_ROUND_BLOCK(x)	L1_TRUNC_BLOCK((x) + L1_SIZE - 1)
    197 #define L2_TRUNC_BLOCK(x)	((x) & L2_FRAME)
    198 #define L2_ROUND_BLOCK(x)	L2_TRUNC_BLOCK((x) + L2_SIZE - 1)
    199 
    200 /* devmap use L2 blocks. (2Mbyte) */
    201 #define DEVMAP_TRUNC_ADDR(x)	L2_TRUNC_BLOCK((x))
    202 #define DEVMAP_ROUND_SIZE(x)	L2_ROUND_BLOCK((x))
    203 
    204 #define	DEVMAP_ENTRY(va, pa, sz)			\
    205 	{						\
    206 		.pd_va = DEVMAP_TRUNC_ADDR(va),		\
    207 		.pd_pa = DEVMAP_TRUNC_ADDR(pa),		\
    208 		.pd_size = DEVMAP_ROUND_SIZE(sz),	\
    209 		.pd_prot = VM_PROT_READ|VM_PROT_WRITE,	\
    210 		.pd_flags = PMAP_DEV			\
    211 	}
    212 #define	DEVMAP_ENTRY_END	{ 0 }
    213 
    214 /* mmap cookie and flags */
    215 #define AARCH64_MMAP_FLAG_SHIFT		(64 - PGSHIFT)
    216 #define AARCH64_MMAP_FLAG_MASK		0xf
    217 #define AARCH64_MMAP_WRITEBACK		0UL
    218 #define AARCH64_MMAP_NOCACHE		1UL
    219 #define AARCH64_MMAP_WRITECOMBINE	2UL
    220 #define AARCH64_MMAP_DEVICE		3UL
    221 
    222 #define ARM_MMAP_MASK			__BITS(63, AARCH64_MMAP_FLAG_SHIFT)
    223 #define ARM_MMAP_WRITECOMBINE		__SHIFTIN(AARCH64_MMAP_WRITECOMBINE, ARM_MMAP_MASK)
    224 #define ARM_MMAP_WRITEBACK		__SHIFTIN(AARCH64_MMAP_WRITEBACK, ARM_MMAP_MASK)
    225 #define ARM_MMAP_NOCACHE		__SHIFTIN(AARCH64_MMAP_NOCACHE, ARM_MMAP_MASK)
    226 #define ARM_MMAP_DEVICE			__SHIFTIN(AARCH64_MMAP_DEVICE, ARM_MMAP_MASK)
    227 
    228 #define	PMAP_PTE			0x10000000 /* kenter_pa */
    229 #define	PMAP_DEV			0x20000000 /* kenter_pa */
    230 
    231 static inline u_int
    232 aarch64_mmap_flags(paddr_t mdpgno)
    233 {
    234 	u_int nflag, pflag;
    235 
    236 	/*
    237 	 * aarch64 arch has 4 memory attribute:
    238 	 *
    239 	 *  WriteBack      - write back cache
    240 	 *  WriteThru      - wite through cache
    241 	 *  NoCache        - no cache
    242 	 *  Device(nGnRnE) - no Gathering, no Reordering, no Early write ack
    243 	 *
    244 	 * but pmap has PMAP_{NOCACHE,WRITE_COMBINE,WRITE_BACK} flags.
    245 	 */
    246 
    247 	nflag = (mdpgno >> AARCH64_MMAP_FLAG_SHIFT) & AARCH64_MMAP_FLAG_MASK;
    248 	switch (nflag) {
    249 	case AARCH64_MMAP_DEVICE:
    250 		pflag = PMAP_DEV;
    251 		break;
    252 	case AARCH64_MMAP_WRITECOMBINE:
    253 		pflag = PMAP_WRITE_COMBINE;
    254 		break;
    255 	case AARCH64_MMAP_WRITEBACK:
    256 		pflag = PMAP_WRITE_BACK;
    257 		break;
    258 	case AARCH64_MMAP_NOCACHE:
    259 	default:
    260 		pflag = PMAP_NOCACHE;
    261 		break;
    262 	}
    263 	return pflag;
    264 }
    265 
    266 
    267 #define pmap_phys_address(pa)		aarch64_ptob((pa))
    268 #define pmap_mmap_flags(ppn)		aarch64_mmap_flags((ppn))
    269 
    270 #define pmap_update(pmap)		((void)0)
    271 #define pmap_copy(dp,sp,d,l,s)		((void)0)
    272 #define pmap_wired_count(pmap)		((pmap)->pm_stats.wired_count)
    273 #define pmap_resident_count(pmap)	((pmap)->pm_stats.resident_count)
    274 
    275 bool	pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *);
    276 void	pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t);
    277 
    278 #define	PMAP_MAPSIZE1	L2_SIZE
    279 
    280 #endif /* _KERNEL */
    281 
    282 #elif defined(__arm__)
    283 
    284 #include <arm/pmap.h>
    285 
    286 #endif /* __arm__/__aarch64__ */
    287 
    288 #endif /* !_AARCH64_PMAP_ */
    289