pmap.h revision 1.3
1 /* $NetBSD: pmap.h,v 1.3 2018/04/09 22:26:16 jmcneill Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AARCH64_PMAP_H_ 33 #define _AARCH64_PMAP_H_ 34 35 #ifdef __aarch64__ 36 37 #include <sys/types.h> 38 #include <sys/pool.h> 39 #include <sys/queue.h> 40 #include <uvm/uvm_pglist.h> 41 42 #include <aarch64/pte.h> 43 44 #define PMAP_GROWKERNEL 45 #define PMAP_STEAL_MEMORY 46 47 #define __HAVE_VM_PAGE_MD 48 49 struct pmap { 50 kmutex_t pm_lock; 51 struct pool *pm_pvpool; 52 pd_entry_t *pm_l0table; /* L0 table: 512G*512 */ 53 paddr_t pm_l0table_pa; 54 55 SLIST_HEAD(, vm_page) pm_vmlist; /* for L[0123] tables */ 56 57 struct pmap_statistics pm_stats; 58 unsigned int pm_refcnt; 59 int pm_asid; 60 bool pm_activated; 61 }; 62 63 struct pv_entry; 64 struct vm_page_md { 65 kmutex_t mdpg_pvlock; 66 SLIST_ENTRY(vm_page) mdpg_vmlist; /* L[0-3] table vm_page list */ 67 TAILQ_HEAD(, pv_entry) mdpg_pvhead; 68 69 /* VM_PROT_READ means referenced, VM_PROT_WRITE means modified */ 70 uint32_t mdpg_flags; 71 72 u_int mdpg_kenter; /* num of pmap_kenter_pa()'ed */ 73 u_int mdpg_wiredcount; /* num of pmap_enter with PMAP_WIRED */ 74 }; 75 76 /* each mdpg_pvlock will be initialized in pmap_init() */ 77 #define VM_MDPAGE_INIT(pg) \ 78 do { \ 79 TAILQ_INIT(&(pg)->mdpage.mdpg_pvhead); \ 80 (pg)->mdpage.mdpg_flags = 0; \ 81 (pg)->mdpage.mdpg_kenter = 0; \ 82 (pg)->mdpage.mdpg_wiredcount = 0; \ 83 } while (/*CONSTCOND*/ 0) 84 85 #define l0pde_pa(pde) ((paddr_t)((pde) & LX_TBL_PA)) 86 #define l0pde_index(v) (((vaddr_t)(v) & L0_ADDR_BITS) >> L0_SHIFT) 87 #define l0pde_valid(pde) (((pde) & LX_VALID) == LX_VALID) 88 /* l0pte always contains table entries */ 89 90 #define l1pde_pa(pde) ((paddr_t)((pde) & LX_TBL_PA)) 91 #define l1pde_index(v) (((vaddr_t)(v) & L1_ADDR_BITS) >> L1_SHIFT) 92 #define l1pde_valid(pde) (((pde) & LX_VALID) == LX_VALID) 93 #define l1pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK) 94 #define l1pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL) 95 96 #define l2pde_pa(pde) ((paddr_t)((pde) & LX_TBL_PA)) 97 #define l2pde_index(v) (((vaddr_t)(v) & L2_ADDR_BITS) >> L2_SHIFT) 98 #define l2pde_valid(pde) (((pde) & LX_VALID) == LX_VALID) 99 #define l2pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK) 100 #define l2pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL) 101 102 #define l3pte_pa(pde) ((paddr_t)((pde) & LX_TBL_PA)) 103 #define l3pte_executable(pde) \ 104 (((pde) & (LX_BLKPAG_UXN|LX_BLKPAG_PXN)) != (LX_BLKPAG_UXN|LX_BLKPAG_PXN)) 105 #define l3pte_index(v) (((vaddr_t)(v) & L3_ADDR_BITS) >> L3_SHIFT) 106 #define l3pte_valid(pde) (((pde) & LX_VALID) == LX_VALID) 107 #define l3pte_is_page(pde) (((pde) & LX_TYPE) == L3_TYPE_PAG) 108 /* l3pte contains always page entries */ 109 110 void pmap_bootstrap(vaddr_t, vaddr_t); 111 bool pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, bool user); 112 void pmap_db_pteinfo(vaddr_t, void (*)(const char *, ...)); 113 114 /* Hooks for the pool allocator */ 115 paddr_t vtophys(vaddr_t); 116 #define VTOPHYS_FAILED ((paddr_t)-1L) /* POOL_PADDR_INVALID */ 117 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 118 119 120 /* devmap */ 121 struct pmap_devmap { 122 vaddr_t pd_va; /* virtual address */ 123 paddr_t pd_pa; /* physical address */ 124 psize_t pd_size; /* size of region */ 125 vm_prot_t pd_prot; /* protection code */ 126 u_int pd_flags; /* flags for pmap_kenter_pa() */ 127 }; 128 129 void pmap_devmap_register(const struct pmap_devmap *); 130 void pmap_devmap_bootstrap(const struct pmap_devmap *); 131 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 132 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 133 vaddr_t pmap_devmap_phystov(paddr_t); 134 paddr_t pmap_devmap_vtophys(paddr_t); 135 136 /* devmap use L2 blocks. (2Mbyte) */ 137 #define DEVMAP_TRUNC_ADDR(x) ((x) & ~L2_OFFSET) 138 #define DEVMAP_ROUND_SIZE(x) (((x) + L2_SIZE - 1) & ~(L2_SIZE - 1)) 139 140 #define DEVMAP_ENTRY(va, pa, sz) \ 141 { \ 142 .pd_va = DEVMAP_TRUNC_ADDR(va), \ 143 .pd_pa = DEVMAP_TRUNC_ADDR(pa), \ 144 .pd_size = DEVMAP_ROUND_SIZE(sz), \ 145 .pd_prot = VM_PROT_READ|VM_PROT_WRITE, \ 146 .pd_flags = PMAP_NOCACHE \ 147 } 148 #define DEVMAP_ENTRY_END { 0 } 149 150 /* mmap cookie and flags */ 151 #define AARCH64_MMAP_FLAG_SHIFT (64 - PGSHIFT) 152 #define AARCH64_MMAP_FLAG_MASK 0xf 153 #define AARCH64_MMAP_WRITEBACK 0UL 154 #define AARCH64_MMAP_NOCACHE 1UL 155 #define AARCH64_MMAP_WRITECOMBINE 2UL 156 #define AARCH64_MMAP_DEVICE 3UL 157 158 #define ARM_MMAP_WRITECOMBINE AARCH64_MMAP_WRITECOMBINE 159 #define ARM_MMAP_WRITEBACK AARCH64_MMAP_WRITEBACK 160 #define ARM_MMAP_NOCACHE AARCH64_MMAP_NOCACHE 161 #define ARM_MMAP_DEVICE AARCH64_MMAP_DEVICE 162 163 #define PMAP_PTE 0x10000000 /* kenter_pa */ 164 #define PMAP_DEV 0x20000000 /* kenter_pa */ 165 166 static inline u_int 167 aarch64_mmap_flags(paddr_t mdpgno) 168 { 169 u_int nflag, pflag; 170 171 /* 172 * aarch64 arch has 4 memory attribute: 173 * 174 * WriteBack - write back cache 175 * WriteThru - wite through cache 176 * NoCache - no cache 177 * Device(nGnRnE) - no Gathering, no Reordering, no Early write ack 178 * 179 * but pmap has PMAP_{NOCACHE,WRITE_COMBINE,WRITE_BACK} flags. 180 */ 181 182 nflag = (mdpgno >> AARCH64_MMAP_FLAG_SHIFT) & AARCH64_MMAP_FLAG_MASK; 183 switch (nflag) { 184 case AARCH64_MMAP_DEVICE: 185 pflag = PMAP_DEV; 186 break; 187 case AARCH64_MMAP_WRITECOMBINE: 188 pflag = PMAP_WRITE_COMBINE; 189 break; 190 case AARCH64_MMAP_WRITEBACK: 191 pflag = PMAP_WRITE_BACK; 192 break; 193 case AARCH64_MMAP_NOCACHE: 194 default: 195 pflag = PMAP_NOCACHE; 196 break; 197 } 198 return pflag; 199 } 200 201 202 #define pmap_phys_address(pa) aarch64_ptob((pa)) 203 #define pmap_mmap_flags(ppn) aarch64_mmap_flags((ppn)) 204 205 #define pmap_update(pmap) ((void)0) 206 #define pmap_copy(dp,sp,d,l,s) ((void)0) 207 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 208 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 209 210 bool pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *); 211 212 #define PMAP_MAPSIZE1 L2_SIZE 213 214 #elif defined(__arm__) 215 216 #include <arm/pmap.h> 217 218 #endif /* __arm__/__aarch64__ */ 219 220 #endif /* !_AARCH64_PMAP_ */ 221
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