pmap.h revision 1.36
1 /* $NetBSD: pmap.h,v 1.36 2020/02/29 21:32:22 ryo Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AARCH64_PMAP_H_ 33 #define _AARCH64_PMAP_H_ 34 35 #ifdef __aarch64__ 36 37 #ifdef _KERNEL 38 #ifdef _KERNEL_OPT 39 #include "opt_kasan.h" 40 #endif 41 42 #include <sys/types.h> 43 #include <sys/pool.h> 44 #include <sys/queue.h> 45 #include <uvm/uvm_pglist.h> 46 47 #include <aarch64/armreg.h> 48 #include <aarch64/pte.h> 49 50 #define PMAP_NEED_PROCWR 51 #define PMAP_GROWKERNEL 52 #define PMAP_STEAL_MEMORY 53 54 #define __HAVE_VM_PAGE_MD 55 #define __HAVE_PMAP_PV_TRACK 1 56 57 #ifndef KASAN 58 #define PMAP_MAP_POOLPAGE(pa) AARCH64_PA_TO_KVA(pa) 59 #define PMAP_UNMAP_POOLPAGE(va) AARCH64_KVA_TO_PA(va) 60 61 #define PMAP_DIRECT 62 static __inline int 63 pmap_direct_process(paddr_t pa, voff_t pgoff, size_t len, 64 int (*process)(void *, size_t, void *), void *arg) 65 { 66 vaddr_t va = AARCH64_PA_TO_KVA(pa); 67 68 return process((void *)(va + pgoff), len, arg); 69 } 70 #endif 71 72 struct pmap { 73 kmutex_t pm_lock; 74 struct pool *pm_pvpool; 75 pd_entry_t *pm_l0table; /* L0 table: 512G*512 */ 76 paddr_t pm_l0table_pa; 77 78 LIST_HEAD(, vm_page) pm_vmlist; /* for L[0123] tables */ 79 80 struct pmap_statistics pm_stats; 81 unsigned int pm_refcnt; 82 unsigned int pm_idlepdp; 83 int pm_asid; 84 bool pm_activated; 85 }; 86 87 struct pv_entry; 88 89 struct pmap_page { 90 kmutex_t pp_pvlock; 91 LIST_HEAD(, pv_entry) pp_pvhead; 92 93 /* VM_PROT_READ means referenced, VM_PROT_WRITE means modified */ 94 uint32_t pp_flags; 95 #define PMAP_PAGE_FLAGS_PV_TRACKED 0x80000000 96 }; 97 98 struct vm_page_md { 99 LIST_ENTRY(vm_page) mdpg_vmlist; /* L[0123] table vm_page list */ 100 pd_entry_t *mdpg_ptep_parent; /* for page descriptor page only */ 101 102 struct pmap_page mdpg_pp; 103 }; 104 105 /* each mdpg_pp.pp_pvlock will be initialized in pmap_init() */ 106 #define VM_MDPAGE_INIT(pg) \ 107 do { \ 108 LIST_INIT(&(pg)->mdpage.mdpg_pp.pp_pvhead); \ 109 (pg)->mdpage.mdpg_pp.pp_flags = 0; \ 110 } while (/*CONSTCOND*/ 0) 111 112 113 /* saved permission bit for referenced/modified emulation */ 114 #define LX_BLKPAG_OS_READ LX_BLKPAG_OS_0 115 #define LX_BLKPAG_OS_WRITE LX_BLKPAG_OS_1 116 #define LX_BLKPAG_OS_WIRED LX_BLKPAG_OS_2 117 #define LX_BLKPAG_OS_BOOT LX_BLKPAG_OS_3 118 #define LX_BLKPAG_OS_RWMASK (LX_BLKPAG_OS_WRITE|LX_BLKPAG_OS_READ) 119 120 /* memory attributes are configured MAIR_EL1 in locore */ 121 #define LX_BLKPAG_ATTR_NORMAL_WB __SHIFTIN(0, LX_BLKPAG_ATTR_INDX) 122 #define LX_BLKPAG_ATTR_NORMAL_NC __SHIFTIN(1, LX_BLKPAG_ATTR_INDX) 123 #define LX_BLKPAG_ATTR_NORMAL_WT __SHIFTIN(2, LX_BLKPAG_ATTR_INDX) 124 #define LX_BLKPAG_ATTR_DEVICE_MEM __SHIFTIN(3, LX_BLKPAG_ATTR_INDX) 125 #define LX_BLKPAG_ATTR_DEVICE_MEM_SO __SHIFTIN(4, LX_BLKPAG_ATTR_INDX) 126 #define LX_BLKPAG_ATTR_MASK LX_BLKPAG_ATTR_INDX 127 128 #define lxpde_pa(pde) ((paddr_t)((pde) & LX_TBL_PA)) 129 #define lxpde_valid(pde) (((pde) & LX_VALID) == LX_VALID) 130 #define l0pde_pa(pde) lxpde_pa(pde) 131 #define l0pde_index(v) (((vaddr_t)(v) & L0_ADDR_BITS) >> L0_SHIFT) 132 #define l0pde_valid(pde) lxpde_valid(pde) 133 /* l0pte always contains table entries */ 134 135 #define l1pde_pa(pde) lxpde_pa(pde) 136 #define l1pde_index(v) (((vaddr_t)(v) & L1_ADDR_BITS) >> L1_SHIFT) 137 #define l1pde_valid(pde) lxpde_valid(pde) 138 #define l1pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK) 139 #define l1pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL) 140 141 #define l2pde_pa(pde) lxpde_pa(pde) 142 #define l2pde_index(v) (((vaddr_t)(v) & L2_ADDR_BITS) >> L2_SHIFT) 143 #define l2pde_valid(pde) lxpde_valid(pde) 144 #define l2pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK) 145 #define l2pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL) 146 147 #define l3pte_pa(pde) lxpde_pa(pde) 148 #define l3pte_executable(pde,user) \ 149 (((pde) & ((user) ? LX_BLKPAG_UXN : LX_BLKPAG_PXN)) == 0) 150 #define l3pte_readable(pde) ((pde) & LX_BLKPAG_AF) 151 #define l3pte_writable(pde) \ 152 (((pde) & (LX_BLKPAG_AF|LX_BLKPAG_AP)) == (LX_BLKPAG_AF|LX_BLKPAG_AP_RW)) 153 #define l3pte_index(v) (((vaddr_t)(v) & L3_ADDR_BITS) >> L3_SHIFT) 154 #define l3pte_valid(pde) lxpde_valid(pde) 155 #define l3pte_is_page(pde) (((pde) & LX_TYPE) == L3_TYPE_PAG) 156 /* l3pte contains always page entries */ 157 158 void pmap_bootstrap(vaddr_t, vaddr_t); 159 bool pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, bool user); 160 161 /* for ddb */ 162 void pmap_db_pteinfo(vaddr_t, void (*)(const char *, ...) __printflike(1, 2)); 163 void pmap_db_ttbrdump(bool, vaddr_t, void (*)(const char *, ...) 164 __printflike(1, 2)); 165 pt_entry_t *kvtopte(vaddr_t); 166 pt_entry_t pmap_kvattr(vaddr_t, vm_prot_t); 167 168 /* locore.S */ 169 pd_entry_t *bootpage_alloc(void); 170 171 /* pmap_locore.c */ 172 int pmapboot_enter(vaddr_t, paddr_t, psize_t, psize_t, 173 pt_entry_t, uint64_t, pd_entry_t *(*)(void), 174 void (*pr)(const char *, ...) __printflike(1, 2)); 175 #define PMAPBOOT_ENTER_NOBLOCK 0x00000001 176 #define PMAPBOOT_ENTER_NOOVERWRITE 0x00000002 177 int pmapboot_enter_range(vaddr_t, paddr_t, psize_t, pt_entry_t, uint64_t, 178 pd_entry_t *(*)(void), void (*)(const char *, ...) __printflike(1, 2)); 179 int pmapboot_protect(vaddr_t, vaddr_t, vm_prot_t); 180 void pmap_db_pte_print(pt_entry_t, int, 181 void (*pr)(const char *, ...) __printflike(1, 2)); 182 183 /* Hooks for the pool allocator */ 184 paddr_t vtophys(vaddr_t); 185 #define VTOPHYS_FAILED ((paddr_t)-1L) /* POOL_PADDR_INVALID */ 186 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 187 188 189 /* devmap */ 190 struct pmap_devmap { 191 vaddr_t pd_va; /* virtual address */ 192 paddr_t pd_pa; /* physical address */ 193 psize_t pd_size; /* size of region */ 194 vm_prot_t pd_prot; /* protection code */ 195 u_int pd_flags; /* flags for pmap_kenter_pa() */ 196 }; 197 198 void pmap_devmap_register(const struct pmap_devmap *); 199 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 200 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 201 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 202 vaddr_t pmap_devmap_phystov(paddr_t); 203 paddr_t pmap_devmap_vtophys(paddr_t); 204 205 paddr_t pmap_alloc_pdp(struct pmap *, struct vm_page **, int, bool); 206 207 #define L1_TRUNC_BLOCK(x) ((x) & L1_FRAME) 208 #define L1_ROUND_BLOCK(x) L1_TRUNC_BLOCK((x) + L1_SIZE - 1) 209 #define L2_TRUNC_BLOCK(x) ((x) & L2_FRAME) 210 #define L2_ROUND_BLOCK(x) L2_TRUNC_BLOCK((x) + L2_SIZE - 1) 211 #define L3_TRUNC_BLOCK(x) ((x) & L3_FRAME) 212 #define L3_ROUND_BLOCK(x) L3_TRUNC_BLOCK((x) + L3_SIZE - 1) 213 214 #define DEVMAP_ALIGN(x) L3_TRUNC_BLOCK((x)) 215 #define DEVMAP_SIZE(x) L3_ROUND_BLOCK((x)) 216 217 #define DEVMAP_ENTRY(va, pa, sz) \ 218 { \ 219 .pd_va = DEVMAP_ALIGN(va), \ 220 .pd_pa = DEVMAP_ALIGN(pa), \ 221 .pd_size = DEVMAP_SIZE(sz), \ 222 .pd_prot = VM_PROT_READ|VM_PROT_WRITE, \ 223 .pd_flags = PMAP_DEV \ 224 } 225 #define DEVMAP_ENTRY_END { 0 } 226 227 /* mmap cookie and flags */ 228 #define AARCH64_MMAP_FLAG_SHIFT (64 - PGSHIFT) 229 #define AARCH64_MMAP_FLAG_MASK 0xf 230 #define AARCH64_MMAP_WRITEBACK 0UL 231 #define AARCH64_MMAP_NOCACHE 1UL 232 #define AARCH64_MMAP_WRITECOMBINE 2UL 233 #define AARCH64_MMAP_DEVICE 3UL 234 235 #define ARM_MMAP_MASK __BITS(63, AARCH64_MMAP_FLAG_SHIFT) 236 #define ARM_MMAP_WRITECOMBINE __SHIFTIN(AARCH64_MMAP_WRITECOMBINE, ARM_MMAP_MASK) 237 #define ARM_MMAP_WRITEBACK __SHIFTIN(AARCH64_MMAP_WRITEBACK, ARM_MMAP_MASK) 238 #define ARM_MMAP_NOCACHE __SHIFTIN(AARCH64_MMAP_NOCACHE, ARM_MMAP_MASK) 239 #define ARM_MMAP_DEVICE __SHIFTIN(AARCH64_MMAP_DEVICE, ARM_MMAP_MASK) 240 241 #define PMAP_PTE 0x10000000 /* kenter_pa */ 242 #define PMAP_DEV 0x20000000 /* kenter_pa */ 243 #define PMAP_DEV_SO 0x40000000 /* kenter_pa */ 244 #define PMAP_DEV_MASK (PMAP_DEV | PMAP_DEV_SO) 245 246 static inline u_int 247 aarch64_mmap_flags(paddr_t mdpgno) 248 { 249 u_int nflag, pflag; 250 251 /* 252 * aarch64 arch has 5 memory attribute: 253 * 254 * WriteBack - write back cache 255 * WriteThru - write through cache 256 * NoCache - no cache 257 * Device(nGnRE) - no Gathering, no Reordering, Early write ack 258 * Device(nGnRnE) - no Gathering, no Reordering, no Early write ack 259 * 260 * but pmap has PMAP_{NOCACHE,WRITE_COMBINE,WRITE_BACK} flags. 261 */ 262 263 nflag = (mdpgno >> AARCH64_MMAP_FLAG_SHIFT) & AARCH64_MMAP_FLAG_MASK; 264 switch (nflag) { 265 case AARCH64_MMAP_DEVICE: 266 pflag = PMAP_DEV; 267 break; 268 case AARCH64_MMAP_WRITECOMBINE: 269 pflag = PMAP_WRITE_COMBINE; 270 break; 271 case AARCH64_MMAP_WRITEBACK: 272 pflag = PMAP_WRITE_BACK; 273 break; 274 case AARCH64_MMAP_NOCACHE: 275 default: 276 pflag = PMAP_NOCACHE; 277 break; 278 } 279 return pflag; 280 } 281 282 /* 283 * Which is the address space of this VA? 284 * return the space considering TBI. (PAC is not yet) 285 * 286 * return value: AARCH64_ADDRSPACE_{LOWER,UPPER}{_OUTOFRANGE}? 287 */ 288 #define AARCH64_ADDRTOP_TAG __BIT(55) /* ECR_EL1.TBI[01]=1 */ 289 #define AARCH64_ADDRTOP_MSB __BIT(63) /* ECR_EL1.TBI[01]=0 */ 290 #define AARCH64_ADDRESS_TAG_MASK __BITS(63,56) /* if TCR.TBI[01]=1 */ 291 #define AARCH64_ADDRESS_PAC_MASK __BITS(54,48) /* depend on VIRT_BIT */ 292 #define AARCH64_ADDRESS_TAGPAC_MASK \ 293 (AARCH64_ADDRESS_TAG_MASK|AARCH64_ADDRESS_PAC_MASK) 294 295 #define AARCH64_ADDRSPACE_LOWER 0 /* -> TTBR0 */ 296 #define AARCH64_ADDRSPACE_UPPER 1 /* -> TTBR1 */ 297 #define AARCH64_ADDRSPACE_LOWER_OUTOFRANGE -1 /* certainly fault */ 298 #define AARCH64_ADDRSPACE_UPPER_OUTOFRANGE -2 /* certainly fault */ 299 static inline int 300 aarch64_addressspace(vaddr_t va) 301 { 302 uint64_t addrtop, tbi; 303 304 addrtop = (uint64_t)va & AARCH64_ADDRTOP_TAG; 305 tbi = addrtop ? TCR_TBI1 : TCR_TBI0; 306 if (reg_tcr_el1_read() & tbi) { 307 if (addrtop == 0) { 308 /* lower address, and TBI0 enabled */ 309 if ((va & AARCH64_ADDRESS_PAC_MASK) != 0) 310 return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE; 311 return AARCH64_ADDRSPACE_LOWER; 312 } 313 /* upper address, and TBI1 enabled */ 314 if ((va & AARCH64_ADDRESS_PAC_MASK) != AARCH64_ADDRESS_PAC_MASK) 315 return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE; 316 return AARCH64_ADDRSPACE_UPPER; 317 } 318 319 addrtop = (uint64_t)va & AARCH64_ADDRTOP_MSB; 320 if (addrtop == 0) { 321 /* lower address, and TBI0 disabled */ 322 if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != 0) 323 return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE; 324 return AARCH64_ADDRSPACE_LOWER; 325 } 326 /* upper address, and TBI1 disabled */ 327 if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != AARCH64_ADDRESS_TAGPAC_MASK) 328 return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE; 329 return AARCH64_ADDRSPACE_UPPER; 330 } 331 332 static inline vaddr_t 333 aarch64_untag_address(vaddr_t va) 334 { 335 uint64_t addrtop, tbi; 336 337 addrtop = (uint64_t)va & AARCH64_ADDRTOP_TAG; 338 tbi = addrtop ? TCR_TBI1 : TCR_TBI0; 339 if (reg_tcr_el1_read() & tbi) { 340 if (addrtop == 0) { 341 /* lower address, and TBI0 enabled */ 342 return (uint64_t)va & ~AARCH64_ADDRESS_TAG_MASK; 343 } 344 /* upper address, and TBI1 enabled */ 345 return (uint64_t)va | AARCH64_ADDRESS_TAG_MASK; 346 } 347 348 /* TBI[01] is disabled, nothing to do */ 349 return va; 350 } 351 352 #define pmap_phys_address(pa) aarch64_ptob((pa)) 353 #define pmap_mmap_flags(ppn) aarch64_mmap_flags((ppn)) 354 355 #define pmap_update(pmap) ((void)0) 356 #define pmap_copy(dp,sp,d,l,s) ((void)0) 357 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 358 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 359 360 void pmap_procwr(struct proc *, vaddr_t, int); 361 bool pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *); 362 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t); 363 364 void pmap_pv_init(void); 365 void pmap_pv_track(paddr_t, psize_t); 366 void pmap_pv_untrack(paddr_t, psize_t); 367 void pmap_pv_protect(paddr_t, vm_prot_t); 368 369 #define PMAP_MAPSIZE1 L2_SIZE 370 371 #endif /* _KERNEL */ 372 373 #elif defined(__arm__) 374 375 #include <arm/pmap.h> 376 377 #endif /* __arm__/__aarch64__ */ 378 379 #endif /* !_AARCH64_PMAP_ */ 380
Indexes created Thu Oct 02 01:09:59 GMT 2025