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pmap.h revision 1.37 
      1 /* $NetBSD: pmap.h,v 1.37 2020/04/08 00:13:40 ryo Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2014 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Matt Thomas of 3am Software Foundry.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _AARCH64_PMAP_H_
     33 #define _AARCH64_PMAP_H_
     34 
     35 #ifdef __aarch64__
     36 
     37 #ifdef _KERNEL
     38 #ifdef _KERNEL_OPT
     39 #include "opt_kasan.h"
     40 #endif
     41 
     42 #include <sys/types.h>
     43 #include <sys/pool.h>
     44 #include <sys/queue.h>
     45 #include <uvm/uvm_pglist.h>
     46 
     47 #include <aarch64/armreg.h>
     48 #include <aarch64/pte.h>
     49 
     50 #define PMAP_NEED_PROCWR
     51 #define PMAP_GROWKERNEL
     52 #define PMAP_STEAL_MEMORY
     53 
     54 #define __HAVE_VM_PAGE_MD
     55 #define __HAVE_PMAP_PV_TRACK	1
     56 
     57 #ifndef KASAN
     58 #define PMAP_MAP_POOLPAGE(pa)		AARCH64_PA_TO_KVA(pa)
     59 #define PMAP_UNMAP_POOLPAGE(va)		AARCH64_KVA_TO_PA(va)
     60 
     61 #define PMAP_DIRECT
     62 static __inline int
     63 pmap_direct_process(paddr_t pa, voff_t pgoff, size_t len,
     64     int (*process)(void *, size_t, void *), void *arg)
     65 {
     66 	vaddr_t va = AARCH64_PA_TO_KVA(pa);
     67 
     68 	return process((void *)(va + pgoff), len, arg);
     69 }
     70 #endif
     71 
     72 struct pmap {
     73 	kmutex_t pm_lock;
     74 	struct pool *pm_pvpool;
     75 	pd_entry_t *pm_l0table;			/* L0 table: 512G*512 */
     76 	paddr_t pm_l0table_pa;
     77 
     78 	LIST_HEAD(, vm_page) pm_vmlist;		/* for L[0123] tables */
     79 
     80 	struct pmap_statistics pm_stats;
     81 	unsigned int pm_refcnt;
     82 	unsigned int pm_idlepdp;
     83 	int pm_asid;
     84 	bool pm_activated;
     85 };
     86 
     87 struct pv_entry;
     88 
     89 struct pmap_page {
     90 	kmutex_t pp_pvlock;
     91 	LIST_HEAD(, pv_entry) pp_pvhead;
     92 
     93 	/* VM_PROT_READ means referenced, VM_PROT_WRITE means modified */
     94 	uint32_t pp_flags;
     95 };
     96 
     97 struct vm_page_md {
     98 	LIST_ENTRY(vm_page) mdpg_vmlist;	/* L[0123] table vm_page list */
     99 	pd_entry_t *mdpg_ptep_parent;	/* for page descriptor page only */
    100 
    101 	struct pmap_page mdpg_pp;
    102 };
    103 
    104 /* each mdpg_pp.pp_pvlock will be initialized in pmap_init() */
    105 #define VM_MDPAGE_INIT(pg)					\
    106 	do {							\
    107 		LIST_INIT(&(pg)->mdpage.mdpg_pp.pp_pvhead);	\
    108 		(pg)->mdpage.mdpg_pp.pp_flags = 0;		\
    109 	} while (/*CONSTCOND*/ 0)
    110 
    111 #define PMAP_PAGE_INIT(pp)						\
    112 	do {								\
    113 		mutex_init(&(pp)->pp_pvlock, MUTEX_SPIN, IPL_VM);	\
    114 	} while (/*CONSTCOND*/ 0)
    115 
    116 /* saved permission bit for referenced/modified emulation */
    117 #define LX_BLKPAG_OS_READ		LX_BLKPAG_OS_0
    118 #define LX_BLKPAG_OS_WRITE		LX_BLKPAG_OS_1
    119 #define LX_BLKPAG_OS_WIRED		LX_BLKPAG_OS_2
    120 #define LX_BLKPAG_OS_BOOT		LX_BLKPAG_OS_3
    121 #define LX_BLKPAG_OS_RWMASK		(LX_BLKPAG_OS_WRITE|LX_BLKPAG_OS_READ)
    122 
    123 /* memory attributes are configured MAIR_EL1 in locore */
    124 #define LX_BLKPAG_ATTR_NORMAL_WB	__SHIFTIN(0, LX_BLKPAG_ATTR_INDX)
    125 #define LX_BLKPAG_ATTR_NORMAL_NC	__SHIFTIN(1, LX_BLKPAG_ATTR_INDX)
    126 #define LX_BLKPAG_ATTR_NORMAL_WT	__SHIFTIN(2, LX_BLKPAG_ATTR_INDX)
    127 #define LX_BLKPAG_ATTR_DEVICE_MEM	__SHIFTIN(3, LX_BLKPAG_ATTR_INDX)
    128 #define LX_BLKPAG_ATTR_DEVICE_MEM_SO	__SHIFTIN(4, LX_BLKPAG_ATTR_INDX)
    129 #define LX_BLKPAG_ATTR_MASK		LX_BLKPAG_ATTR_INDX
    130 
    131 #define lxpde_pa(pde)		((paddr_t)((pde) & LX_TBL_PA))
    132 #define lxpde_valid(pde)	(((pde) & LX_VALID) == LX_VALID)
    133 #define l0pde_pa(pde)		lxpde_pa(pde)
    134 #define l0pde_index(v)		(((vaddr_t)(v) & L0_ADDR_BITS) >> L0_SHIFT)
    135 #define l0pde_valid(pde)	lxpde_valid(pde)
    136 /* l0pte always contains table entries */
    137 
    138 #define l1pde_pa(pde)		lxpde_pa(pde)
    139 #define l1pde_index(v)		(((vaddr_t)(v) & L1_ADDR_BITS) >> L1_SHIFT)
    140 #define l1pde_valid(pde)	lxpde_valid(pde)
    141 #define l1pde_is_block(pde)	(((pde) & LX_TYPE) == LX_TYPE_BLK)
    142 #define l1pde_is_table(pde)	(((pde) & LX_TYPE) == LX_TYPE_TBL)
    143 
    144 #define l2pde_pa(pde)		lxpde_pa(pde)
    145 #define l2pde_index(v)		(((vaddr_t)(v) & L2_ADDR_BITS) >> L2_SHIFT)
    146 #define l2pde_valid(pde)	lxpde_valid(pde)
    147 #define l2pde_is_block(pde)	(((pde) & LX_TYPE) == LX_TYPE_BLK)
    148 #define l2pde_is_table(pde)	(((pde) & LX_TYPE) == LX_TYPE_TBL)
    149 
    150 #define l3pte_pa(pde)		lxpde_pa(pde)
    151 #define l3pte_executable(pde,user)	\
    152     (((pde) & ((user) ? LX_BLKPAG_UXN : LX_BLKPAG_PXN)) == 0)
    153 #define l3pte_readable(pde)	((pde) & LX_BLKPAG_AF)
    154 #define l3pte_writable(pde)	\
    155     (((pde) & (LX_BLKPAG_AF|LX_BLKPAG_AP)) == (LX_BLKPAG_AF|LX_BLKPAG_AP_RW))
    156 #define l3pte_index(v)		(((vaddr_t)(v) & L3_ADDR_BITS) >> L3_SHIFT)
    157 #define l3pte_valid(pde)	lxpde_valid(pde)
    158 #define l3pte_is_page(pde)	(((pde) & LX_TYPE) == L3_TYPE_PAG)
    159 /* l3pte contains always page entries */
    160 
    161 void pmap_bootstrap(vaddr_t, vaddr_t);
    162 bool pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, bool user);
    163 
    164 /* for ddb */
    165 void pmap_db_pteinfo(vaddr_t, void (*)(const char *, ...) __printflike(1, 2));
    166 void pmap_db_ttbrdump(bool, vaddr_t, void (*)(const char *, ...)
    167     __printflike(1, 2));
    168 pt_entry_t *kvtopte(vaddr_t);
    169 pt_entry_t pmap_kvattr(vaddr_t, vm_prot_t);
    170 
    171 /* locore.S */
    172 pd_entry_t *bootpage_alloc(void);
    173 
    174 /* pmap_locore.c */
    175 int pmapboot_enter(vaddr_t, paddr_t, psize_t, psize_t,
    176     pt_entry_t, uint64_t, pd_entry_t *(*)(void),
    177     void (*pr)(const char *, ...) __printflike(1, 2));
    178 #define PMAPBOOT_ENTER_NOBLOCK		0x00000001
    179 #define PMAPBOOT_ENTER_NOOVERWRITE	0x00000002
    180 int pmapboot_enter_range(vaddr_t, paddr_t, psize_t, pt_entry_t, uint64_t,
    181     pd_entry_t *(*)(void), void (*)(const char *, ...) __printflike(1, 2));
    182 int pmapboot_protect(vaddr_t, vaddr_t, vm_prot_t);
    183 void pmap_db_pte_print(pt_entry_t, int,
    184     void (*pr)(const char *, ...) __printflike(1, 2));
    185 
    186 /* Hooks for the pool allocator */
    187 paddr_t vtophys(vaddr_t);
    188 #define VTOPHYS_FAILED		((paddr_t)-1L)	/* POOL_PADDR_INVALID */
    189 #define POOL_VTOPHYS(va)	vtophys((vaddr_t) (va))
    190 
    191 
    192 /* devmap */
    193 struct pmap_devmap {
    194 	vaddr_t pd_va;		/* virtual address */
    195 	paddr_t pd_pa;		/* physical address */
    196 	psize_t pd_size;	/* size of region */
    197 	vm_prot_t pd_prot;	/* protection code */
    198 	u_int pd_flags;		/* flags for pmap_kenter_pa() */
    199 };
    200 
    201 void pmap_devmap_register(const struct pmap_devmap *);
    202 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *);
    203 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t);
    204 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t);
    205 vaddr_t pmap_devmap_phystov(paddr_t);
    206 paddr_t pmap_devmap_vtophys(paddr_t);
    207 
    208 paddr_t pmap_alloc_pdp(struct pmap *, struct vm_page **, int, bool);
    209 
    210 #define L1_TRUNC_BLOCK(x)	((x) & L1_FRAME)
    211 #define L1_ROUND_BLOCK(x)	L1_TRUNC_BLOCK((x) + L1_SIZE - 1)
    212 #define L2_TRUNC_BLOCK(x)	((x) & L2_FRAME)
    213 #define L2_ROUND_BLOCK(x)	L2_TRUNC_BLOCK((x) + L2_SIZE - 1)
    214 #define L3_TRUNC_BLOCK(x)	((x) & L3_FRAME)
    215 #define L3_ROUND_BLOCK(x)	L3_TRUNC_BLOCK((x) + L3_SIZE - 1)
    216 
    217 #define DEVMAP_ALIGN(x)		L3_TRUNC_BLOCK((x))
    218 #define DEVMAP_SIZE(x)		L3_ROUND_BLOCK((x))
    219 
    220 #define	DEVMAP_ENTRY(va, pa, sz)			\
    221 	{						\
    222 		.pd_va = DEVMAP_ALIGN(va),		\
    223 		.pd_pa = DEVMAP_ALIGN(pa),		\
    224 		.pd_size = DEVMAP_SIZE(sz),			\
    225 		.pd_prot = VM_PROT_READ|VM_PROT_WRITE,	\
    226 		.pd_flags = PMAP_DEV			\
    227 	}
    228 #define	DEVMAP_ENTRY_END	{ 0 }
    229 
    230 /* mmap cookie and flags */
    231 #define AARCH64_MMAP_FLAG_SHIFT		(64 - PGSHIFT)
    232 #define AARCH64_MMAP_FLAG_MASK		0xf
    233 #define AARCH64_MMAP_WRITEBACK		0UL
    234 #define AARCH64_MMAP_NOCACHE		1UL
    235 #define AARCH64_MMAP_WRITECOMBINE	2UL
    236 #define AARCH64_MMAP_DEVICE		3UL
    237 
    238 #define ARM_MMAP_MASK			__BITS(63, AARCH64_MMAP_FLAG_SHIFT)
    239 #define ARM_MMAP_WRITECOMBINE		__SHIFTIN(AARCH64_MMAP_WRITECOMBINE, ARM_MMAP_MASK)
    240 #define ARM_MMAP_WRITEBACK		__SHIFTIN(AARCH64_MMAP_WRITEBACK, ARM_MMAP_MASK)
    241 #define ARM_MMAP_NOCACHE		__SHIFTIN(AARCH64_MMAP_NOCACHE, ARM_MMAP_MASK)
    242 #define ARM_MMAP_DEVICE			__SHIFTIN(AARCH64_MMAP_DEVICE, ARM_MMAP_MASK)
    243 
    244 #define	PMAP_PTE			0x10000000 /* kenter_pa */
    245 #define	PMAP_DEV			0x20000000 /* kenter_pa */
    246 #define	PMAP_DEV_SO			0x40000000 /* kenter_pa */
    247 #define	PMAP_DEV_MASK			(PMAP_DEV | PMAP_DEV_SO)
    248 
    249 static inline u_int
    250 aarch64_mmap_flags(paddr_t mdpgno)
    251 {
    252 	u_int nflag, pflag;
    253 
    254 	/*
    255 	 * aarch64 arch has 5 memory attribute:
    256 	 *
    257 	 *  WriteBack      - write back cache
    258 	 *  WriteThru      - write through cache
    259 	 *  NoCache        - no cache
    260 	 *  Device(nGnRE)  - no Gathering, no Reordering, Early write ack
    261 	 *  Device(nGnRnE) - no Gathering, no Reordering, no Early write ack
    262 	 *
    263 	 * but pmap has PMAP_{NOCACHE,WRITE_COMBINE,WRITE_BACK} flags.
    264 	 */
    265 
    266 	nflag = (mdpgno >> AARCH64_MMAP_FLAG_SHIFT) & AARCH64_MMAP_FLAG_MASK;
    267 	switch (nflag) {
    268 	case AARCH64_MMAP_DEVICE:
    269 		pflag = PMAP_DEV;
    270 		break;
    271 	case AARCH64_MMAP_WRITECOMBINE:
    272 		pflag = PMAP_WRITE_COMBINE;
    273 		break;
    274 	case AARCH64_MMAP_WRITEBACK:
    275 		pflag = PMAP_WRITE_BACK;
    276 		break;
    277 	case AARCH64_MMAP_NOCACHE:
    278 	default:
    279 		pflag = PMAP_NOCACHE;
    280 		break;
    281 	}
    282 	return pflag;
    283 }
    284 
    285 /*
    286  * Which is the address space of this VA?
    287  * return the space considering TBI. (PAC is not yet)
    288  *
    289  * return value: AARCH64_ADDRSPACE_{LOWER,UPPER}{_OUTOFRANGE}?
    290  */
    291 #define AARCH64_ADDRTOP_TAG		__BIT(55)	/* ECR_EL1.TBI[01]=1 */
    292 #define AARCH64_ADDRTOP_MSB		__BIT(63)	/* ECR_EL1.TBI[01]=0 */
    293 #define AARCH64_ADDRESS_TAG_MASK	__BITS(63,56)	/* if TCR.TBI[01]=1 */
    294 #define AARCH64_ADDRESS_PAC_MASK	__BITS(54,48)	/* depend on VIRT_BIT */
    295 #define AARCH64_ADDRESS_TAGPAC_MASK	\
    296 			(AARCH64_ADDRESS_TAG_MASK|AARCH64_ADDRESS_PAC_MASK)
    297 
    298 #define AARCH64_ADDRSPACE_LOWER			0	/* -> TTBR0 */
    299 #define AARCH64_ADDRSPACE_UPPER			1	/* -> TTBR1 */
    300 #define AARCH64_ADDRSPACE_LOWER_OUTOFRANGE	-1	/* certainly fault */
    301 #define AARCH64_ADDRSPACE_UPPER_OUTOFRANGE	-2	/* certainly fault */
    302 static inline int
    303 aarch64_addressspace(vaddr_t va)
    304 {
    305 	uint64_t addrtop, tbi;
    306 
    307 	addrtop = (uint64_t)va & AARCH64_ADDRTOP_TAG;
    308 	tbi = addrtop ? TCR_TBI1 : TCR_TBI0;
    309 	if (reg_tcr_el1_read() & tbi) {
    310 		if (addrtop == 0) {
    311 			/* lower address, and TBI0 enabled */
    312 			if ((va & AARCH64_ADDRESS_PAC_MASK) != 0)
    313 				return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE;
    314 			return AARCH64_ADDRSPACE_LOWER;
    315 		}
    316 		/* upper address, and TBI1 enabled */
    317 		if ((va & AARCH64_ADDRESS_PAC_MASK) != AARCH64_ADDRESS_PAC_MASK)
    318 			return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE;
    319 		return AARCH64_ADDRSPACE_UPPER;
    320 	}
    321 
    322 	addrtop = (uint64_t)va & AARCH64_ADDRTOP_MSB;
    323 	if (addrtop == 0) {
    324 		/* lower address, and TBI0 disabled */
    325 		if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != 0)
    326 			return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE;
    327 		return AARCH64_ADDRSPACE_LOWER;
    328 	}
    329 	/* upper address, and TBI1 disabled */
    330 	if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != AARCH64_ADDRESS_TAGPAC_MASK)
    331 		return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE;
    332 	return AARCH64_ADDRSPACE_UPPER;
    333 }
    334 
    335 static inline vaddr_t
    336 aarch64_untag_address(vaddr_t va)
    337 {
    338 	uint64_t addrtop, tbi;
    339 
    340 	addrtop = (uint64_t)va & AARCH64_ADDRTOP_TAG;
    341 	tbi = addrtop ? TCR_TBI1 : TCR_TBI0;
    342 	if (reg_tcr_el1_read() & tbi) {
    343 		if (addrtop == 0) {
    344 			/* lower address, and TBI0 enabled */
    345 			return (uint64_t)va & ~AARCH64_ADDRESS_TAG_MASK;
    346 		}
    347 		/* upper address, and TBI1 enabled */
    348 		return (uint64_t)va | AARCH64_ADDRESS_TAG_MASK;
    349 	}
    350 
    351 	/* TBI[01] is disabled, nothing to do */
    352 	return va;
    353 }
    354 
    355 #define pmap_phys_address(pa)		aarch64_ptob((pa))
    356 #define pmap_mmap_flags(ppn)		aarch64_mmap_flags((ppn))
    357 
    358 #define pmap_update(pmap)		((void)0)
    359 #define pmap_copy(dp,sp,d,l,s)		((void)0)
    360 #define pmap_wired_count(pmap)		((pmap)->pm_stats.wired_count)
    361 #define pmap_resident_count(pmap)	((pmap)->pm_stats.resident_count)
    362 
    363 void	pmap_procwr(struct proc *, vaddr_t, int);
    364 bool	pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *);
    365 void	pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t);
    366 
    367 void	pmap_pv_init(void);
    368 void	pmap_pv_track(paddr_t, psize_t);
    369 void	pmap_pv_untrack(paddr_t, psize_t);
    370 void	pmap_pv_protect(paddr_t, vm_prot_t);
    371 
    372 #define	PMAP_MAPSIZE1	L2_SIZE
    373 
    374 #endif /* _KERNEL */
    375 
    376 #elif defined(__arm__)
    377 
    378 #include <arm/pmap.h>
    379 
    380 #endif /* __arm__/__aarch64__ */
    381 
    382 #endif /* !_AARCH64_PMAP_ */
    383