pmap.h revision 1.5.2.2
1 /* $NetBSD: pmap.h,v 1.5.2.2 2020/04/08 14:07:24 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AARCH64_PMAP_H_ 33 #define _AARCH64_PMAP_H_ 34 35 #ifdef __aarch64__ 36 37 #ifdef _KERNEL 38 #ifdef _KERNEL_OPT 39 #include "opt_kasan.h" 40 #endif 41 42 #include <sys/types.h> 43 #include <sys/pool.h> 44 #include <sys/queue.h> 45 #include <uvm/uvm_pglist.h> 46 47 #include <aarch64/armreg.h> 48 #include <aarch64/pte.h> 49 50 #define PMAP_GROWKERNEL 51 #define PMAP_STEAL_MEMORY 52 53 #define __HAVE_VM_PAGE_MD 54 #define __HAVE_PMAP_PV_TRACK 1 55 56 #ifndef KASAN 57 #define PMAP_MAP_POOLPAGE(pa) AARCH64_PA_TO_KVA(pa) 58 #define PMAP_UNMAP_POOLPAGE(va) AARCH64_KVA_TO_PA(va) 59 60 #define PMAP_DIRECT 61 static __inline int 62 pmap_direct_process(paddr_t pa, voff_t pgoff, size_t len, 63 int (*process)(void *, size_t, void *), void *arg) 64 { 65 vaddr_t va = AARCH64_PA_TO_KVA(pa); 66 67 return process((void *)(va + pgoff), len, arg); 68 } 69 #endif 70 71 struct pmap { 72 kmutex_t pm_lock; 73 struct pool *pm_pvpool; 74 pd_entry_t *pm_l0table; /* L0 table: 512G*512 */ 75 paddr_t pm_l0table_pa; 76 77 LIST_HEAD(, vm_page) pm_vmlist; /* for L[0123] tables */ 78 79 struct pmap_statistics pm_stats; 80 unsigned int pm_refcnt; 81 unsigned int pm_idlepdp; 82 int pm_asid; 83 bool pm_activated; 84 }; 85 86 struct pv_entry; 87 88 struct pmap_page { 89 kmutex_t pp_pvlock; 90 LIST_HEAD(, pv_entry) pp_pvhead; 91 92 /* VM_PROT_READ means referenced, VM_PROT_WRITE means modified */ 93 uint32_t pp_flags; 94 #define PMAP_PAGE_FLAGS_PV_TRACKED 0x80000000 95 }; 96 97 struct vm_page_md { 98 LIST_ENTRY(vm_page) mdpg_vmlist; /* L[0123] table vm_page list */ 99 pd_entry_t *mdpg_ptep_parent; /* for page descriptor page only */ 100 101 struct pmap_page mdpg_pp; 102 }; 103 104 /* each mdpg_pp.pp_pvlock will be initialized in pmap_init() */ 105 #define VM_MDPAGE_INIT(pg) \ 106 do { \ 107 LIST_INIT(&(pg)->mdpage.mdpg_pp.pp_pvhead); \ 108 (pg)->mdpage.mdpg_pp.pp_flags = 0; \ 109 } while (/*CONSTCOND*/ 0) 110 111 112 /* saved permission bit for referenced/modified emulation */ 113 #define LX_BLKPAG_OS_READ LX_BLKPAG_OS_0 114 #define LX_BLKPAG_OS_WRITE LX_BLKPAG_OS_1 115 #define LX_BLKPAG_OS_WIRED LX_BLKPAG_OS_2 116 #define LX_BLKPAG_OS_BOOT LX_BLKPAG_OS_3 117 #define LX_BLKPAG_OS_RWMASK (LX_BLKPAG_OS_WRITE|LX_BLKPAG_OS_READ) 118 119 /* memory attributes are configured MAIR_EL1 in locore */ 120 #define LX_BLKPAG_ATTR_NORMAL_WB __SHIFTIN(0, LX_BLKPAG_ATTR_INDX) 121 #define LX_BLKPAG_ATTR_NORMAL_NC __SHIFTIN(1, LX_BLKPAG_ATTR_INDX) 122 #define LX_BLKPAG_ATTR_NORMAL_WT __SHIFTIN(2, LX_BLKPAG_ATTR_INDX) 123 #define LX_BLKPAG_ATTR_DEVICE_MEM __SHIFTIN(3, LX_BLKPAG_ATTR_INDX) 124 #define LX_BLKPAG_ATTR_DEVICE_MEM_SO __SHIFTIN(4, LX_BLKPAG_ATTR_INDX) 125 #define LX_BLKPAG_ATTR_MASK LX_BLKPAG_ATTR_INDX 126 127 #define lxpde_pa(pde) ((paddr_t)((pde) & LX_TBL_PA)) 128 #define lxpde_valid(pde) (((pde) & LX_VALID) == LX_VALID) 129 #define l0pde_pa(pde) lxpde_pa(pde) 130 #define l0pde_index(v) (((vaddr_t)(v) & L0_ADDR_BITS) >> L0_SHIFT) 131 #define l0pde_valid(pde) lxpde_valid(pde) 132 /* l0pte always contains table entries */ 133 134 #define l1pde_pa(pde) lxpde_pa(pde) 135 #define l1pde_index(v) (((vaddr_t)(v) & L1_ADDR_BITS) >> L1_SHIFT) 136 #define l1pde_valid(pde) lxpde_valid(pde) 137 #define l1pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK) 138 #define l1pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL) 139 140 #define l2pde_pa(pde) lxpde_pa(pde) 141 #define l2pde_index(v) (((vaddr_t)(v) & L2_ADDR_BITS) >> L2_SHIFT) 142 #define l2pde_valid(pde) lxpde_valid(pde) 143 #define l2pde_is_block(pde) (((pde) & LX_TYPE) == LX_TYPE_BLK) 144 #define l2pde_is_table(pde) (((pde) & LX_TYPE) == LX_TYPE_TBL) 145 146 #define l3pte_pa(pde) lxpde_pa(pde) 147 #define l3pte_executable(pde,user) \ 148 (((pde) & ((user) ? LX_BLKPAG_UXN : LX_BLKPAG_PXN)) == 0) 149 #define l3pte_readable(pde) ((pde) & LX_BLKPAG_AF) 150 #define l3pte_writable(pde) \ 151 (((pde) & (LX_BLKPAG_AF|LX_BLKPAG_AP)) == (LX_BLKPAG_AF|LX_BLKPAG_AP_RW)) 152 #define l3pte_index(v) (((vaddr_t)(v) & L3_ADDR_BITS) >> L3_SHIFT) 153 #define l3pte_valid(pde) lxpde_valid(pde) 154 #define l3pte_is_page(pde) (((pde) & LX_TYPE) == L3_TYPE_PAG) 155 /* l3pte contains always page entries */ 156 157 void pmap_bootstrap(vaddr_t, vaddr_t); 158 bool pmap_fault_fixup(struct pmap *, vaddr_t, vm_prot_t, bool user); 159 160 /* for ddb */ 161 void pmap_db_pteinfo(vaddr_t, void (*)(const char *, ...) __printflike(1, 2)); 162 void pmap_db_ttbrdump(bool, vaddr_t, void (*)(const char *, ...) 163 __printflike(1, 2)); 164 pt_entry_t *kvtopte(vaddr_t); 165 pt_entry_t pmap_kvattr(vaddr_t, vm_prot_t); 166 167 /* locore.S */ 168 pd_entry_t *bootpage_alloc(void); 169 170 /* pmap_locore.c */ 171 int pmapboot_enter(vaddr_t, paddr_t, psize_t, psize_t, 172 pt_entry_t, uint64_t, pd_entry_t *(*)(void), 173 void (*pr)(const char *, ...) __printflike(1, 2)); 174 #define PMAPBOOT_ENTER_NOBLOCK 0x00000001 175 #define PMAPBOOT_ENTER_NOOVERWRITE 0x00000002 176 int pmapboot_enter_range(vaddr_t, paddr_t, psize_t, pt_entry_t, uint64_t, 177 pd_entry_t *(*)(void), void (*)(const char *, ...) __printflike(1, 2)); 178 int pmapboot_protect(vaddr_t, vaddr_t, vm_prot_t); 179 void pmap_db_pte_print(pt_entry_t, int, 180 void (*pr)(const char *, ...) __printflike(1, 2)); 181 182 /* Hooks for the pool allocator */ 183 paddr_t vtophys(vaddr_t); 184 #define VTOPHYS_FAILED ((paddr_t)-1L) /* POOL_PADDR_INVALID */ 185 #define POOL_VTOPHYS(va) vtophys((vaddr_t) (va)) 186 187 188 /* devmap */ 189 struct pmap_devmap { 190 vaddr_t pd_va; /* virtual address */ 191 paddr_t pd_pa; /* physical address */ 192 psize_t pd_size; /* size of region */ 193 vm_prot_t pd_prot; /* protection code */ 194 u_int pd_flags; /* flags for pmap_kenter_pa() */ 195 }; 196 197 void pmap_devmap_register(const struct pmap_devmap *); 198 void pmap_devmap_bootstrap(vaddr_t, const struct pmap_devmap *); 199 const struct pmap_devmap *pmap_devmap_find_pa(paddr_t, psize_t); 200 const struct pmap_devmap *pmap_devmap_find_va(vaddr_t, vsize_t); 201 vaddr_t pmap_devmap_phystov(paddr_t); 202 paddr_t pmap_devmap_vtophys(paddr_t); 203 204 paddr_t pmap_alloc_pdp(struct pmap *, struct vm_page **, int, bool); 205 206 #define L1_TRUNC_BLOCK(x) ((x) & L1_FRAME) 207 #define L1_ROUND_BLOCK(x) L1_TRUNC_BLOCK((x) + L1_SIZE - 1) 208 #define L2_TRUNC_BLOCK(x) ((x) & L2_FRAME) 209 #define L2_ROUND_BLOCK(x) L2_TRUNC_BLOCK((x) + L2_SIZE - 1) 210 #define L3_TRUNC_BLOCK(x) ((x) & L3_FRAME) 211 #define L3_ROUND_BLOCK(x) L3_TRUNC_BLOCK((x) + L3_SIZE - 1) 212 213 #define DEVMAP_ALIGN(x) L3_TRUNC_BLOCK((x)) 214 #define DEVMAP_SIZE(x) L3_ROUND_BLOCK((x)) 215 216 #define DEVMAP_ENTRY(va, pa, sz) \ 217 { \ 218 .pd_va = DEVMAP_ALIGN(va), \ 219 .pd_pa = DEVMAP_ALIGN(pa), \ 220 .pd_size = DEVMAP_SIZE(sz), \ 221 .pd_prot = VM_PROT_READ|VM_PROT_WRITE, \ 222 .pd_flags = PMAP_NOCACHE \ 223 } 224 #define DEVMAP_ENTRY_END { 0 } 225 226 /* mmap cookie and flags */ 227 #define AARCH64_MMAP_FLAG_SHIFT (64 - PGSHIFT) 228 #define AARCH64_MMAP_FLAG_MASK 0xf 229 #define AARCH64_MMAP_WRITEBACK 0UL 230 #define AARCH64_MMAP_NOCACHE 1UL 231 #define AARCH64_MMAP_WRITECOMBINE 2UL 232 #define AARCH64_MMAP_DEVICE 3UL 233 234 #define ARM_MMAP_MASK __BITS(63, AARCH64_MMAP_FLAG_SHIFT) 235 #define ARM_MMAP_WRITECOMBINE __SHIFTIN(AARCH64_MMAP_WRITECOMBINE, ARM_MMAP_MASK) 236 #define ARM_MMAP_WRITEBACK __SHIFTIN(AARCH64_MMAP_WRITEBACK, ARM_MMAP_MASK) 237 #define ARM_MMAP_NOCACHE __SHIFTIN(AARCH64_MMAP_NOCACHE, ARM_MMAP_MASK) 238 #define ARM_MMAP_DEVICE __SHIFTIN(AARCH64_MMAP_DEVICE, ARM_MMAP_MASK) 239 240 #define PMAP_PTE 0x10000000 /* kenter_pa */ 241 #define PMAP_DEV 0x20000000 /* kenter_pa */ 242 #define PMAP_DEV_SO 0x40000000 /* kenter_pa */ 243 #define PMAP_DEV_MASK (PMAP_DEV | PMAP_DEV_SO) 244 245 static inline u_int 246 aarch64_mmap_flags(paddr_t mdpgno) 247 { 248 u_int nflag, pflag; 249 250 /* 251 * aarch64 arch has 5 memory attribute: 252 * 253 * WriteBack - write back cache 254 * WriteThru - write through cache 255 * NoCache - no cache 256 * Device(nGnRE) - no Gathering, no Reordering, Early write ack 257 * Device(nGnRnE) - no Gathering, no Reordering, no Early write ack 258 * 259 * but pmap has PMAP_{NOCACHE,WRITE_COMBINE,WRITE_BACK} flags. 260 */ 261 262 nflag = (mdpgno >> AARCH64_MMAP_FLAG_SHIFT) & AARCH64_MMAP_FLAG_MASK; 263 switch (nflag) { 264 case AARCH64_MMAP_DEVICE: 265 pflag = PMAP_DEV; 266 break; 267 case AARCH64_MMAP_WRITECOMBINE: 268 pflag = PMAP_WRITE_COMBINE; 269 break; 270 case AARCH64_MMAP_WRITEBACK: 271 pflag = PMAP_WRITE_BACK; 272 break; 273 case AARCH64_MMAP_NOCACHE: 274 default: 275 pflag = PMAP_NOCACHE; 276 break; 277 } 278 return pflag; 279 } 280 281 /* 282 * Which is the address space of this VA? 283 * return the space considering TBI. (PAC is not yet) 284 * 285 * return value: AARCH64_ADDRSPACE_{LOWER,UPPER}{_OUTOFRANGE}? 286 */ 287 #define AARCH64_ADDRTOP_TAG __BIT(55) /* ECR_EL1.TBI[01]=1 */ 288 #define AARCH64_ADDRTOP_MSB __BIT(63) /* ECR_EL1.TBI[01]=0 */ 289 #define AARCH64_ADDRESS_TAG_MASK __BITS(63,56) /* if TCR.TBI[01]=1 */ 290 #define AARCH64_ADDRESS_PAC_MASK __BITS(54,48) /* depend on VIRT_BIT */ 291 #define AARCH64_ADDRESS_TAGPAC_MASK \ 292 (AARCH64_ADDRESS_TAG_MASK|AARCH64_ADDRESS_PAC_MASK) 293 294 #define AARCH64_ADDRSPACE_LOWER 0 /* -> TTBR0 */ 295 #define AARCH64_ADDRSPACE_UPPER 1 /* -> TTBR1 */ 296 #define AARCH64_ADDRSPACE_LOWER_OUTOFRANGE -1 /* certainly fault */ 297 #define AARCH64_ADDRSPACE_UPPER_OUTOFRANGE -2 /* certainly fault */ 298 static inline int 299 aarch64_addressspace(vaddr_t va) 300 { 301 uint64_t addrtop, tbi; 302 303 addrtop = (uint64_t)va & AARCH64_ADDRTOP_TAG; 304 tbi = addrtop ? TCR_TBI1 : TCR_TBI0; 305 if (reg_tcr_el1_read() & tbi) { 306 if (addrtop == 0) { 307 /* lower address, and TBI0 enabled */ 308 if ((va & AARCH64_ADDRESS_PAC_MASK) != 0) 309 return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE; 310 return AARCH64_ADDRSPACE_LOWER; 311 } 312 /* upper address, and TBI1 enabled */ 313 if ((va & AARCH64_ADDRESS_PAC_MASK) != AARCH64_ADDRESS_PAC_MASK) 314 return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE; 315 return AARCH64_ADDRSPACE_UPPER; 316 } 317 318 addrtop = (uint64_t)va & AARCH64_ADDRTOP_MSB; 319 if (addrtop == 0) { 320 /* lower address, and TBI0 disabled */ 321 if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != 0) 322 return AARCH64_ADDRSPACE_LOWER_OUTOFRANGE; 323 return AARCH64_ADDRSPACE_LOWER; 324 } 325 /* upper address, and TBI1 disabled */ 326 if ((va & AARCH64_ADDRESS_TAGPAC_MASK) != AARCH64_ADDRESS_TAGPAC_MASK) 327 return AARCH64_ADDRSPACE_UPPER_OUTOFRANGE; 328 return AARCH64_ADDRSPACE_UPPER; 329 } 330 331 static inline vaddr_t 332 aarch64_untag_address(vaddr_t va) 333 { 334 uint64_t addrtop, tbi; 335 336 addrtop = (uint64_t)va & AARCH64_ADDRTOP_TAG; 337 tbi = addrtop ? TCR_TBI1 : TCR_TBI0; 338 if (reg_tcr_el1_read() & tbi) { 339 if (addrtop == 0) { 340 /* lower address, and TBI0 enabled */ 341 return (uint64_t)va & ~AARCH64_ADDRESS_TAG_MASK; 342 } 343 /* upper address, and TBI1 enabled */ 344 return (uint64_t)va | AARCH64_ADDRESS_TAG_MASK; 345 } 346 347 /* TBI[01] is disabled, nothing to do */ 348 return va; 349 } 350 351 #define pmap_phys_address(pa) aarch64_ptob((pa)) 352 #define pmap_mmap_flags(ppn) aarch64_mmap_flags((ppn)) 353 354 #define pmap_update(pmap) ((void)0) 355 #define pmap_copy(dp,sp,d,l,s) ((void)0) 356 #define pmap_wired_count(pmap) ((pmap)->pm_stats.wired_count) 357 #define pmap_resident_count(pmap) ((pmap)->pm_stats.resident_count) 358 359 bool pmap_extract_coherency(pmap_t, vaddr_t, paddr_t *, bool *); 360 void pmap_icache_sync_range(pmap_t, vaddr_t, vaddr_t); 361 362 void pmap_pv_init(void); 363 void pmap_pv_track(paddr_t, psize_t); 364 void pmap_pv_untrack(paddr_t, psize_t); 365 void pmap_pv_protect(paddr_t, vm_prot_t); 366 367 #define PMAP_MAPSIZE1 L2_SIZE 368 369 #endif /* _KERNEL */ 370 371 #elif defined(__arm__) 372 373 #include <arm/pmap.h> 374 375 #endif /* __arm__/__aarch64__ */ 376 377 #endif /* !_AARCH64_PMAP_ */ 378
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