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pte.h revision 1.1 
      1 /* $NetBSD: pte.h,v 1.1 2014/08/10 05:47:38 matt Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2014 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Matt Thomas of 3am Software Foundry.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     29  * POSSIBILITY OF SUCH DAMAGE.
     30  */
     31 
     32 #ifndef _AARCH64_PTE_H_
     33 #define _AARCH64_PTE_H_
     34 
     35 #ifdef __aarch64__
     36 
     37 typedef unsigned long long pt_entry_t;
     38 
     39 #define LX_VALID		__BIT(0)
     40 #define LX_TYPE			__BIT(1)
     41 #define LX_TYPE_BLK		__SHIFTOUT(0, LX_TYPE)
     42 #define LX_TYPE_TBL		__SHIFTOUT(1, LX_TYPE)
     43 #define L3_TYPE_PAG		__SHIFTOUT(1, LX_TYPE)
     44 
     45 #define	L1_BLK_OS		__BITS(58, 55)
     46 #define	L1_BLK_UXN		__BIT(54)
     47 #define	L1_BLK_PXN		__BIT(53)
     48 #define	L1_BLK_CONTIG		__BIT(52)
     49 #define	L1_BLK_OA		__BITS(47, 30)	/* 1GB */
     50 #define L1_BLK_NG		__BIT(11)	// Not Global
     51 #define L1_BLK_AF		__BIT(10)	// Access Flag
     52 #define L1_BLK_SH		__BITS(9,8)	// Shareability
     53 #define L1_BLK_AP		__BITS(7,6)
     54 #define L1_BLK_NS		__BIT(5)
     55 #define L1_BLK_ATTR_INDX	__BITS(4,2)
     56 
     57 #define LX_TBL_NLTA_4K		__BITS(47, 12)
     58 #define LX_TBL_NLTA_16K		__BITS(47, 14)
     59 #define LX_TBL_NLTA_64K		__BITS(47, 16)
     60 #define	L1_TBL_NS_TABLE		__BIT(63)
     61 #define	L1_TBL_AP_TABLE		__BITS(62,61)
     62 #define	L1_TBL_XN_TABLE		__BIT(60)
     63 #define	L1_TBL_PXN_TABLE	__BIT(59)
     64 
     65 #define	L2_BLKPAG_OS		__BITS(58, 55)
     66 #define	L2_BLKPAG_UXN		__BIT(54)
     67 #define	L2_BLKPAG_CONTIG	__BIT(52)
     68 #define	L2_BLK_OA_4K		__BITS(47, 21)	// 2MB
     69 #define	L2_BLK_OA_16K		__BITS(47, 25)	// 32MB
     70 #define	L2_BLK_OA_64K		__BITS(47, 29)	// 512MB
     71 #define L2_BLKPAG_AF		__BIT(10)	// Access Flag
     72 #define L2_BLKPAG_SH		__BITS(9,8)	// Shareability
     73 #define L2_BLKPAG_S2AP		__BITS(7,6)
     74 #define L2_BLKPAG_MEM_ATTR	__BITS(5,2)
     75 
     76 #define L3_PAG_OA_4K		__BITS(47, 12)
     77 #define L3_PAG_OA_16K		__BITS(47, 14)
     78 #define L3_PAG_OA_64K		__BITS(47, 16)
     79 
     80 #define TCR_TBI1		__BIT(38)	// ignore Top Byte for TTBR1_EL1
     81 #define TCR_TBI0		__BIT(37)	// ignore Top Byte for TTBR0_EL1
     82 #define TCR_AS64K		__BIT(36)	// Use 64K ASIDs
     83 #define TCR_IPS			__BITS(34,32)	// Intermediate Phys Addr Size
     84 #define	TCR_IPS_256TB		5		// 48 bits (256 TB)
     85 #define	TCR_IPS_64TB		4		// 44 bits  (16 TB)
     86 #define	TCR_IPS_4TB		3		// 42 bits  ( 4 TB)
     87 #define	TCR_IPS_1TB		2		// 40 bits  ( 1 TB)
     88 #define	TCR_IPS_64GB		1		// 36 bits  (64 GB)
     89 #define	TCR_IPS_4GB		0		// 32 bits   (4 GB)
     90 #define TCR_TG1			__BITS(31,30)	// Page Granule Size
     91 #define TCR_PAGE_SIZE1(tcr)	(1L << (__SHIFTOUT(tcr, TCR_TG1) * 2 + 10))
     92 #define	TCR_TG_4KB		1		// 4KB page size
     93 #define	TCR_TG_16KB		2		// 16KB page size
     94 #define	TCR_TG_64KB		3		// 64KB page size
     95 #define TCR_SH1			__BITS(29,28)
     96 #define TCR_SH_NONE		0
     97 #define TCR_SH_OUTER		1
     98 #define TCR_SH_INNER		2
     99 #define TCR_ORGN1		__BITS(27,26)
    100 #define	TCR_XRGN_NC		0		// Non Cacheable
    101 #define	TCR_XRGN_WB_WA		1		// WriteBack WriteAllocate
    102 #define	TCR_XRGN_WT		0		// WriteThrough
    103 #define	TCR_XRGN_WB		0		// WriteBack
    104 #define TCR_IRGN1		__BITS(25,24)
    105 #define TCR_EPD1		__BIT(23)	// Walk Disable for TTBR1_EL1
    106 #define TCR_A1			__BIT(22)	// ASID is in TTBR1_EL1
    107 #define TCR_T1SZ		__BITS(21,16)	// Size offset for TTBR1_EL1
    108 #define TCR_TG0			__BITS(15,14)
    109 #define TCR_SH0			__BITS(13,12)
    110 #define TCR_ORGN1		__BITS(11,10)
    111 #define TCR_IRGN1		__BITS(9,8)
    112 #define TCR_EPD0		__BIT(7)	// Walk Disable for TTBR0
    113 #define TCR_T0SZ		__BITS(5,0)	// Size offset for TTBR0_EL1
    114 
    115 #define	TTBR_ASID		__BITS(63, 48)
    116 #define	TTBR_BADDR		__BITS(47, 0)
    117 
    118 #elif defined(__arm__)
    119 
    120 #include <arm/pte.h>
    121 
    122 #endif /* __aarch64__/__arm__ */
    123 
    124 #endif /* _AARCH64_PTE_H_ */
    125