| History log of /src/sys/arch/aarch64/include/pte.h |
| Revision | | Date | Author | Comments |
| 1.14 |
| 19-Aug-2022 |
ryo | Fixed a bug that pte's __BIT(63,48) could be set when accessing addresses above 0x0001000000000000 in /dev/mem with mmap().
|
| 1.13 |
| 10-Oct-2021 |
skrll | Use sys/uvm/pmap/pmap_tlb.c on Aarch64 in the same way that some Arm, MIPS,
and some PPC kernels do. This removes the limitation of 256 processes on
CPUs with 8bit ASID field, e.g. Apple M1.
Additionally the following changes have been made
- removed a couple of unnecessary aarch64_tlbi_all calls
- removed any invalidation after freeing page tables due to
_pmap_sweep_pdp. This was never necessary afaict.
- all kernel mappings are marked global and userland mapping not-global.
Performance testing hasn't show a significant difference. The data here
is from building a kernel on an lx2k system with nvme.
before
1489.6u 400.4s 2:40.65 1176.5% 228+224k 0+32289io 57pf+0w
1482.6u 403.2s 2:38.49 1189.9% 228+222k 0+32274io 46pf+0w
1485.4u 402.2s 2:37.27 1200.2% 228+222k 0+32275io 12pf+0w
after
1493.9u 404.6s 2:37.50 1205.4% 227+221k 0+32265io 48pf+0w
1485.0u 408.0s 2:38.54 1194.0% 227+222k 0+32272io 36pf+0w
1484.3u 407.0s 2:35.88 1213.3% 228+224k 0+32268io 14pf+0w
>>> stats.ttest_ind([160.65,158.49,157.27], [157.5,158.54,155.88])
Ttest_indResult(statistic=1.1923622711296888, pvalue=0.2990182944606766)
>>>
|
| 1.12 |
| 29-Feb-2020 |
ryo | Fix pmap to work correctly with tagged addresses
- when fault, untag from address before passing to uvm/pmap functions
- pmap_extract() checks more strictly and consider the address tag
|
| 1.11 |
| 31-Jan-2020 |
maxv | BTI definitions.
|
| 1.10 |
| 11-Sep-2019 |
skrll | branches: 1.10.2;
Define PRIxPTE
|
| 1.9 |
| 11-Sep-2019 |
skrll | Move the TCR and TTBR defines into armreg.h where they below. NFCI.
|
| 1.8 |
| 11-Sep-2019 |
jmcneill | - Fix TCR_TG0 field definitions to match Armv8 ARM
- Rename TCR_IPS_64TB to TCR_IPS_16TB, add TCR_IPS_4PB
- Whitespace fixes
|
| 1.7 |
| 15-Aug-2019 |
skrll | Indent the field value defines. NFCI.
|
| 1.6 |
| 13-Aug-2019 |
skrll | Add DBM
|
| 1.5 |
| 04-Oct-2018 |
ryo | * define LX_BLKPAG_{OS,ATTR}_* for OS dependent PTE attributes in pmap.h
* cleanup macros
|
| 1.4 |
| 17-Jul-2018 |
ryo | fix build with aarch64 gcc/gas
|
| 1.3 |
| 01-Apr-2018 |
ryo | branches: 1.3.2;
Add initial support for ARMv8 (AARCH64) (by nisimura@ and ryo@)
- sys/arch/evbarm64 is gone and integrated into sys/arch/evbarm. (by skrll@)
- add support fdt. evbarm/conf/GENERIC64 fdt (bcm2837,sunxi,tegra) based generic 64bit kernel config. (by skrll@, jmcneill@)
|
| 1.2 |
| 16-Jan-2017 |
maya | branches: 1.2.12;
Correct definitions for TCR.
Values from ARM Cortex A-53 MPCore Processor Technical Reference Manual
4.3.48. Translation Control Register, EL1
|
| 1.1 |
| 10-Aug-2014 |
matt | branches: 1.1.4; 1.1.6; 1.1.10; 1.1.14;
Preliminary files for AARCH64 (64-bit ARM) support.
Enough for a distribution build.
|
| 1.1.14.1 |
| 21-Apr-2017 |
bouyer | Sync with HEAD
|
| 1.1.10.1 |
| 20-Mar-2017 |
pgoyette | Sync with HEAD
|
| 1.1.6.1 |
| 05-Feb-2017 |
skrll | Sync with HEAD
|
| 1.1.4.3 |
| 03-Dec-2017 |
jdolecek | update from HEAD
|
| 1.1.4.2 |
| 20-Aug-2014 |
tls | Rebase to HEAD as of a few days ago.
|
| 1.1.4.1 |
| 10-Aug-2014 |
tls | file pte.h was added on branch tls-maxphys on 2014-08-20 00:02:39 +0000
|
| 1.2.12.3 |
| 20-Oct-2018 |
pgoyette | Sync with head
|
| 1.2.12.2 |
| 28-Jul-2018 |
pgoyette | Sync with HEAD
|
| 1.2.12.1 |
| 07-Apr-2018 |
pgoyette | Sync with HEAD. 77 conflicts resolved - all of them $NetBSD$
|
| 1.3.2.2 |
| 13-Apr-2020 |
martin | Mostly merge changes from HEAD upto 20200411
|
| 1.3.2.1 |
| 10-Jun-2019 |
christos | Sync with HEAD
|
| 1.10.2.1 |
| 29-Feb-2020 |
ad | Sync with head.
|
