pte.h revision 1.3
1 /* $NetBSD: pte.h,v 1.3 2018/04/01 04:35:03 ryo Exp $ */ 2 3 /*- 4 * Copyright (c) 2014 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Matt Thomas of 3am Software Foundry. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _AARCH64_PTE_H_ 33 #define _AARCH64_PTE_H_ 34 35 #ifdef __aarch64__ 36 37 #ifndef _LOCORE 38 typedef uint64_t pd_entry_t; /* L0(512G) / L1(1G) / L2(2M) table entry */ 39 typedef uint64_t pt_entry_t; /* L3(4k) table entry */ 40 #endif /* _LOCORE */ 41 42 /* 43 * translation table, block, and page descriptors 44 */ 45 #define LX_TBL_NSTABLE __BIT(63) /* inherited next level */ 46 #define LX_TBL_APTABLE __BITS(62,61) /* inherited next level */ 47 #define LX_TBL_APTABLE_NOEFFECT __SHIFTIN(0,LX_TBL_APTABLE) 48 #define LX_TBL_APTABLE_EL0_NOACCESS __SHIFTIN(1,LX_TBL_APTABLE) 49 #define LX_TBL_APTABLE_RO __SHIFTIN(2,LX_TBL_APTABLE) 50 #define LX_TBL_APTABLE_RO_EL0_NOREAD __SHIFTIN(3,LX_TBL_APTABLE) 51 #define LX_TBL_UXNTABLE __BIT(60) /* inherited next level */ 52 #define LX_TBL_PXNTABLE __BIT(59) /* inherited next level */ 53 #define LX_BLKPAG_OS __BITS(58, 55) 54 # define LX_BLKPAG_OS_0 __SHIFTIN(1,LX_BLKPAG_OS) 55 # define LX_BLKPAG_OS_1 __SHIFTIN(2,LX_BLKPAG_OS) 56 # define LX_BLKPAG_OS_2 __SHIFTIN(4,LX_BLKPAG_OS) 57 # define LX_BLKPAG_OS_3 __SHIFTIN(8,LX_BLKPAG_OS) 58 #define LX_BLKPAG_UXN __BIT(54) /* Unprivileged Execute Never */ 59 #define LX_BLKPAG_PXN __BIT(53) /* Privileged Execute Never */ 60 #define LX_BLKPAG_CONTIG __BIT(52) /* Hint of TLB cache */ 61 #define LX_TBL_PA __BITS(47, 12) 62 #define LX_BLKPAG_OA __BITS(47, 12) 63 #define LX_BLKPAG_NG __BIT(11) /* Not Global */ 64 #define LX_BLKPAG_AF __BIT(10) /* Access Flag */ 65 #define LX_BLKPAG_SH __BITS(9,8) /* Shareability */ 66 #define LX_BLKPAG_SH_NS __SHIFTIN(0,LX_BLKPAG_SH) /* Non Shareable */ 67 #define LX_BLKPAG_SH_OS __SHIFTIN(2,LX_BLKPAG_SH) /* Outer Shareable */ 68 #define LX_BLKPAG_SH_IS __SHIFTIN(3,LX_BLKPAG_SH) /* Inner Shareable */ 69 #define LX_BLKPAG_AP __BIT(7) 70 #define LX_BLKPAG_AP_RW __SHIFTIN(0,LX_BLKPAG_AP) /* RW */ 71 #define LX_BLKPAG_AP_RO __SHIFTIN(1,LX_BLKPAG_AP) /* RO */ 72 #define LX_BLKPAG_APUSER __BIT(6) 73 #define LX_BLKPAG_NS __BIT(5) 74 #define LX_BLKPAG_ATTR_INDX __BITS(4,2) /* refer MAIR_EL1 attr<n> */ 75 #define LX_TYPE __BIT(1) 76 #define LX_TYPE_BLK __SHIFTIN(0, LX_TYPE) 77 #define LX_TYPE_TBL __SHIFTIN(1, LX_TYPE) 78 #define L3_TYPE_PAG __SHIFTIN(1, LX_TYPE) 79 #define LX_VALID __BIT(0) 80 81 #define L1_BLK_OA __BITS(47, 30) /* 1GB */ 82 #define L2_BLK_OA __BITS(47, 21) /* 2MB */ 83 #define L3_PAG_OA __BITS(47, 12) /* 4KB */ 84 85 86 /* L0 table, 512GB/entry * 512 */ 87 #define L0_SHIFT 39 88 #define L0_ADDR_BITS __BITS(47,39) 89 #define L0_SIZE (1UL << L0_SHIFT) 90 #define L0_OFFSET (L0_SIZE - 1UL) 91 #define L0_FRAME (~L0_OFFSET) 92 /* L0_BLOCK Level 0 doesn't support block translation */ 93 #define L0_TABLE (LX_TYPE_TBL | LX_VALID) 94 95 /* L1 table, 1GB/entry * 512 */ 96 #define L1_SHIFT 30 97 #define L1_ADDR_BITS __BITS(38,30) 98 #define L1_SIZE (1UL << L1_SHIFT) 99 #define L1_OFFSET (L1_SIZE - 1UL) 100 #define L1_FRAME (~L1_OFFSET) 101 #define L1_BLOCK (LX_BLKPAG_NG | LX_TYPE_BLK | LX_VALID) 102 #define L1_TABLE (LX_TYPE_TBL | LX_VALID) 103 104 /* L2 table, 2MB/entry * 512 */ 105 #define L2_SHIFT 21 106 #define L2_ADDR_BITS __BITS(29,21) 107 #define L2_SIZE (1UL << L2_SHIFT) 108 #define L2_OFFSET (L2_SIZE - 1UL) 109 #define L2_FRAME (~L2_OFFSET) 110 #define L2_BLOCK (LX_BLKPAG_NG | LX_TYPE_BLK | LX_VALID) 111 #define L2_TABLE (LX_TYPE_TBL | LX_VALID) 112 #define L2_BLOCK_MASK __BITS(47,21) 113 114 /* L3 table, 4KB/entry * 512 */ 115 #define L3_SHIFT 12 116 #define L3_ADDR_BITS __BITS(20,12) 117 #define L3_SIZE (1UL << L3_SHIFT) 118 #define L3_OFFSET (L3_SIZE - 1UL) 119 #define L3_FRAME (~L3_OFFSET) 120 #define L3_PAGE (LX_BLKPAG_NG | L3_TYPE_PAG | LX_VALID) 121 122 #define Ln_ENTRIES_SHIFT 9 123 #define Ln_ENTRIES (1 << Ln_ENTRIES_SHIFT) 124 #define Ln_TABLE_SIZE (8 << Ln_ENTRIES_SHIFT) 125 126 127 /* TCR_EL1 - Translation Control Register */ 128 #define TCR_TBI1 __BIT(38) /* ignore Top Byte TTBR1_EL1 */ 129 #define TCR_TBI0 __BIT(37) /* ignore Top Byte TTBR0_EL1 */ 130 #define TCR_AS64K __BIT(36) /* Use 64K ASIDs */ 131 #define TCR_IPS __BITS(34,32) /* Intermediate PhysAdr Size */ 132 #define TCR_IPS_256TB __SHIFTIN(5,TCR_IPS) /* 48 bits (256 TB) */ 133 #define TCR_IPS_64TB __SHIFTIN(4,TCR_IPS) /* 44 bits (16 TB) */ 134 #define TCR_IPS_4TB __SHIFTIN(3,TCR_IPS) /* 42 bits ( 4 TB) */ 135 #define TCR_IPS_1TB __SHIFTIN(2,TCR_IPS) /* 40 bits ( 1 TB) */ 136 #define TCR_IPS_64GB __SHIFTIN(1,TCR_IPS) /* 36 bits (64 GB) */ 137 #define TCR_IPS_4GB __SHIFTIN(0,TCR_IPS) /* 32 bits (4 GB) */ 138 #define TCR_TG1 __BITS(31,30) /* TTBR1 Page Granule Size */ 139 #define TCR_TG1_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */ 140 #define TCR_TG1_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */ 141 #define TCR_TG1_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */ 142 #define TCR_SH1 __BITS(29,28) 143 #define TCR_SH1_NONE __SHIFTIN(0,TCR_SH1) 144 #define TCR_SH1_OUTER __SHIFTIN(2,TCR_SH1) 145 #define TCR_SH1_INNER __SHIFTIN(3,TCR_SH1) 146 #define TCR_ORGN1 __BITS(27,26) /* TTBR1 Outer cacheability */ 147 #define TCR_ORGN1_NC __SHIFTIN(0,TCR_ORGN1) /* Non Cacheable */ 148 #define TCR_ORGN1_WB_WA __SHIFTIN(1,TCR_ORGN1) /* WriteBack WriteAllocate */ 149 #define TCR_ORGN1_WT __SHIFTIN(2,TCR_ORGN1) /* WriteThrough */ 150 #define TCR_ORGN1_WB __SHIFTIN(3,TCR_ORGN1) /* WriteBack */ 151 #define TCR_IRGN1 __BITS(25,24) /* TTBR1 Inner cacheability */ 152 #define TCR_IRGN1_NC __SHIFTIN(0,TCR_IRGN1) /* Non Cacheable */ 153 #define TCR_IRGN1_WB_WA __SHIFTIN(1,TCR_IRGN1) /* WriteBack WriteAllocate */ 154 #define TCR_IRGN1_WT __SHIFTIN(2,TCR_IRGN1) /* WriteThrough */ 155 #define TCR_IRGN1_WB __SHIFTIN(3,TCR_IRGN1) /* WriteBack */ 156 #define TCR_EPD1 __BIT(23) /* Walk Disable for TTBR1_EL1 */ 157 #define TCR_A1 __BIT(22) /* ASID is in TTBR1_EL1 */ 158 #define TCR_T1SZ __BITS(21,16) /* Size offset for TTBR1_EL1 */ 159 #define TCR_TG0 __BITS(15,14) /* TTBR0 Page Granule Size */ 160 #define TCR_TG0_16KB __SHIFTIN(1,TCR_TG1) /* 16KB page size */ 161 #define TCR_TG0_4KB __SHIFTIN(2,TCR_TG1) /* 4KB page size */ 162 #define TCR_TG0_64KB __SHIFTIN(3,TCR_TG1) /* 64KB page size */ 163 #define TCR_SH0 __BITS(13,12) 164 #define TCR_SH0_NONE __SHIFTIN(0,TCR_SH0) 165 #define TCR_SH0_OUTER __SHIFTIN(2,TCR_SH0) 166 #define TCR_SH0_INNER __SHIFTIN(3,TCR_SH0) 167 #define TCR_ORGN0 __BITS(11,10) /* TTBR0 Outer cacheability */ 168 #define TCR_ORGN0_NC __SHIFTIN(0,TCR_ORGN0) /* Non Cacheable */ 169 #define TCR_ORGN0_WB_WA __SHIFTIN(1,TCR_ORGN0) /* WriteBack WriteAllocate */ 170 #define TCR_ORGN0_WT __SHIFTIN(2,TCR_ORGN0) /* WriteThrough */ 171 #define TCR_ORGN0_WB __SHIFTIN(3,TCR_ORGN0) /* WriteBack */ 172 #define TCR_IRGN0 __BITS(9,8) /* TTBR0 Inner cacheability */ 173 #define TCR_IRGN0_NC __SHIFTIN(0,TCR_IRGN0) /* Non Cacheable */ 174 #define TCR_IRGN0_WB_WA __SHIFTIN(1,TCR_IRGN0) /* WriteBack WriteAllocate */ 175 #define TCR_IRGN0_WT __SHIFTIN(2,TCR_IRGN0) /* WriteThrough */ 176 #define TCR_IRGN0_WB __SHIFTIN(3,TCR_IRGN0) /* WriteBack */ 177 #define TCR_EPD0 __BIT(7) /* Walk Disable for TTBR0 */ 178 #define TCR_T0SZ __BITS(5,0) /* Size offset for TTBR0_EL1 */ 179 180 181 /* TTBR0_EL1, TTBR1_EL1 - Translation Table Base Register */ 182 #define TTBR_ASID __BITS(63,48) 183 #define TTBR_BADDR __BITS(47,0) 184 185 186 #elif defined(__arm__) 187 188 #include <arm/pte.h> 189 190 #endif /* __aarch64__/__arm__ */ 191 192 #endif /* _AARCH64_PTE_H_ */ 193
Indexes created Thu Oct 02 01:09:59 GMT 2025