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pci_1000.c revision 1.17.14.1
      1  1.17.14.1       mjf /* $NetBSD: pci_1000.c,v 1.17.14.1 2008/06/02 13:21:47 mjf Exp $ */
      2        1.1      ross 
      3        1.1      ross /*
      4        1.1      ross  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      5        1.1      ross  * All rights reserved.
      6        1.1      ross  *
      7        1.1      ross  * This code is based on pci_kn20aa.c, written by Chris G. Demetriou at
      8        1.1      ross  * Carnegie-Mellon University. Platform support for Mikasa and Mikasa/Pinnacle
      9        1.1      ross  * (Pinkasa) by Ross Harvey with copyright assignment by permission of Avalon
     10        1.1      ross  * Computer Systems, Inc.
     11        1.1      ross  *
     12        1.1      ross  * Redistribution and use in source and binary forms, with or without
     13        1.1      ross  * modification, are permitted provided that the following conditions
     14        1.1      ross  * are met:
     15        1.1      ross  * 1. Redistributions of source code must retain the above copyright
     16        1.1      ross  *    notice, this list of conditions and the following disclaimer.
     17        1.1      ross  * 2. Redistributions in binary form must reproduce the above copyright
     18        1.1      ross  *    notice, this list of conditions and the following disclaimer in the
     19        1.1      ross  *    documentation and/or other materials provided with the distribution.
     20        1.1      ross  *
     21        1.1      ross  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     22        1.1      ross  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     23        1.1      ross  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     24        1.1      ross  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     25        1.1      ross  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     26        1.1      ross  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     27        1.1      ross  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     28        1.1      ross  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     29        1.1      ross  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     30        1.1      ross  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     31        1.1      ross  * POSSIBILITY OF SUCH DAMAGE.
     32        1.1      ross  */
     33        1.1      ross 
     34        1.1      ross /*
     35        1.1      ross  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
     36        1.1      ross  * All rights reserved.
     37        1.1      ross  *
     38        1.1      ross  * Author: Chris G. Demetriou
     39        1.1      ross  *
     40        1.1      ross  * Permission to use, copy, modify and distribute this software and
     41        1.1      ross  * its documentation is hereby granted, provided that both the copyright
     42        1.1      ross  * notice and this permission notice appear in all copies of the
     43        1.1      ross  * software, derivative works or modified versions, and any portions
     44        1.1      ross  * thereof, and that both notices appear in supporting documentation.
     45        1.1      ross  *
     46        1.1      ross  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     47        1.1      ross  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     48        1.1      ross  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     49        1.1      ross  *
     50        1.1      ross  * Carnegie Mellon requests users of this software to return to
     51        1.1      ross  *
     52        1.1      ross  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     53        1.1      ross  *  School of Computer Science
     54        1.1      ross  *  Carnegie Mellon University
     55        1.1      ross  *  Pittsburgh PA 15213-3890
     56        1.1      ross  *
     57        1.1      ross  * any improvements or extensions that they make and grant Carnegie the
     58        1.1      ross  * rights to redistribute these changes.
     59        1.1      ross  */
     60        1.1      ross 
     61        1.1      ross #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
     62        1.1      ross 
     63  1.17.14.1       mjf __KERNEL_RCSID(0, "$NetBSD: pci_1000.c,v 1.17.14.1 2008/06/02 13:21:47 mjf Exp $");
     64        1.1      ross 
     65        1.1      ross #include <sys/types.h>
     66        1.1      ross #include <sys/param.h>
     67        1.1      ross #include <sys/time.h>
     68        1.1      ross #include <sys/systm.h>
     69        1.1      ross #include <sys/errno.h>
     70        1.1      ross #include <sys/malloc.h>
     71        1.1      ross #include <sys/device.h>
     72        1.1      ross #include <sys/syslog.h>
     73        1.1      ross 
     74       1.10       mrg #include <uvm/uvm_extern.h>
     75        1.1      ross 
     76        1.1      ross #include <machine/autoconf.h>
     77        1.1      ross 
     78        1.1      ross #include <dev/pci/pcireg.h>
     79        1.1      ross #include <dev/pci/pcivar.h>
     80        1.1      ross 
     81        1.1      ross #include <alpha/pci/pci_1000.h>
     82        1.1      ross 
     83        1.1      ross #include "sio.h"
     84        1.7   thorpej #if NSIO > 0 || NPCEB > 0
     85        1.1      ross #include <alpha/pci/siovar.h>
     86        1.1      ross #endif
     87        1.1      ross 
     88        1.1      ross static bus_space_tag_t another_mystery_icu_iot;
     89        1.1      ross static bus_space_handle_t another_mystery_icu_ioh;
     90        1.1      ross 
     91       1.11  sommerfe int	dec_1000_intr_map __P((struct pci_attach_args *, pci_intr_handle_t *));
     92        1.1      ross const char *dec_1000_intr_string __P((void *, pci_intr_handle_t));
     93        1.8       cgd const struct evcnt *dec_1000_intr_evcnt __P((void *, pci_intr_handle_t));
     94        1.1      ross void	*dec_1000_intr_establish __P((void *, pci_intr_handle_t,
     95        1.1      ross 	    int, int (*func)(void *), void *));
     96        1.1      ross void	dec_1000_intr_disestablish __P((void *, void *));
     97        1.1      ross 
     98        1.9   thorpej #define	PCI_NIRQ	16
     99        1.9   thorpej #define	PCI_STRAY_MAX	5
    100        1.1      ross 
    101        1.1      ross struct alpha_shared_intr *dec_1000_pci_intr;
    102        1.1      ross 
    103       1.12   thorpej static void dec_1000_iointr __P((void *arg, unsigned long vec));
    104        1.1      ross static void dec_1000_enable_intr __P((int irq));
    105        1.1      ross static void dec_1000_disable_intr __P((int irq));
    106        1.1      ross static void pci_1000_imi __P((void));
    107        1.1      ross static pci_chipset_tag_t pc_tag;
    108        1.1      ross 
    109        1.1      ross void
    110        1.1      ross pci_1000_pickintr(core, iot, memt, pc)
    111        1.1      ross 	void *core;
    112        1.1      ross 	bus_space_tag_t iot, memt;
    113        1.1      ross 	pci_chipset_tag_t pc;
    114        1.1      ross {
    115        1.9   thorpej 	char *cp;
    116        1.1      ross 	int i;
    117        1.1      ross 
    118        1.1      ross 	another_mystery_icu_iot = iot;
    119        1.1      ross 
    120        1.1      ross 	pc_tag = pc;
    121        1.1      ross 	if (bus_space_map(iot, 0x536, 2, 0, &another_mystery_icu_ioh))
    122        1.1      ross 		panic("pci_1000_pickintr");
    123        1.1      ross         pc->pc_intr_v = core;
    124        1.1      ross         pc->pc_intr_map = dec_1000_intr_map;
    125        1.1      ross         pc->pc_intr_string = dec_1000_intr_string;
    126        1.8       cgd 	pc->pc_intr_evcnt = dec_1000_intr_evcnt;
    127        1.1      ross         pc->pc_intr_establish = dec_1000_intr_establish;
    128        1.1      ross         pc->pc_intr_disestablish = dec_1000_intr_disestablish;
    129        1.1      ross 
    130        1.1      ross 	pc->pc_pciide_compat_intr_establish = NULL;
    131        1.1      ross 
    132        1.9   thorpej 	dec_1000_pci_intr =
    133        1.9   thorpej 	    alpha_shared_intr_alloc(PCI_NIRQ, 8);
    134        1.9   thorpej 	for (i = 0; i < PCI_NIRQ; i++) {
    135        1.1      ross 		alpha_shared_intr_set_maxstrays(dec_1000_pci_intr, i,
    136        1.1      ross 		    PCI_STRAY_MAX);
    137        1.9   thorpej 
    138        1.9   thorpej 		cp = alpha_shared_intr_string(dec_1000_pci_intr, i);
    139        1.9   thorpej 		sprintf(cp, "irq %d", i);
    140        1.9   thorpej 		evcnt_attach_dynamic(alpha_shared_intr_evcnt(
    141        1.9   thorpej 		    dec_1000_pci_intr, i), EVCNT_TYPE_INTR, NULL,
    142        1.9   thorpej 		    "dec_1000", cp);
    143        1.9   thorpej 	}
    144        1.1      ross 
    145        1.1      ross 	pci_1000_imi();
    146        1.7   thorpej #if NSIO > 0 || NPCEB > 0
    147        1.1      ross 	sio_intr_setup(pc, iot);
    148        1.1      ross #endif
    149        1.1      ross }
    150        1.1      ross 
    151        1.1      ross int
    152       1.11  sommerfe dec_1000_intr_map(pa, ihp)
    153       1.11  sommerfe 	struct pci_attach_args *pa;
    154        1.1      ross         pci_intr_handle_t *ihp;
    155        1.1      ross {
    156       1.11  sommerfe 	pcitag_t bustag = pa->pa_intrtag;
    157       1.11  sommerfe 	int buspin = pa->pa_intrpin;
    158       1.11  sommerfe 	pci_chipset_tag_t pc = pa->pa_pc;
    159        1.1      ross 	int	device;
    160        1.1      ross 
    161        1.1      ross 	if (buspin == 0)	/* No IRQ used. */
    162        1.1      ross 		return 1;
    163        1.1      ross 	if (!(1 <= buspin && buspin <= 4))
    164        1.1      ross 		goto bad;
    165        1.1      ross 
    166       1.13   thorpej 	pci_decompose_tag(pc, bustag, NULL, &device, NULL);
    167        1.1      ross 
    168        1.1      ross 	switch(device) {
    169        1.1      ross 	case 6:
    170        1.1      ross 		if(buspin != 1)
    171        1.1      ross 			break;
    172        1.1      ross 		*ihp = 0xc;		/* integrated ncr scsi */
    173        1.1      ross 		return 0;
    174        1.1      ross 	case 11:
    175        1.1      ross 	case 12:
    176        1.1      ross 	case 13:
    177        1.1      ross 		*ihp = (device - 11) * 4 + buspin - 1;
    178        1.1      ross 		return 0;
    179        1.1      ross 	}
    180        1.1      ross 
    181        1.1      ross bad:	printf("dec_1000_intr_map: can't map dev %d pin %d\n", device, buspin);
    182        1.1      ross 	return 1;
    183        1.1      ross }
    184        1.1      ross 
    185        1.1      ross const char *
    186        1.1      ross dec_1000_intr_string(ccv, ih)
    187        1.1      ross 	void *ccv;
    188        1.1      ross 	pci_intr_handle_t ih;
    189        1.1      ross {
    190        1.1      ross 	static const char irqmsg_fmt[] = "dec_1000 irq %ld";
    191        1.1      ross         static char irqstr[sizeof irqmsg_fmt];
    192        1.1      ross 
    193        1.9   thorpej         if (ih >= PCI_NIRQ)
    194       1.14    provos                 panic("dec_1000_intr_string: bogus dec_1000 IRQ 0x%lx", ih);
    195        1.1      ross 
    196        1.6      ross         snprintf(irqstr, sizeof irqstr, irqmsg_fmt, ih);
    197        1.1      ross         return (irqstr);
    198        1.8       cgd }
    199        1.8       cgd 
    200        1.8       cgd const struct evcnt *
    201        1.8       cgd dec_1000_intr_evcnt(ccv, ih)
    202        1.8       cgd 	void *ccv;
    203        1.8       cgd 	pci_intr_handle_t ih;
    204        1.8       cgd {
    205        1.8       cgd 
    206        1.9   thorpej 	if (ih >= PCI_NIRQ)
    207       1.14    provos 		panic("dec_1000_intr_evcnt: bogus dec_1000 IRQ 0x%lx", ih);
    208        1.9   thorpej 
    209        1.9   thorpej 	return (alpha_shared_intr_evcnt(dec_1000_pci_intr, ih));
    210        1.1      ross }
    211        1.1      ross 
    212        1.1      ross void *
    213        1.1      ross dec_1000_intr_establish(ccv, ih, level, func, arg)
    214        1.1      ross         void *ccv, *arg;
    215        1.1      ross         pci_intr_handle_t ih;
    216        1.1      ross         int level;
    217        1.1      ross         int (*func) __P((void *));
    218        1.1      ross {
    219        1.1      ross 	void *cookie;
    220        1.1      ross 
    221        1.9   thorpej         if (ih >= PCI_NIRQ)
    222       1.14    provos                 panic("dec_1000_intr_establish: IRQ too high, 0x%lx", ih);
    223        1.1      ross 
    224        1.1      ross 	cookie = alpha_shared_intr_establish(dec_1000_pci_intr, ih, IST_LEVEL,
    225        1.1      ross 	    level, func, arg, "dec_1000 irq");
    226        1.1      ross 
    227        1.1      ross 	if (cookie != NULL &&
    228       1.12   thorpej 	    alpha_shared_intr_firstactive(dec_1000_pci_intr, ih)) {
    229       1.17        ad 		scb_set(0x900 + SCB_IDXTOVEC(ih), dec_1000_iointr, NULL,
    230       1.17        ad 		    level);
    231        1.1      ross 		dec_1000_enable_intr(ih);
    232       1.12   thorpej 	}
    233        1.1      ross 	return (cookie);
    234        1.1      ross }
    235        1.1      ross 
    236        1.1      ross void
    237        1.1      ross dec_1000_intr_disestablish(ccv, cookie)
    238        1.1      ross         void *ccv, *cookie;
    239        1.1      ross {
    240        1.4   thorpej 	struct alpha_shared_intrhand *ih = cookie;
    241        1.4   thorpej 	unsigned int irq = ih->ih_num;
    242        1.4   thorpej 	int s;
    243        1.4   thorpej 
    244        1.4   thorpej 	s = splhigh();
    245        1.4   thorpej 
    246        1.4   thorpej 	alpha_shared_intr_disestablish(dec_1000_pci_intr, cookie,
    247        1.4   thorpej 	    "dec_1000 irq");
    248        1.4   thorpej 	if (alpha_shared_intr_isactive(dec_1000_pci_intr, irq) == 0) {
    249        1.4   thorpej 		dec_1000_disable_intr(irq);
    250        1.4   thorpej 		alpha_shared_intr_set_dfltsharetype(dec_1000_pci_intr, irq,
    251        1.4   thorpej 		    IST_NONE);
    252       1.12   thorpej 		scb_free(0x900 + SCB_IDXTOVEC(irq));
    253        1.4   thorpej 	}
    254        1.4   thorpej 
    255        1.4   thorpej 	splx(s);
    256        1.1      ross }
    257        1.1      ross 
    258        1.1      ross static void
    259       1.12   thorpej dec_1000_iointr(arg, vec)
    260       1.12   thorpej 	void *arg;
    261        1.1      ross 	unsigned long vec;
    262        1.1      ross {
    263        1.1      ross 	int irq;
    264        1.1      ross 
    265       1.12   thorpej 	irq = SCB_VECTOIDX(vec - 0x900);
    266       1.12   thorpej 
    267       1.12   thorpej 	if (!alpha_shared_intr_dispatch(dec_1000_pci_intr, irq)) {
    268       1.12   thorpej 		alpha_shared_intr_stray(dec_1000_pci_intr, irq,
    269       1.12   thorpej 		    "dec_1000 irq");
    270       1.12   thorpej 		if (ALPHA_SHARED_INTR_DISABLE(dec_1000_pci_intr, irq))
    271       1.12   thorpej 			dec_1000_disable_intr(irq);
    272       1.15   thorpej 	} else
    273       1.15   thorpej 		alpha_shared_intr_reset_strays(dec_1000_pci_intr, irq);
    274        1.1      ross }
    275        1.1      ross 
    276        1.1      ross /*
    277        1.1      ross  * Read and write the mystery ICU IMR registers
    278        1.1      ross  */
    279        1.1      ross 
    280        1.1      ross #define	IR() bus_space_read_2(another_mystery_icu_iot,		\
    281        1.1      ross 				another_mystery_icu_ioh, 0)
    282        1.1      ross 
    283        1.1      ross #define	IW(v) bus_space_write_2(another_mystery_icu_iot,	\
    284        1.1      ross 				another_mystery_icu_ioh, 0, (v))
    285        1.1      ross 
    286        1.1      ross /*
    287        1.1      ross  * Enable and disable interrupts at the ICU level
    288        1.1      ross  */
    289        1.1      ross 
    290        1.1      ross static void
    291        1.1      ross dec_1000_enable_intr(irq)
    292        1.1      ross 	int irq;
    293        1.1      ross {
    294        1.1      ross 	IW(IR() | 1 << irq);
    295        1.1      ross }
    296        1.1      ross 
    297        1.1      ross static void
    298        1.1      ross dec_1000_disable_intr(irq)
    299        1.1      ross 	int irq;
    300        1.1      ross {
    301        1.1      ross 	IW(IR() & ~(1 << irq));
    302        1.1      ross }
    303        1.1      ross /*
    304        1.1      ross  * Initialize mystery ICU
    305        1.1      ross  */
    306        1.1      ross static void
    307        1.1      ross pci_1000_imi()
    308        1.1      ross {
    309        1.1      ross 	IW(0);					/* XXX ?? */
    310        1.1      ross }
    311