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pci_1000.c revision 1.24
      1  1.24      matt /* $NetBSD: pci_1000.c,v 1.24 2012/02/06 02:14:14 matt Exp $ */
      2   1.1      ross 
      3   1.1      ross /*
      4   1.1      ross  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      5   1.1      ross  * All rights reserved.
      6   1.1      ross  *
      7   1.1      ross  * This code is based on pci_kn20aa.c, written by Chris G. Demetriou at
      8   1.1      ross  * Carnegie-Mellon University. Platform support for Mikasa and Mikasa/Pinnacle
      9   1.1      ross  * (Pinkasa) by Ross Harvey with copyright assignment by permission of Avalon
     10   1.1      ross  * Computer Systems, Inc.
     11   1.1      ross  *
     12   1.1      ross  * Redistribution and use in source and binary forms, with or without
     13   1.1      ross  * modification, are permitted provided that the following conditions
     14   1.1      ross  * are met:
     15   1.1      ross  * 1. Redistributions of source code must retain the above copyright
     16   1.1      ross  *    notice, this list of conditions and the following disclaimer.
     17   1.1      ross  * 2. Redistributions in binary form must reproduce the above copyright
     18   1.1      ross  *    notice, this list of conditions and the following disclaimer in the
     19   1.1      ross  *    documentation and/or other materials provided with the distribution.
     20   1.1      ross  *
     21   1.1      ross  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     22   1.1      ross  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     23   1.1      ross  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     24   1.1      ross  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     25   1.1      ross  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     26   1.1      ross  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     27   1.1      ross  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     28   1.1      ross  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     29   1.1      ross  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     30   1.1      ross  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     31   1.1      ross  * POSSIBILITY OF SUCH DAMAGE.
     32   1.1      ross  */
     33   1.1      ross 
     34   1.1      ross /*
     35   1.1      ross  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
     36   1.1      ross  * All rights reserved.
     37   1.1      ross  *
     38   1.1      ross  * Author: Chris G. Demetriou
     39  1.24      matt  *
     40   1.1      ross  * Permission to use, copy, modify and distribute this software and
     41   1.1      ross  * its documentation is hereby granted, provided that both the copyright
     42   1.1      ross  * notice and this permission notice appear in all copies of the
     43   1.1      ross  * software, derivative works or modified versions, and any portions
     44   1.1      ross  * thereof, and that both notices appear in supporting documentation.
     45  1.24      matt  *
     46  1.24      matt  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     47  1.24      matt  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     48   1.1      ross  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     49  1.24      matt  *
     50   1.1      ross  * Carnegie Mellon requests users of this software to return to
     51   1.1      ross  *
     52   1.1      ross  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     53   1.1      ross  *  School of Computer Science
     54   1.1      ross  *  Carnegie Mellon University
     55   1.1      ross  *  Pittsburgh PA 15213-3890
     56   1.1      ross  *
     57   1.1      ross  * any improvements or extensions that they make and grant Carnegie the
     58   1.1      ross  * rights to redistribute these changes.
     59   1.1      ross  */
     60   1.1      ross 
     61   1.1      ross #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
     62   1.1      ross 
     63  1.24      matt __KERNEL_RCSID(0, "$NetBSD: pci_1000.c,v 1.24 2012/02/06 02:14:14 matt Exp $");
     64   1.1      ross 
     65   1.1      ross #include <sys/types.h>
     66   1.1      ross #include <sys/param.h>
     67   1.1      ross #include <sys/time.h>
     68   1.1      ross #include <sys/systm.h>
     69   1.1      ross #include <sys/errno.h>
     70   1.1      ross #include <sys/malloc.h>
     71   1.1      ross #include <sys/device.h>
     72   1.1      ross #include <sys/syslog.h>
     73   1.1      ross 
     74   1.1      ross #include <machine/autoconf.h>
     75   1.1      ross 
     76   1.1      ross #include <dev/pci/pcireg.h>
     77   1.1      ross #include <dev/pci/pcivar.h>
     78   1.1      ross 
     79   1.1      ross #include <alpha/pci/pci_1000.h>
     80   1.1      ross 
     81   1.1      ross #include "sio.h"
     82   1.7   thorpej #if NSIO > 0 || NPCEB > 0
     83   1.1      ross #include <alpha/pci/siovar.h>
     84   1.1      ross #endif
     85   1.1      ross 
     86   1.1      ross static bus_space_tag_t another_mystery_icu_iot;
     87   1.1      ross static bus_space_handle_t another_mystery_icu_ioh;
     88   1.1      ross 
     89  1.23    dyoung int	dec_1000_intr_map(const struct pci_attach_args *, pci_intr_handle_t *);
     90  1.19       dsl const char *dec_1000_intr_string(void *, pci_intr_handle_t);
     91  1.19       dsl const struct evcnt *dec_1000_intr_evcnt(void *, pci_intr_handle_t);
     92  1.19       dsl void	*dec_1000_intr_establish(void *, pci_intr_handle_t,
     93  1.19       dsl 	    int, int (*func)(void *), void *);
     94  1.19       dsl void	dec_1000_intr_disestablish(void *, void *);
     95   1.1      ross 
     96   1.9   thorpej #define	PCI_NIRQ	16
     97   1.9   thorpej #define	PCI_STRAY_MAX	5
     98   1.1      ross 
     99   1.1      ross struct alpha_shared_intr *dec_1000_pci_intr;
    100   1.1      ross 
    101  1.19       dsl static void dec_1000_iointr(void *arg, unsigned long vec);
    102  1.19       dsl static void dec_1000_enable_intr(int irq);
    103  1.19       dsl static void dec_1000_disable_intr(int irq);
    104  1.19       dsl static void pci_1000_imi(void);
    105   1.1      ross static pci_chipset_tag_t pc_tag;
    106   1.1      ross 
    107   1.1      ross void
    108  1.21       dsl pci_1000_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt, pci_chipset_tag_t pc)
    109   1.1      ross {
    110   1.9   thorpej 	char *cp;
    111   1.1      ross 	int i;
    112   1.1      ross 
    113   1.1      ross 	another_mystery_icu_iot = iot;
    114   1.1      ross 
    115   1.1      ross 	pc_tag = pc;
    116   1.1      ross 	if (bus_space_map(iot, 0x536, 2, 0, &another_mystery_icu_ioh))
    117   1.1      ross 		panic("pci_1000_pickintr");
    118  1.24      matt 	pc->pc_intr_v = core;
    119  1.24      matt 	pc->pc_intr_map = dec_1000_intr_map;
    120  1.24      matt 	pc->pc_intr_string = dec_1000_intr_string;
    121   1.8       cgd 	pc->pc_intr_evcnt = dec_1000_intr_evcnt;
    122  1.24      matt 	pc->pc_intr_establish = dec_1000_intr_establish;
    123  1.24      matt 	pc->pc_intr_disestablish = dec_1000_intr_disestablish;
    124   1.1      ross 
    125   1.1      ross 	pc->pc_pciide_compat_intr_establish = NULL;
    126   1.1      ross 
    127   1.9   thorpej 	dec_1000_pci_intr =
    128   1.9   thorpej 	    alpha_shared_intr_alloc(PCI_NIRQ, 8);
    129   1.9   thorpej 	for (i = 0; i < PCI_NIRQ; i++) {
    130   1.1      ross 		alpha_shared_intr_set_maxstrays(dec_1000_pci_intr, i,
    131   1.1      ross 		    PCI_STRAY_MAX);
    132   1.9   thorpej 
    133   1.9   thorpej 		cp = alpha_shared_intr_string(dec_1000_pci_intr, i);
    134   1.9   thorpej 		sprintf(cp, "irq %d", i);
    135   1.9   thorpej 		evcnt_attach_dynamic(alpha_shared_intr_evcnt(
    136   1.9   thorpej 		    dec_1000_pci_intr, i), EVCNT_TYPE_INTR, NULL,
    137   1.9   thorpej 		    "dec_1000", cp);
    138   1.9   thorpej 	}
    139   1.1      ross 
    140   1.1      ross 	pci_1000_imi();
    141   1.7   thorpej #if NSIO > 0 || NPCEB > 0
    142   1.1      ross 	sio_intr_setup(pc, iot);
    143   1.1      ross #endif
    144   1.1      ross }
    145   1.1      ross 
    146  1.24      matt int
    147  1.23    dyoung dec_1000_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp)
    148   1.1      ross {
    149  1.11  sommerfe 	pcitag_t bustag = pa->pa_intrtag;
    150  1.11  sommerfe 	int buspin = pa->pa_intrpin;
    151  1.11  sommerfe 	pci_chipset_tag_t pc = pa->pa_pc;
    152   1.1      ross 	int	device;
    153   1.1      ross 
    154   1.1      ross 	if (buspin == 0)	/* No IRQ used. */
    155   1.1      ross 		return 1;
    156   1.1      ross 	if (!(1 <= buspin && buspin <= 4))
    157   1.1      ross 		goto bad;
    158   1.1      ross 
    159  1.13   thorpej 	pci_decompose_tag(pc, bustag, NULL, &device, NULL);
    160   1.1      ross 
    161   1.1      ross 	switch(device) {
    162   1.1      ross 	case 6:
    163   1.1      ross 		if(buspin != 1)
    164   1.1      ross 			break;
    165   1.1      ross 		*ihp = 0xc;		/* integrated ncr scsi */
    166   1.1      ross 		return 0;
    167   1.1      ross 	case 11:
    168   1.1      ross 	case 12:
    169   1.1      ross 	case 13:
    170   1.1      ross 		*ihp = (device - 11) * 4 + buspin - 1;
    171   1.1      ross 		return 0;
    172   1.1      ross 	}
    173   1.1      ross 
    174   1.1      ross bad:	printf("dec_1000_intr_map: can't map dev %d pin %d\n", device, buspin);
    175   1.1      ross 	return 1;
    176   1.1      ross }
    177   1.1      ross 
    178   1.1      ross const char *
    179  1.20       dsl dec_1000_intr_string(void *ccv, pci_intr_handle_t ih)
    180   1.1      ross {
    181   1.1      ross 	static const char irqmsg_fmt[] = "dec_1000 irq %ld";
    182  1.24      matt 	static char irqstr[sizeof irqmsg_fmt];
    183   1.1      ross 
    184  1.24      matt 	if (ih >= PCI_NIRQ)
    185  1.24      matt 	        panic("dec_1000_intr_string: bogus dec_1000 IRQ 0x%lx", ih);
    186   1.1      ross 
    187  1.24      matt 	snprintf(irqstr, sizeof irqstr, irqmsg_fmt, ih);
    188  1.24      matt 	return (irqstr);
    189   1.8       cgd }
    190   1.8       cgd 
    191   1.8       cgd const struct evcnt *
    192  1.20       dsl dec_1000_intr_evcnt(void *ccv, pci_intr_handle_t ih)
    193   1.8       cgd {
    194   1.8       cgd 
    195   1.9   thorpej 	if (ih >= PCI_NIRQ)
    196  1.14    provos 		panic("dec_1000_intr_evcnt: bogus dec_1000 IRQ 0x%lx", ih);
    197   1.9   thorpej 
    198   1.9   thorpej 	return (alpha_shared_intr_evcnt(dec_1000_pci_intr, ih));
    199   1.1      ross }
    200   1.1      ross 
    201   1.1      ross void *
    202  1.24      matt dec_1000_intr_establish(
    203  1.24      matt 	void *ccv,
    204  1.24      matt 	pci_intr_handle_t ih,
    205  1.24      matt 	int level,
    206  1.24      matt 	int (*func)(void *),
    207  1.24      matt 	void *arg)
    208  1.24      matt {
    209   1.1      ross 	void *cookie;
    210   1.1      ross 
    211  1.24      matt 	if (ih >= PCI_NIRQ)
    212  1.24      matt 	        panic("dec_1000_intr_establish: IRQ too high, 0x%lx", ih);
    213   1.1      ross 
    214   1.1      ross 	cookie = alpha_shared_intr_establish(dec_1000_pci_intr, ih, IST_LEVEL,
    215   1.1      ross 	    level, func, arg, "dec_1000 irq");
    216   1.1      ross 
    217   1.1      ross 	if (cookie != NULL &&
    218  1.12   thorpej 	    alpha_shared_intr_firstactive(dec_1000_pci_intr, ih)) {
    219  1.17        ad 		scb_set(0x900 + SCB_IDXTOVEC(ih), dec_1000_iointr, NULL,
    220  1.17        ad 		    level);
    221   1.1      ross 		dec_1000_enable_intr(ih);
    222  1.12   thorpej 	}
    223   1.1      ross 	return (cookie);
    224   1.1      ross }
    225   1.1      ross 
    226  1.24      matt void
    227  1.21       dsl dec_1000_intr_disestablish(void *ccv, void *cookie)
    228   1.1      ross {
    229   1.4   thorpej 	struct alpha_shared_intrhand *ih = cookie;
    230   1.4   thorpej 	unsigned int irq = ih->ih_num;
    231   1.4   thorpej 	int s;
    232   1.4   thorpej 
    233   1.4   thorpej 	s = splhigh();
    234   1.4   thorpej 
    235   1.4   thorpej 	alpha_shared_intr_disestablish(dec_1000_pci_intr, cookie,
    236   1.4   thorpej 	    "dec_1000 irq");
    237   1.4   thorpej 	if (alpha_shared_intr_isactive(dec_1000_pci_intr, irq) == 0) {
    238   1.4   thorpej 		dec_1000_disable_intr(irq);
    239   1.4   thorpej 		alpha_shared_intr_set_dfltsharetype(dec_1000_pci_intr, irq,
    240   1.4   thorpej 		    IST_NONE);
    241  1.12   thorpej 		scb_free(0x900 + SCB_IDXTOVEC(irq));
    242   1.4   thorpej 	}
    243   1.4   thorpej 
    244   1.4   thorpej 	splx(s);
    245   1.1      ross }
    246   1.1      ross 
    247   1.1      ross static void
    248  1.20       dsl dec_1000_iointr(void *arg, unsigned long vec)
    249   1.1      ross {
    250   1.1      ross 	int irq;
    251   1.1      ross 
    252  1.12   thorpej 	irq = SCB_VECTOIDX(vec - 0x900);
    253  1.12   thorpej 
    254  1.12   thorpej 	if (!alpha_shared_intr_dispatch(dec_1000_pci_intr, irq)) {
    255  1.12   thorpej 		alpha_shared_intr_stray(dec_1000_pci_intr, irq,
    256  1.12   thorpej 		    "dec_1000 irq");
    257  1.12   thorpej 		if (ALPHA_SHARED_INTR_DISABLE(dec_1000_pci_intr, irq))
    258  1.12   thorpej 			dec_1000_disable_intr(irq);
    259  1.15   thorpej 	} else
    260  1.15   thorpej 		alpha_shared_intr_reset_strays(dec_1000_pci_intr, irq);
    261   1.1      ross }
    262   1.1      ross 
    263   1.1      ross /*
    264   1.1      ross  * Read and write the mystery ICU IMR registers
    265   1.1      ross  */
    266   1.1      ross 
    267   1.1      ross #define	IR() bus_space_read_2(another_mystery_icu_iot,		\
    268   1.1      ross 				another_mystery_icu_ioh, 0)
    269   1.1      ross 
    270   1.1      ross #define	IW(v) bus_space_write_2(another_mystery_icu_iot,	\
    271   1.1      ross 				another_mystery_icu_ioh, 0, (v))
    272   1.1      ross 
    273   1.1      ross /*
    274   1.1      ross  * Enable and disable interrupts at the ICU level
    275   1.1      ross  */
    276   1.1      ross 
    277   1.1      ross static void
    278  1.20       dsl dec_1000_enable_intr(int irq)
    279   1.1      ross {
    280   1.1      ross 	IW(IR() | 1 << irq);
    281   1.1      ross }
    282   1.1      ross 
    283   1.1      ross static void
    284  1.20       dsl dec_1000_disable_intr(int irq)
    285   1.1      ross {
    286   1.1      ross 	IW(IR() & ~(1 << irq));
    287   1.1      ross }
    288   1.1      ross /*
    289   1.1      ross  * Initialize mystery ICU
    290   1.1      ross  */
    291   1.1      ross static void
    292  1.24      matt pci_1000_imi(void)
    293   1.1      ross {
    294   1.1      ross 	IW(0);					/* XXX ?? */
    295   1.1      ross }
    296