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pci_1000.c revision 1.9
      1  1.9  thorpej /* $NetBSD: pci_1000.c,v 1.9 2000/06/05 21:47:21 thorpej Exp $ */
      2  1.1     ross 
      3  1.1     ross /*
      4  1.1     ross  * Copyright (c) 1998 The NetBSD Foundation, Inc.
      5  1.1     ross  * All rights reserved.
      6  1.1     ross  *
      7  1.1     ross  * This code is based on pci_kn20aa.c, written by Chris G. Demetriou at
      8  1.1     ross  * Carnegie-Mellon University. Platform support for Mikasa and Mikasa/Pinnacle
      9  1.1     ross  * (Pinkasa) by Ross Harvey with copyright assignment by permission of Avalon
     10  1.1     ross  * Computer Systems, Inc.
     11  1.1     ross  *
     12  1.1     ross  * Redistribution and use in source and binary forms, with or without
     13  1.1     ross  * modification, are permitted provided that the following conditions
     14  1.1     ross  * are met:
     15  1.1     ross  * 1. Redistributions of source code must retain the above copyright
     16  1.1     ross  *    notice, this list of conditions and the following disclaimer.
     17  1.1     ross  * 2. Redistributions in binary form must reproduce the above copyright
     18  1.1     ross  *    notice, this list of conditions and the following disclaimer in the
     19  1.1     ross  *    documentation and/or other materials provided with the distribution.
     20  1.1     ross  * 3. All advertising materials mentioning features or use of this software
     21  1.1     ross  *    must display the following acknowledgement:
     22  1.1     ross  *	This product includes software developed by the NetBSD
     23  1.1     ross  *	Foundation, Inc. and its contributors.
     24  1.1     ross  * 4. Neither the name of The NetBSD Foundation nor the names of its
     25  1.1     ross  *    contributors may be used to endorse or promote products derived
     26  1.1     ross  *    from this software without specific prior written permission.
     27  1.1     ross  *
     28  1.1     ross  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     29  1.1     ross  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     30  1.1     ross  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     31  1.1     ross  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     32  1.1     ross  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     33  1.1     ross  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     34  1.1     ross  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     35  1.1     ross  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     36  1.1     ross  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     37  1.1     ross  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     38  1.1     ross  * POSSIBILITY OF SUCH DAMAGE.
     39  1.1     ross  */
     40  1.1     ross 
     41  1.1     ross /*
     42  1.1     ross  * Copyright (c) 1995, 1996 Carnegie-Mellon University.
     43  1.1     ross  * All rights reserved.
     44  1.1     ross  *
     45  1.1     ross  * Author: Chris G. Demetriou
     46  1.1     ross  *
     47  1.1     ross  * Permission to use, copy, modify and distribute this software and
     48  1.1     ross  * its documentation is hereby granted, provided that both the copyright
     49  1.1     ross  * notice and this permission notice appear in all copies of the
     50  1.1     ross  * software, derivative works or modified versions, and any portions
     51  1.1     ross  * thereof, and that both notices appear in supporting documentation.
     52  1.1     ross  *
     53  1.1     ross  * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
     54  1.1     ross  * CONDITION.  CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
     55  1.1     ross  * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
     56  1.1     ross  *
     57  1.1     ross  * Carnegie Mellon requests users of this software to return to
     58  1.1     ross  *
     59  1.1     ross  *  Software Distribution Coordinator  or  Software.Distribution (at) CS.CMU.EDU
     60  1.1     ross  *  School of Computer Science
     61  1.1     ross  *  Carnegie Mellon University
     62  1.1     ross  *  Pittsburgh PA 15213-3890
     63  1.1     ross  *
     64  1.1     ross  * any improvements or extensions that they make and grant Carnegie the
     65  1.1     ross  * rights to redistribute these changes.
     66  1.1     ross  */
     67  1.1     ross 
     68  1.1     ross #include <sys/cdefs.h>			/* RCS ID & Copyright macro defns */
     69  1.1     ross 
     70  1.9  thorpej __KERNEL_RCSID(0, "$NetBSD: pci_1000.c,v 1.9 2000/06/05 21:47:21 thorpej Exp $");
     71  1.1     ross 
     72  1.1     ross #include <sys/types.h>
     73  1.1     ross #include <sys/param.h>
     74  1.1     ross #include <sys/time.h>
     75  1.1     ross #include <sys/systm.h>
     76  1.1     ross #include <sys/errno.h>
     77  1.1     ross #include <sys/malloc.h>
     78  1.1     ross #include <sys/device.h>
     79  1.1     ross #include <sys/syslog.h>
     80  1.1     ross 
     81  1.1     ross #include <vm/vm.h>
     82  1.1     ross 
     83  1.1     ross #include <machine/autoconf.h>
     84  1.1     ross 
     85  1.1     ross #include <dev/pci/pcireg.h>
     86  1.1     ross #include <dev/pci/pcivar.h>
     87  1.1     ross 
     88  1.1     ross #include <alpha/pci/pci_1000.h>
     89  1.1     ross 
     90  1.1     ross #include "sio.h"
     91  1.7  thorpej #if NSIO > 0 || NPCEB > 0
     92  1.1     ross #include <alpha/pci/siovar.h>
     93  1.1     ross #endif
     94  1.1     ross 
     95  1.1     ross static bus_space_tag_t another_mystery_icu_iot;
     96  1.1     ross static bus_space_handle_t another_mystery_icu_ioh;
     97  1.1     ross 
     98  1.1     ross int	dec_1000_intr_map __P((void *, pcitag_t, int, int, pci_intr_handle_t *));
     99  1.1     ross const char *dec_1000_intr_string __P((void *, pci_intr_handle_t));
    100  1.8      cgd const struct evcnt *dec_1000_intr_evcnt __P((void *, pci_intr_handle_t));
    101  1.1     ross void	*dec_1000_intr_establish __P((void *, pci_intr_handle_t,
    102  1.1     ross 	    int, int (*func)(void *), void *));
    103  1.1     ross void	dec_1000_intr_disestablish __P((void *, void *));
    104  1.1     ross 
    105  1.9  thorpej #define	PCI_NIRQ	16
    106  1.9  thorpej #define	PCI_STRAY_MAX	5
    107  1.1     ross 
    108  1.1     ross struct alpha_shared_intr *dec_1000_pci_intr;
    109  1.1     ross 
    110  1.1     ross static void dec_1000_iointr __P((void *framep, unsigned long vec));
    111  1.1     ross static void dec_1000_enable_intr __P((int irq));
    112  1.1     ross static void dec_1000_disable_intr __P((int irq));
    113  1.1     ross static void pci_1000_imi __P((void));
    114  1.1     ross static pci_chipset_tag_t pc_tag;
    115  1.1     ross 
    116  1.1     ross void
    117  1.1     ross pci_1000_pickintr(core, iot, memt, pc)
    118  1.1     ross 	void *core;
    119  1.1     ross 	bus_space_tag_t iot, memt;
    120  1.1     ross 	pci_chipset_tag_t pc;
    121  1.1     ross {
    122  1.9  thorpej 	char *cp;
    123  1.1     ross 	int i;
    124  1.1     ross 
    125  1.1     ross 	another_mystery_icu_iot = iot;
    126  1.1     ross 
    127  1.1     ross 	pc_tag = pc;
    128  1.1     ross 	if (bus_space_map(iot, 0x536, 2, 0, &another_mystery_icu_ioh))
    129  1.1     ross 		panic("pci_1000_pickintr");
    130  1.1     ross         pc->pc_intr_v = core;
    131  1.1     ross         pc->pc_intr_map = dec_1000_intr_map;
    132  1.1     ross         pc->pc_intr_string = dec_1000_intr_string;
    133  1.8      cgd 	pc->pc_intr_evcnt = dec_1000_intr_evcnt;
    134  1.1     ross         pc->pc_intr_establish = dec_1000_intr_establish;
    135  1.1     ross         pc->pc_intr_disestablish = dec_1000_intr_disestablish;
    136  1.1     ross 
    137  1.1     ross 	pc->pc_pciide_compat_intr_establish = NULL;
    138  1.1     ross 
    139  1.9  thorpej 	dec_1000_pci_intr =
    140  1.9  thorpej 	    alpha_shared_intr_alloc(PCI_NIRQ, 8);
    141  1.9  thorpej 	for (i = 0; i < PCI_NIRQ; i++) {
    142  1.1     ross 		alpha_shared_intr_set_maxstrays(dec_1000_pci_intr, i,
    143  1.1     ross 		    PCI_STRAY_MAX);
    144  1.9  thorpej 
    145  1.9  thorpej 		cp = alpha_shared_intr_string(dec_1000_pci_intr, i);
    146  1.9  thorpej 		sprintf(cp, "irq %d", i);
    147  1.9  thorpej 		evcnt_attach_dynamic(alpha_shared_intr_evcnt(
    148  1.9  thorpej 		    dec_1000_pci_intr, i), EVCNT_TYPE_INTR, NULL,
    149  1.9  thorpej 		    "dec_1000", cp);
    150  1.9  thorpej 	}
    151  1.1     ross 
    152  1.1     ross 	pci_1000_imi();
    153  1.7  thorpej #if NSIO > 0 || NPCEB > 0
    154  1.1     ross 	sio_intr_setup(pc, iot);
    155  1.1     ross #endif
    156  1.1     ross 	set_iointr(dec_1000_iointr);
    157  1.1     ross }
    158  1.1     ross 
    159  1.1     ross int
    160  1.1     ross dec_1000_intr_map(ccv, bustag, buspin, line, ihp)
    161  1.1     ross         void *ccv;
    162  1.1     ross         pcitag_t bustag;
    163  1.1     ross         int buspin, line;
    164  1.1     ross         pci_intr_handle_t *ihp;
    165  1.1     ross {
    166  1.1     ross 	int	device;
    167  1.1     ross 
    168  1.1     ross 	if (buspin == 0)	/* No IRQ used. */
    169  1.1     ross 		return 1;
    170  1.1     ross 	if (!(1 <= buspin && buspin <= 4))
    171  1.1     ross 		goto bad;
    172  1.1     ross 
    173  1.1     ross 	alpha_pci_decompose_tag(pc_tag, bustag, NULL, &device, NULL);
    174  1.1     ross 
    175  1.1     ross 	switch(device) {
    176  1.1     ross 	case 6:
    177  1.1     ross 		if(buspin != 1)
    178  1.1     ross 			break;
    179  1.1     ross 		*ihp = 0xc;		/* integrated ncr scsi */
    180  1.1     ross 		return 0;
    181  1.1     ross 	case 11:
    182  1.1     ross 	case 12:
    183  1.1     ross 	case 13:
    184  1.1     ross 		*ihp = (device - 11) * 4 + buspin - 1;
    185  1.1     ross 		return 0;
    186  1.1     ross 	}
    187  1.1     ross 
    188  1.1     ross bad:	printf("dec_1000_intr_map: can't map dev %d pin %d\n", device, buspin);
    189  1.1     ross 	return 1;
    190  1.1     ross }
    191  1.1     ross 
    192  1.1     ross const char *
    193  1.1     ross dec_1000_intr_string(ccv, ih)
    194  1.1     ross 	void *ccv;
    195  1.1     ross 	pci_intr_handle_t ih;
    196  1.1     ross {
    197  1.1     ross 	static const char irqmsg_fmt[] = "dec_1000 irq %ld";
    198  1.1     ross         static char irqstr[sizeof irqmsg_fmt];
    199  1.1     ross 
    200  1.9  thorpej         if (ih >= PCI_NIRQ)
    201  1.5  thorpej                 panic("dec_1000_intr_string: bogus dec_1000 IRQ 0x%lx\n", ih);
    202  1.1     ross 
    203  1.6     ross         snprintf(irqstr, sizeof irqstr, irqmsg_fmt, ih);
    204  1.1     ross         return (irqstr);
    205  1.8      cgd }
    206  1.8      cgd 
    207  1.8      cgd const struct evcnt *
    208  1.8      cgd dec_1000_intr_evcnt(ccv, ih)
    209  1.8      cgd 	void *ccv;
    210  1.8      cgd 	pci_intr_handle_t ih;
    211  1.8      cgd {
    212  1.8      cgd 
    213  1.9  thorpej 	if (ih >= PCI_NIRQ)
    214  1.9  thorpej 		panic("dec_1000_intr_evcnt: bogus dec_1000 IRQ 0x%lx\n", ih);
    215  1.9  thorpej 
    216  1.9  thorpej 	return (alpha_shared_intr_evcnt(dec_1000_pci_intr, ih));
    217  1.1     ross }
    218  1.1     ross 
    219  1.1     ross void *
    220  1.1     ross dec_1000_intr_establish(ccv, ih, level, func, arg)
    221  1.1     ross         void *ccv, *arg;
    222  1.1     ross         pci_intr_handle_t ih;
    223  1.1     ross         int level;
    224  1.1     ross         int (*func) __P((void *));
    225  1.1     ross {
    226  1.1     ross 	void *cookie;
    227  1.1     ross 
    228  1.9  thorpej         if (ih >= PCI_NIRQ)
    229  1.5  thorpej                 panic("dec_1000_intr_establish: IRQ too high, 0x%lx\n", ih);
    230  1.1     ross 
    231  1.1     ross 	cookie = alpha_shared_intr_establish(dec_1000_pci_intr, ih, IST_LEVEL,
    232  1.1     ross 	    level, func, arg, "dec_1000 irq");
    233  1.1     ross 
    234  1.1     ross 	if (cookie != NULL &&
    235  1.1     ross 	    alpha_shared_intr_isactive(dec_1000_pci_intr, ih))
    236  1.1     ross 		dec_1000_enable_intr(ih);
    237  1.1     ross 	return (cookie);
    238  1.1     ross }
    239  1.1     ross 
    240  1.1     ross void
    241  1.1     ross dec_1000_intr_disestablish(ccv, cookie)
    242  1.1     ross         void *ccv, *cookie;
    243  1.1     ross {
    244  1.4  thorpej 	struct alpha_shared_intrhand *ih = cookie;
    245  1.4  thorpej 	unsigned int irq = ih->ih_num;
    246  1.4  thorpej 	int s;
    247  1.4  thorpej 
    248  1.4  thorpej 	s = splhigh();
    249  1.4  thorpej 
    250  1.4  thorpej 	alpha_shared_intr_disestablish(dec_1000_pci_intr, cookie,
    251  1.4  thorpej 	    "dec_1000 irq");
    252  1.4  thorpej 	if (alpha_shared_intr_isactive(dec_1000_pci_intr, irq) == 0) {
    253  1.4  thorpej 		dec_1000_disable_intr(irq);
    254  1.4  thorpej 		alpha_shared_intr_set_dfltsharetype(dec_1000_pci_intr, irq,
    255  1.4  thorpej 		    IST_NONE);
    256  1.4  thorpej 	}
    257  1.4  thorpej 
    258  1.4  thorpej 	splx(s);
    259  1.1     ross }
    260  1.1     ross 
    261  1.1     ross static void
    262  1.1     ross dec_1000_iointr(framep, vec)
    263  1.1     ross 	void *framep;
    264  1.1     ross 	unsigned long vec;
    265  1.1     ross {
    266  1.1     ross 	int irq;
    267  1.1     ross 
    268  1.1     ross 	if (vec >= 0x900) {
    269  1.9  thorpej 		if (vec >= 0x900 + (PCI_NIRQ << 4))
    270  1.5  thorpej 			panic("dec_1000_iointr: vec 0x%lx out of range\n", vec);
    271  1.1     ross 		irq = (vec - 0x900) >> 4;
    272  1.1     ross 
    273  1.1     ross 		if (!alpha_shared_intr_dispatch(dec_1000_pci_intr, irq)) {
    274  1.1     ross 			alpha_shared_intr_stray(dec_1000_pci_intr, irq,
    275  1.1     ross 			    "dec_1000 irq");
    276  1.3  thorpej 			if (ALPHA_SHARED_INTR_DISABLE(dec_1000_pci_intr, irq))
    277  1.1     ross 				dec_1000_disable_intr(irq);
    278  1.1     ross 		}
    279  1.1     ross 		return;
    280  1.1     ross 	}
    281  1.7  thorpej #if NSIO > 0 || NPCEB > 0
    282  1.1     ross 	if (vec >= 0x800) {
    283  1.1     ross 		sio_iointr(framep, vec);
    284  1.1     ross 		return;
    285  1.1     ross 	}
    286  1.1     ross #endif
    287  1.5  thorpej 	panic("dec_1000_iointr: weird vec 0x%lx\n", vec);
    288  1.1     ross }
    289  1.1     ross 
    290  1.1     ross /*
    291  1.1     ross  * Read and write the mystery ICU IMR registers
    292  1.1     ross  */
    293  1.1     ross 
    294  1.1     ross #define	IR() bus_space_read_2(another_mystery_icu_iot,		\
    295  1.1     ross 				another_mystery_icu_ioh, 0)
    296  1.1     ross 
    297  1.1     ross #define	IW(v) bus_space_write_2(another_mystery_icu_iot,	\
    298  1.1     ross 				another_mystery_icu_ioh, 0, (v))
    299  1.1     ross 
    300  1.1     ross /*
    301  1.1     ross  * Enable and disable interrupts at the ICU level
    302  1.1     ross  */
    303  1.1     ross 
    304  1.1     ross static void
    305  1.1     ross dec_1000_enable_intr(irq)
    306  1.1     ross 	int irq;
    307  1.1     ross {
    308  1.1     ross 	IW(IR() | 1 << irq);
    309  1.1     ross }
    310  1.1     ross 
    311  1.1     ross static void
    312  1.1     ross dec_1000_disable_intr(irq)
    313  1.1     ross 	int irq;
    314  1.1     ross {
    315  1.1     ross 	IW(IR() & ~(1 << irq));
    316  1.1     ross }
    317  1.1     ross /*
    318  1.1     ross  * Initialize mystery ICU
    319  1.1     ross  */
    320  1.1     ross static void
    321  1.1     ross pci_1000_imi()
    322  1.1     ross {
    323  1.1     ross 	IW(0);					/* XXX ?? */
    324  1.1     ross }
    325