1 /* $NetBSD: pci_2100_a500.c,v 1.18 2021/07/04 22:42:36 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 33 34 __KERNEL_RCSID(0, "$NetBSD: pci_2100_a500.c,v 1.18 2021/07/04 22:42:36 thorpej Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/param.h> 38 #include <sys/time.h> 39 #include <sys/systm.h> 40 #include <sys/errno.h> 41 #include <sys/kmem.h> 42 #include <sys/device.h> 43 #include <sys/cpu.h> 44 #include <sys/syslog.h> 45 46 #include <machine/autoconf.h> 47 #include <machine/rpb.h> 48 49 #include <dev/eisa/eisavar.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <alpha/pci/ttwogareg.h> 55 #include <alpha/pci/ttwogavar.h> 56 #include <alpha/pci/pci_2100_a500.h> 57 58 static bus_space_tag_t pic_iot; 59 static bus_space_handle_t pic_master_ioh; 60 static bus_space_handle_t pic_slave_ioh[4]; 61 static bus_space_handle_t pic_elcr_ioh; 62 63 static const int pic_slave_to_master[4] = { 1, 3, 4, 5 }; 64 65 static int dec_2100_a500_pic_intr_map(const struct pci_attach_args *, 66 pci_intr_handle_t *); 67 68 static int dec_2100_a500_icic_intr_map(const struct pci_attach_args *, 69 pci_intr_handle_t *); 70 71 static void *dec_2100_a500_intr_establish(pci_chipset_tag_t, 72 pci_intr_handle_t, int, int (*)(void *), void *); 73 static void dec_2100_a500_intr_disestablish(pci_chipset_tag_t, void *); 74 75 static int dec_2100_a500_eisa_intr_map(void *, u_int, 76 eisa_intr_handle_t *); 77 static const char *dec_2100_a500_eisa_intr_string(void *, int, char *, size_t); 78 static const struct evcnt *dec_2100_a500_eisa_intr_evcnt(void *, int); 79 static void *dec_2100_a500_eisa_intr_establish(void *, int, int, int, 80 int (*)(void *), void *); 81 static void dec_2100_a500_eisa_intr_disestablish(void *, void *); 82 static int dec_2100_a500_eisa_intr_alloc(void *, int, int, int *); 83 84 #define PCI_STRAY_MAX 5 85 86 /* 87 * On systems with cascaded 8259s, it's actually 32. Systems which 88 * use the ICIC interrupt logic have 64, however. 89 */ 90 #define SABLE_MAX_IRQ 64 91 #define SABLE_8259_MAX_IRQ 32 92 93 static void dec_2100_a500_iointr(void *, u_long); 94 95 static void dec_2100_a500_pic_enable_intr(struct ttwoga_config *, 96 int, int); 97 static void dec_2100_a500_pic_init_intr(struct ttwoga_config *); 98 static void dec_2100_a500_pic_setlevel(struct ttwoga_config *, int, int); 99 static void dec_2100_a500_pic_eoi(struct ttwoga_config *, int); 100 101 static void dec_2100_a500_icic_enable_intr(struct ttwoga_config *, 102 int, int); 103 static void dec_2100_a500_icic_init_intr(struct ttwoga_config *); 104 static void dec_2100_a500_icic_setlevel(struct ttwoga_config *, int, int); 105 static void dec_2100_a500_icic_eoi(struct ttwoga_config *, int); 106 107 #define T2_IRQ_EISA_START 7 108 #define T2_IRQ_EISA_COUNT 16 109 110 #define T2_IRQ_IS_EISA(irq) \ 111 ((irq) >= T2_IRQ_EISA_START && \ 112 (irq) < (T2_IRQ_EISA_START + T2_IRQ_EISA_COUNT)) 113 114 static const int dec_2100_a500_intr_deftype[SABLE_MAX_IRQ] = { 115 IST_LEVEL, /* PCI slot 0 A */ 116 IST_LEVEL, /* on-board SCSI */ 117 IST_LEVEL, /* on-board Ethernet */ 118 IST_EDGE, /* mouse */ 119 IST_LEVEL, /* PCI slot 1 A */ 120 IST_LEVEL, /* PCI slot 2 A */ 121 IST_EDGE, /* keyboard */ 122 IST_EDGE, /* floppy (EISA IRQ 0) */ 123 IST_EDGE, /* serial port 1 (EISA IRQ 1) */ 124 IST_EDGE, /* parallel port (EISA IRQ 2) */ 125 IST_NONE, /* EISA IRQ 3 (edge/level) */ 126 IST_NONE, /* EISA IRQ 4 (edge/level) */ 127 IST_NONE, /* EISA IRQ 5 (edge/level) */ 128 IST_NONE, /* EISA IRQ 6 (edge/level) */ 129 IST_NONE, /* EISA IRQ 7 (edge/level) */ 130 IST_EDGE, /* serial port 0 (EISA IRQ 8) */ 131 IST_NONE, /* EISA IRQ 9 (edge/level) */ 132 IST_NONE, /* EISA IRQ 10 (edge/level) */ 133 IST_NONE, /* EISA IRQ 11 (edge/level) */ 134 IST_NONE, /* EISA IRQ 12 (edge/level) */ 135 IST_LEVEL, /* PCI slot 2 B (EISA IRQ 13 n/c) */ 136 IST_NONE, /* EISA IRQ 14 (edge/level) */ 137 IST_NONE, /* EISA IRQ 15 (edge/level) */ 138 IST_LEVEL, /* I2C (XXX double-check this) */ 139 IST_LEVEL, /* PCI slot 0 B */ 140 IST_LEVEL, /* PCI slot 1 B */ 141 IST_LEVEL, /* PCI slot 0 C */ 142 IST_LEVEL, /* PCI slot 1 C */ 143 IST_LEVEL, /* PCI slot 2 C */ 144 IST_LEVEL, /* PCI slot 0 D */ 145 IST_LEVEL, /* PCI slot 1 D */ 146 IST_LEVEL, /* PCI slot 2 D */ 147 148 /* 149 * These are the PCI interrupts on the T3/T4 systems. See 150 * dec_2100_a500_icic_intr_map() for the mapping. 151 */ 152 IST_LEVEL, 153 IST_LEVEL, 154 IST_LEVEL, 155 IST_LEVEL, 156 IST_LEVEL, 157 IST_LEVEL, 158 IST_LEVEL, 159 IST_LEVEL, 160 IST_LEVEL, 161 IST_LEVEL, 162 IST_LEVEL, 163 IST_LEVEL, 164 IST_LEVEL, 165 IST_LEVEL, 166 IST_LEVEL, 167 IST_LEVEL, 168 IST_LEVEL, 169 IST_LEVEL, 170 IST_LEVEL, 171 IST_LEVEL, 172 IST_LEVEL, 173 IST_LEVEL, 174 IST_LEVEL, 175 IST_LEVEL, 176 IST_LEVEL, 177 IST_LEVEL, 178 IST_LEVEL, 179 IST_LEVEL, 180 IST_LEVEL, 181 IST_LEVEL, 182 IST_LEVEL, 183 IST_LEVEL, 184 }; 185 186 static void 187 pci_2100_a500_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt, 188 pci_chipset_tag_t pc) 189 { 190 struct ttwoga_config *tcp = core; 191 struct evcnt *ev; 192 char *cp; 193 int i; 194 195 pic_iot = iot; 196 197 pc->pc_intr_v = core; 198 pc->pc_intr_string = alpha_pci_generic_intr_string; 199 pc->pc_intr_evcnt = alpha_pci_generic_intr_evcnt; 200 pc->pc_intr_establish = dec_2100_a500_intr_establish; 201 pc->pc_intr_disestablish = dec_2100_a500_intr_disestablish; 202 203 /* Not supported on T2. */ 204 pc->pc_pciide_compat_intr_establish = NULL; 205 206 pc->pc_intr_desc = "T2"; 207 /* 64 16-byte vectors per hose. */ 208 pc->pc_vecbase = 0x800 + ((64 * 16) * tcp->tc_hose); 209 pc->pc_nirq = SABLE_MAX_IRQ; 210 211 pc->pc_shared_intrs = alpha_shared_intr_alloc(pc->pc_nirq); 212 213 for (i = 0; i < pc->pc_nirq; i++) { 214 alpha_shared_intr_set_maxstrays(pc->pc_shared_intrs, i, 215 PCI_STRAY_MAX); 216 alpha_shared_intr_set_private(pc->pc_shared_intrs, i, 217 pc->pc_intr_v); 218 alpha_shared_intr_set_dfltsharetype(pc->pc_shared_intrs, i, 219 tcp->tc_hose == 0 ? dec_2100_a500_intr_deftype[i] 220 : IST_LEVEL); 221 222 ev = alpha_shared_intr_evcnt(pc->pc_shared_intrs, i); 223 cp = kmem_asprintf("irq %d", 224 T2_IRQ_IS_EISA(i) ? i - T2_IRQ_EISA_START : i); 225 226 alpha_shared_intr_set_string(pc->pc_shared_intrs, i, cp); 227 228 evcnt_attach_dynamic(ev, EVCNT_TYPE_INTR, NULL, 229 T2_IRQ_IS_EISA(i) ? "eisa" : pc->pc_intr_desc, cp); 230 } 231 232 /* 233 * T2 uses a custom layout of cascaded 8259 PICs for interrupt 234 * control. T3 and T4 use a built-in interrupt controller. 235 * 236 * Note that the external PCI bus (Hose 1) always uses 237 * the new interrupt controller. 238 */ 239 if (tcp->tc_rev < TRN_T3 && tcp->tc_hose == 0) { 240 pc->pc_intr_map = dec_2100_a500_pic_intr_map; 241 tcp->tc_enable_intr = dec_2100_a500_pic_enable_intr; 242 tcp->tc_setlevel = dec_2100_a500_pic_setlevel; 243 tcp->tc_eoi = dec_2100_a500_pic_eoi; 244 dec_2100_a500_pic_init_intr(tcp); 245 } else { 246 pc->pc_intr_map = dec_2100_a500_icic_intr_map; 247 tcp->tc_enable_intr = dec_2100_a500_icic_enable_intr; 248 tcp->tc_setlevel = dec_2100_a500_icic_setlevel; 249 tcp->tc_eoi = dec_2100_a500_icic_eoi; 250 dec_2100_a500_icic_init_intr(tcp); 251 } 252 } 253 ALPHA_PCI_INTR_INIT(ST_DEC_2100_A500, pci_2100_a500_pickintr) 254 ALPHA_PCI_INTR_INIT(ST_DEC_2100A_A500, pci_2100_a500_pickintr) 255 256 void 257 pci_2100_a500_eisa_pickintr(pci_chipset_tag_t pc, eisa_chipset_tag_t ec) 258 { 259 260 ec->ec_v = pc->pc_intr_v; 261 ec->ec_intr_map = dec_2100_a500_eisa_intr_map; 262 ec->ec_intr_string = dec_2100_a500_eisa_intr_string; 263 ec->ec_intr_evcnt = dec_2100_a500_eisa_intr_evcnt; 264 ec->ec_intr_establish = dec_2100_a500_eisa_intr_establish; 265 ec->ec_intr_disestablish = dec_2100_a500_eisa_intr_disestablish; 266 } 267 268 void 269 pci_2100_a500_isa_pickintr(pci_chipset_tag_t pc, isa_chipset_tag_t ic) 270 { 271 272 ic->ic_v = pc->pc_intr_v; 273 ic->ic_intr_evcnt = dec_2100_a500_eisa_intr_evcnt; 274 ic->ic_intr_establish = dec_2100_a500_eisa_intr_establish; 275 ic->ic_intr_disestablish = dec_2100_a500_eisa_intr_disestablish; 276 ic->ic_intr_alloc = dec_2100_a500_eisa_intr_alloc; 277 } 278 279 /***************************************************************************** 280 * PCI interrupt support. 281 *****************************************************************************/ 282 283 static int 284 dec_2100_a500_pic_intr_map(const struct pci_attach_args *pa, 285 pci_intr_handle_t *ihp) 286 { 287 /* 288 * Interrupts in the Sable are even more of a pain than other 289 * Alpha systems. The interrupt logic is made up of 5 8259 290 * PICs, arranged as follows: 291 * 292 * Slave 0 --------------------------------+ 293 * 0 PCI slot 0 A | 294 * 1 on-board SCSI | 295 * 2 on-board Ethernet | 296 * 3 mouse | 297 * 4 PCI slot 1 A | 298 * 5 PCI slot 2 A | 299 * 6 keyboard | 300 * 7 floppy (EISA IRQ 0) | 301 * | 302 * Slave 1 ------------------------+ | Master 303 * 0 serial port 1 (EISA IRQ 1) | | 0 ESC interrupt 304 * 1 parallel port (EISA IRQ 2) | +-- 1 Slave 0 305 * 2 EISA IRQ 3 | 2 reserved 306 * 3 EISA IRQ 4 +---------- 3 Slave 1 307 * 4 EISA IRQ 5 +---------- 4 Slave 2 308 * 5 EISA IRQ 6 | +-- 5 Slave 3 309 * 6 EISA IRQ 7 | | 6 reserved 310 * 7 serial port 0 (EISA IRQ 8) | | 7 n/c 311 * | | 312 * Slave 2 ------------------------+ | 313 * 0 EISA IRQ 9 | 314 * 1 EISA IRQ 10 | 315 * 2 EISA IRQ 11 | 316 * 3 EISA IRQ 12 | 317 * 4 PCI slot 2 B (EISA IRQ 13 n/c) | 318 * 5 EISA IRQ 14 | 319 * 6 EISA IRQ 15 | 320 * 7 I2C | 321 * | 322 * Slave 3 --------------------------------+ 323 * 0 PCI slot 0 B 324 * 1 PCI slot 1 B 325 * 2 PCI slot 0 C 326 * 3 PCI slot 1 C 327 * 4 PCI slot 2 C 328 * 5 PCI slot 0 D 329 * 6 PCI slot 1 D 330 * 7 PCI slot 2 D 331 * 332 * Careful readers will note that the PCEB does not handle ISA 333 * interrupts at all; when ISA interrupts are established, they 334 * must be mapped to Sable interrupts. Thankfully, this is easy 335 * to do. 336 * 337 * The T3 and T4, generally found on Lynx, use a totally different 338 * scheme because they have more PCI interrupts to handle; see below. 339 */ 340 static const int irqmap[9/*device*/][4/*pin*/] = { 341 { 0x02, -1, -1, -1 }, /* 0: on-board Ethernet */ 342 { 0x01, -1, -1, -1 }, /* 1: on-board SCSI */ 343 { -1, -1, -1, -1 }, /* 2: invalid */ 344 { -1, -1, -1, -1 }, /* 3: invalid */ 345 { -1, -1, -1, -1 }, /* 4: invalid */ 346 { -1, -1, -1, -1 }, /* 5: invalid */ 347 { 0x00, 0x18, 0x1a, 0x1d }, /* 6: PCI slot 0 */ 348 { 0x04, 0x19, 0x1b, 0x1e }, /* 7: PCI slot 1 */ 349 { 0x05, 0x14, 0x1c, 0x1f }, /* 8: PCI slot 2 */ 350 }; 351 pcitag_t bustag = pa->pa_intrtag; 352 int buspin = pa->pa_intrpin; 353 pci_chipset_tag_t pc = pa->pa_pc; 354 int device, irq; 355 356 if (buspin == 0) { 357 /* No IRQ used. */ 358 return (1); 359 } 360 361 if (buspin < 0 || buspin > 4) { 362 printf("dec_2100_a500_pic_intr_map: bad interrupt pin %d\n", 363 buspin); 364 return (1); 365 } 366 367 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 368 if (device > 8) { 369 printf("dec_2100_a500_pic_intr_map: bad device %d\n", 370 device); 371 return (1); 372 } 373 374 irq = irqmap[device][buspin - 1]; 375 if (irq == -1) { 376 printf("dec_2100_a500_pic_intr_map: no mapping for " 377 "device %d pin %d\n", device, buspin); 378 return (1); 379 } 380 alpha_pci_intr_handle_init(ihp, irq, 0); 381 return (0); 382 } 383 384 static int 385 dec_2100_a500_icic_intr_map(const struct pci_attach_args *pa, 386 pci_intr_handle_t *ihp) 387 { 388 pcitag_t bustag = pa->pa_intrtag; 389 int buspin = pa->pa_intrpin; 390 pci_chipset_tag_t pc = pa->pa_pc; 391 int device, irq; 392 393 if (buspin == 0) { 394 /* No IRQ used. */ 395 return (1); 396 } 397 398 if (buspin > 4) { 399 printf("dec_2100_a500_icic_intr_map: bad interrupt in %d\n", 400 buspin); 401 return (1); 402 } 403 404 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 405 switch (device) { 406 case 0: /* on-board Ethernet */ 407 irq = 24; 408 break; 409 410 case 1: /* on-board SCSI */ 411 irq = 28; 412 break; 413 414 case 6: /* PCI slots */ 415 case 7: 416 case 8: 417 irq = (32 + (4 * (device - 6))) + (buspin - 1); 418 break; 419 420 default: 421 printf("dec_2100_a500_icic_intr_map: bad device %d\n", 422 device); 423 return (1); 424 } 425 426 alpha_pci_intr_handle_init(ihp, irq, 0); 427 return (0); 428 } 429 430 static void * 431 dec_2100_a500_intr_establish(pci_chipset_tag_t const pc, 432 pci_intr_handle_t const ih, int const level, 433 int (*func)(void *), void *arg) 434 { 435 struct ttwoga_config *tcp = pc->pc_intr_v; 436 void *cookie; 437 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 438 const u_int flags = alpha_pci_intr_handle_get_flags(&ih); 439 440 KASSERT(irq < SABLE_MAX_IRQ); 441 442 cookie = alpha_shared_intr_alloc_intrhand(pc->pc_shared_intrs, irq, 443 dec_2100_a500_intr_deftype[irq], level, flags, func, arg, "T2"); 444 445 if (cookie == NULL) 446 return NULL; 447 448 mutex_enter(&cpu_lock); 449 450 if (! alpha_shared_intr_link(pc->pc_shared_intrs, cookie, "T2")) { 451 mutex_exit(&cpu_lock); 452 alpha_shared_intr_free_intrhand(cookie); 453 return NULL; 454 } 455 456 if (alpha_shared_intr_firstactive(pc->pc_shared_intrs, irq)) { 457 scb_set(pc->pc_vecbase + SCB_IDXTOVEC(irq), 458 dec_2100_a500_iointr, tcp); 459 (*tcp->tc_enable_intr)(tcp, irq, 1); 460 } 461 462 mutex_exit(&cpu_lock); 463 464 return cookie; 465 } 466 467 static void 468 dec_2100_a500_intr_disestablish(pci_chipset_tag_t const pc, void * const cookie) 469 { 470 struct ttwoga_config *tcp = pc->pc_intr_v; 471 struct alpha_shared_intrhand *ih = cookie; 472 unsigned int irq = ih->ih_num; 473 474 mutex_enter(&cpu_lock); 475 476 if (alpha_shared_intr_firstactive(pc->pc_shared_intrs, irq)) { 477 (*tcp->tc_enable_intr)(tcp, irq, 0); 478 alpha_shared_intr_set_dfltsharetype(pc->pc_shared_intrs, 479 irq, dec_2100_a500_intr_deftype[irq]); 480 scb_free(pc->pc_vecbase + SCB_IDXTOVEC(irq)); 481 } 482 483 alpha_shared_intr_unlink(pc->pc_shared_intrs, cookie, "T2"); 484 485 mutex_exit(&cpu_lock); 486 487 alpha_shared_intr_free_intrhand(cookie); 488 } 489 490 /***************************************************************************** 491 * EISA interrupt support. 492 *****************************************************************************/ 493 494 static int 495 dec_2100_a500_eisa_intr_map(void *v, u_int eirq, eisa_intr_handle_t *ihp) 496 { 497 498 if (eirq > 15) { 499 printf("dec_2100_a500_eisa_intr_map: bad EISA IRQ %d\n", 500 eirq); 501 *ihp = -1; 502 return (1); 503 } 504 505 /* 506 * EISA IRQ 13 is not connected. 507 */ 508 if (eirq == 13) { 509 printf("dec_2100_a500_eisa_intr_map: EISA IRQ 13 not " 510 "connected\n"); 511 *ihp = -1; 512 return (1); 513 } 514 515 /* 516 * Don't map to a T2 IRQ here; we must do this when we hook the 517 * interrupt up, since ISA interrupts aren't explicitly translated. 518 */ 519 520 *ihp = eirq; 521 return (0); 522 } 523 524 static const char * 525 dec_2100_a500_eisa_intr_string(void *v, int eirq, char *buf, size_t len) 526 { 527 if (eirq > 15 || eirq == 13) 528 panic("%s: bogus EISA IRQ 0x%x", __func__, eirq); 529 530 snprintf(buf, len, "eisa irq %d (T2 irq %d)", eirq, 531 eirq + T2_IRQ_EISA_START); 532 return buf; 533 } 534 535 static const struct evcnt * 536 dec_2100_a500_eisa_intr_evcnt(void *v, int eirq) 537 { 538 struct ttwoga_config *tcp = v; 539 pci_chipset_tag_t const pc = &tcp->tc_pc; 540 541 if (eirq > 15 || eirq == 13) 542 panic("%s: bogus EISA IRQ 0x%x", __func__, eirq); 543 544 return (alpha_shared_intr_evcnt(pc->pc_shared_intrs, 545 eirq + T2_IRQ_EISA_START)); 546 } 547 548 static void * 549 dec_2100_a500_eisa_intr_establish(void *v, int eirq, int type, int level, 550 int (*fn)(void *), void *arg) 551 { 552 struct ttwoga_config *tcp = v; 553 pci_chipset_tag_t const pc = &tcp->tc_pc; 554 void *cookie; 555 int irq; 556 557 if (eirq > 15 || type == IST_NONE) 558 panic("dec_2100_a500_eisa_intr_establish: bogus irq or type"); 559 560 if (eirq == 13) { 561 printf("dec_2100_a500_eisa_intr_establish: EISA IRQ 13 not " 562 "connected\n"); 563 return (NULL); 564 } 565 566 irq = eirq + T2_IRQ_EISA_START; 567 568 /* 569 * We can't change the trigger type of some interrupts. Don't allow 570 * level triggers to be hooked up to non-changeable edge triggers. 571 */ 572 if (dec_2100_a500_intr_deftype[irq] == IST_EDGE && type == IST_LEVEL) { 573 printf("dec_2100_a500_eisa_intr_establish: non-EDGE on EDGE\n"); 574 return (NULL); 575 } 576 577 cookie = alpha_shared_intr_alloc_intrhand(pc->pc_shared_intrs, irq, 578 type, level, 0, fn, arg, "T2"); 579 580 if (cookie == NULL) 581 return NULL; 582 583 mutex_enter(&cpu_lock); 584 585 if (! alpha_shared_intr_link(pc->pc_shared_intrs, cookie, "T2")) { 586 mutex_exit(&cpu_lock); 587 alpha_shared_intr_free_intrhand(cookie); 588 return NULL; 589 } 590 591 if (alpha_shared_intr_firstactive(pc->pc_shared_intrs, irq)) { 592 scb_set(pc->pc_vecbase + SCB_IDXTOVEC(irq), 593 dec_2100_a500_iointr, tcp); 594 (*tcp->tc_setlevel)(tcp, eirq, 595 alpha_shared_intr_get_sharetype(pc->pc_shared_intrs, 596 irq) == IST_LEVEL); 597 (*tcp->tc_enable_intr)(tcp, irq, 1); 598 } 599 600 mutex_exit(&cpu_lock); 601 602 return cookie; 603 } 604 605 static void 606 dec_2100_a500_eisa_intr_disestablish(void *v, void *cookie) 607 { 608 struct ttwoga_config *tcp = v; 609 pci_chipset_tag_t const pc = &tcp->tc_pc; 610 struct alpha_shared_intrhand *ih = cookie; 611 int irq = ih->ih_num; 612 613 mutex_enter(&cpu_lock); 614 615 if (alpha_shared_intr_firstactive(pc->pc_shared_intrs, irq)) { 616 (*tcp->tc_enable_intr)(tcp, irq, 0); 617 alpha_shared_intr_set_dfltsharetype(pc->pc_shared_intrs, 618 irq, dec_2100_a500_intr_deftype[irq]); 619 scb_free(pc->pc_vecbase + SCB_IDXTOVEC(irq)); 620 } 621 622 /* Remove it from the link. */ 623 alpha_shared_intr_unlink(pc->pc_shared_intrs, cookie, "T2"); 624 625 mutex_exit(&cpu_lock); 626 627 alpha_shared_intr_free_intrhand(cookie); 628 } 629 630 static int 631 dec_2100_a500_eisa_intr_alloc(void *v, int mask, int type, int *eirqp) 632 { 633 634 /* XXX Not supported right now. */ 635 return (1); 636 } 637 638 /***************************************************************************** 639 * Interrupt support routines. 640 *****************************************************************************/ 641 642 #define ICIC_ADDR(tcp, addr) \ 643 do { \ 644 alpha_mb(); \ 645 T2GA((tcp), T2_AIR) = (addr); \ 646 alpha_mb(); \ 647 alpha_mb(); \ 648 (void) T2GA((tcp), T2_AIR); \ 649 alpha_mb(); \ 650 alpha_mb(); \ 651 } while (0) 652 653 #define ICIC_READ(tcp) T2GA((tcp), T2_DIR) 654 #define ICIC_WRITE(tcp, val) \ 655 do { \ 656 alpha_mb(); \ 657 T2GA((tcp), T2_DIR) = (val); \ 658 alpha_mb(); \ 659 alpha_mb(); \ 660 } while (0) 661 662 static void 663 dec_2100_a500_iointr(void *arg, u_long vec) 664 { 665 struct ttwoga_config *tcp = arg; 666 pci_chipset_tag_t const pc = &tcp->tc_pc; 667 int irq, rv; 668 669 irq = SCB_VECTOIDX(vec - pc->pc_vecbase); 670 671 rv = alpha_shared_intr_dispatch(pc->pc_shared_intrs, irq); 672 (*tcp->tc_eoi)(tcp, irq); 673 if (rv == 0) { 674 alpha_shared_intr_stray(pc->pc_shared_intrs, irq, "T2"); 675 if (ALPHA_SHARED_INTR_DISABLE(pc->pc_shared_intrs, irq)) 676 (*tcp->tc_enable_intr)(tcp, irq, 0); 677 } else 678 alpha_shared_intr_reset_strays(pc->pc_shared_intrs, irq); 679 } 680 681 static void 682 dec_2100_a500_pic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff) 683 { 684 int pic; 685 uint8_t bit, mask; 686 687 pic = irq >> 3; 688 bit = 1 << (irq & 0x7); 689 690 mask = bus_space_read_1(pic_iot, pic_slave_ioh[pic], 1); 691 if (onoff) 692 mask &= ~bit; 693 else 694 mask |= bit; 695 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, mask); 696 } 697 698 static void 699 dec_2100_a500_icic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff) 700 { 701 uint64_t bit, mask; 702 703 bit = 1UL << irq; 704 705 ICIC_ADDR(tcp, 0x40); 706 707 mask = ICIC_READ(tcp); 708 if (onoff) 709 mask &= ~bit; 710 else 711 mask |= bit; 712 ICIC_WRITE(tcp, mask); 713 } 714 715 static void 716 dec_2100_a500_pic_init_intr(struct ttwoga_config *tcp) 717 { 718 static const int picaddr[4] = { 719 0x536, 0x53a, 0x53c, 0x53e 720 }; 721 int pic; 722 723 /* 724 * Map the master PIC. 725 */ 726 if (bus_space_map(pic_iot, 0x534, 2, 0, &pic_master_ioh)) 727 panic("dec_2100_a500_pic_init_intr: unable to map master PIC"); 728 729 /* 730 * Map all slave PICs and mask off the interrupts on them. 731 */ 732 for (pic = 0; pic < 4; pic++) { 733 if (bus_space_map(pic_iot, picaddr[pic], 2, 0, 734 &pic_slave_ioh[pic])) 735 panic("dec_2100_a500_pic_init_intr: unable to map " 736 "slave PIC %d", pic); 737 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, 0xff); 738 } 739 740 /* 741 * Map the ELCR registers. 742 */ 743 if (bus_space_map(pic_iot, 0x26, 2, 0, &pic_elcr_ioh)) 744 panic("dec_2100_a500_pic_init_intr: unable to map ELCR " 745 "registers"); 746 } 747 748 static void 749 dec_2100_a500_icic_init_intr(struct ttwoga_config *tcp) 750 { 751 752 ICIC_ADDR(tcp, 0x40); 753 ICIC_WRITE(tcp, 0xffffffffffffffffUL); 754 } 755 756 static void 757 dec_2100_a500_pic_setlevel(struct ttwoga_config *tcp, int eirq, int level) 758 { 759 int elcr; 760 uint8_t bit, mask; 761 762 switch (eirq) { /* EISA IRQ */ 763 case 3: 764 case 4: 765 case 5: 766 case 6: 767 case 7: 768 elcr = 0; 769 bit = 1 << (eirq - 3); 770 break; 771 772 case 9: 773 case 10: 774 case 11: 775 elcr = 0; 776 bit = 1 << (eirq - 4); 777 break; 778 779 case 12: 780 elcr = 1; 781 bit = 1 << (eirq - 12); 782 break; 783 784 case 14: 785 case 15: 786 elcr = 1; 787 bit = 1 << (eirq - 13); 788 break; 789 790 default: 791 panic("dec_2100_a500_pic_setlevel: bogus EISA IRQ %d", eirq); 792 } 793 794 mask = bus_space_read_1(pic_iot, pic_elcr_ioh, elcr); 795 if (level) 796 mask |= bit; 797 else 798 mask &= ~bit; 799 bus_space_write_1(pic_iot, pic_elcr_ioh, elcr, mask); 800 } 801 802 static void 803 dec_2100_a500_icic_setlevel(struct ttwoga_config *tcp, int eirq, int level) 804 { 805 uint64_t bit, mask; 806 807 switch (eirq) { 808 case 3: 809 case 4: 810 case 5: 811 case 6: 812 case 7: 813 case 9: 814 case 10: 815 case 11: 816 case 12: 817 case 14: 818 case 15: 819 bit = 1UL << (eirq + T2_IRQ_EISA_START); 820 821 ICIC_ADDR(tcp, 0x50); 822 mask = ICIC_READ(tcp); 823 if (level) 824 mask |= bit; 825 else 826 mask &= ~bit; 827 ICIC_WRITE(tcp, mask); 828 break; 829 830 default: 831 panic("dec_2100_a500_icic_setlevel: bogus EISA IRQ %d", eirq); 832 } 833 } 834 835 static void 836 dec_2100_a500_pic_eoi(struct ttwoga_config *tcp, int irq) 837 { 838 int pic; 839 840 if (irq >= 0 && irq <= 7) 841 pic = 0; 842 else if (irq >= 8 && irq <= 15) 843 pic = 1; 844 else if (irq >= 16 && irq <= 23) 845 pic = 2; 846 else 847 pic = 3; 848 849 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 0, 850 0xe0 | (irq - (8 * pic))); 851 bus_space_write_1(pic_iot, pic_master_ioh, 0, 852 0xe0 | pic_slave_to_master[pic]); 853 } 854 855 static void 856 dec_2100_a500_icic_eoi(struct ttwoga_config *tcp, int irq) 857 { 858 859 T2GA(tcp, T2_VAR) = irq; 860 alpha_mb(); 861 alpha_mb(); /* MAGIC */ 862 } 863
Indexes created Fri Sep 26 20:09:58 GMT 2025