pci_2100_a500.c revision 1.3.2.3
1 1.3.2.3 nathanw /* $NetBSD: pci_2100_a500.c,v 1.3.2.3 2002/10/18 02:34:22 nathanw Exp $ */ 2 1.3.2.2 nathanw 3 1.3.2.2 nathanw /*- 4 1.3.2.2 nathanw * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 1.3.2.2 nathanw * All rights reserved. 6 1.3.2.2 nathanw * 7 1.3.2.2 nathanw * This code is derived from software contributed to The NetBSD Foundation 8 1.3.2.2 nathanw * by Jason R. Thorpe. 9 1.3.2.2 nathanw * 10 1.3.2.2 nathanw * Redistribution and use in source and binary forms, with or without 11 1.3.2.2 nathanw * modification, are permitted provided that the following conditions 12 1.3.2.2 nathanw * are met: 13 1.3.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 14 1.3.2.2 nathanw * notice, this list of conditions and the following disclaimer. 15 1.3.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 16 1.3.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 17 1.3.2.2 nathanw * documentation and/or other materials provided with the distribution. 18 1.3.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 19 1.3.2.2 nathanw * must display the following acknowledgement: 20 1.3.2.2 nathanw * This product includes software developed by the NetBSD 21 1.3.2.2 nathanw * Foundation, Inc. and its contributors. 22 1.3.2.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its 23 1.3.2.2 nathanw * contributors may be used to endorse or promote products derived 24 1.3.2.2 nathanw * from this software without specific prior written permission. 25 1.3.2.2 nathanw * 26 1.3.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 1.3.2.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 1.3.2.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 1.3.2.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 1.3.2.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 1.3.2.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 1.3.2.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 1.3.2.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 1.3.2.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 1.3.2.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 1.3.2.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 37 1.3.2.2 nathanw */ 38 1.3.2.2 nathanw 39 1.3.2.2 nathanw #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 40 1.3.2.2 nathanw 41 1.3.2.3 nathanw __KERNEL_RCSID(0, "$NetBSD: pci_2100_a500.c,v 1.3.2.3 2002/10/18 02:34:22 nathanw Exp $"); 42 1.3.2.2 nathanw 43 1.3.2.2 nathanw #include <sys/types.h> 44 1.3.2.2 nathanw #include <sys/param.h> 45 1.3.2.2 nathanw #include <sys/time.h> 46 1.3.2.2 nathanw #include <sys/systm.h> 47 1.3.2.2 nathanw #include <sys/errno.h> 48 1.3.2.2 nathanw #include <sys/malloc.h> 49 1.3.2.2 nathanw #include <sys/device.h> 50 1.3.2.2 nathanw #include <sys/syslog.h> 51 1.3.2.2 nathanw 52 1.3.2.2 nathanw #include <machine/autoconf.h> 53 1.3.2.2 nathanw 54 1.3.2.2 nathanw #include <dev/eisa/eisavar.h> 55 1.3.2.2 nathanw 56 1.3.2.2 nathanw #include <dev/pci/pcireg.h> 57 1.3.2.2 nathanw #include <dev/pci/pcivar.h> 58 1.3.2.2 nathanw 59 1.3.2.2 nathanw #include <alpha/pci/ttwogareg.h> 60 1.3.2.2 nathanw #include <alpha/pci/ttwogavar.h> 61 1.3.2.2 nathanw #include <alpha/pci/pci_2100_a500.h> 62 1.3.2.2 nathanw 63 1.3.2.2 nathanw static bus_space_tag_t pic_iot; 64 1.3.2.2 nathanw static bus_space_handle_t pic_master_ioh; 65 1.3.2.2 nathanw static bus_space_handle_t pic_slave_ioh[4]; 66 1.3.2.2 nathanw static bus_space_handle_t pic_elcr_ioh; 67 1.3.2.2 nathanw 68 1.3.2.2 nathanw static const int pic_slave_to_master[4] = { 1, 3, 4, 5 }; 69 1.3.2.2 nathanw 70 1.3.2.2 nathanw int dec_2100_a500_pic_intr_map(struct pci_attach_args *, 71 1.3.2.2 nathanw pci_intr_handle_t *); 72 1.3.2.2 nathanw 73 1.3.2.2 nathanw int dec_2100_a500_icic_intr_map(struct pci_attach_args *, 74 1.3.2.2 nathanw pci_intr_handle_t *); 75 1.3.2.2 nathanw 76 1.3.2.2 nathanw const char *dec_2100_a500_intr_string(void *, pci_intr_handle_t); 77 1.3.2.2 nathanw const struct evcnt *dec_2100_a500_intr_evcnt(void *, pci_intr_handle_t); 78 1.3.2.2 nathanw void *dec_2100_a500_intr_establish(void *, pci_intr_handle_t, 79 1.3.2.2 nathanw int, int (*)(void *), void *); 80 1.3.2.2 nathanw void dec_2100_a500_intr_disestablish(void *, void *); 81 1.3.2.2 nathanw 82 1.3.2.2 nathanw int dec_2100_a500_eisa_intr_map(void *, u_int, eisa_intr_handle_t *); 83 1.3.2.2 nathanw const char *dec_2100_a500_eisa_intr_string(void *, int); 84 1.3.2.2 nathanw const struct evcnt *dec_2100_a500_eisa_intr_evcnt(void *, int); 85 1.3.2.2 nathanw void *dec_2100_a500_eisa_intr_establish(void *, int, int, int, 86 1.3.2.2 nathanw int (*)(void *), void *); 87 1.3.2.2 nathanw void dec_2100_a500_eisa_intr_disestablish(void *, void *); 88 1.3.2.2 nathanw int dec_2100_a500_eisa_intr_alloc(void *, int, int, int *); 89 1.3.2.2 nathanw 90 1.3.2.2 nathanw #define PCI_STRAY_MAX 5 91 1.3.2.2 nathanw 92 1.3.2.2 nathanw /* 93 1.3.2.2 nathanw * On systems with cascaded 8259s, it's actually 32. Systems which 94 1.3.2.2 nathanw * use the ICIC interrupt logic have 64, however. 95 1.3.2.2 nathanw */ 96 1.3.2.2 nathanw #define SABLE_MAX_IRQ 64 97 1.3.2.2 nathanw #define SABLE_8259_MAX_IRQ 32 98 1.3.2.2 nathanw 99 1.3.2.2 nathanw void dec_2100_a500_iointr(void *, u_long); 100 1.3.2.2 nathanw 101 1.3.2.2 nathanw void dec_2100_a500_pic_enable_intr(struct ttwoga_config *, int, int); 102 1.3.2.2 nathanw void dec_2100_a500_pic_init_intr(struct ttwoga_config *); 103 1.3.2.2 nathanw void dec_2100_a500_pic_setlevel(struct ttwoga_config *, int, int); 104 1.3.2.2 nathanw void dec_2100_a500_pic_eoi(struct ttwoga_config *, int); 105 1.3.2.2 nathanw 106 1.3.2.2 nathanw void dec_2100_a500_icic_enable_intr(struct ttwoga_config *, int, int); 107 1.3.2.2 nathanw void dec_2100_a500_icic_init_intr(struct ttwoga_config *); 108 1.3.2.2 nathanw void dec_2100_a500_icic_setlevel(struct ttwoga_config *, int, int); 109 1.3.2.2 nathanw void dec_2100_a500_icic_eoi(struct ttwoga_config *, int); 110 1.3.2.2 nathanw 111 1.3.2.2 nathanw #define T2_IRQ_EISA_START 7 112 1.3.2.2 nathanw #define T2_IRQ_EISA_COUNT 16 113 1.3.2.2 nathanw 114 1.3.2.2 nathanw #define T2_IRQ_IS_EISA(irq) \ 115 1.3.2.2 nathanw ((irq) >= T2_IRQ_EISA_START && \ 116 1.3.2.2 nathanw (irq) < (T2_IRQ_EISA_START + T2_IRQ_EISA_COUNT)) 117 1.3.2.2 nathanw 118 1.3.2.2 nathanw const int dec_2100_a500_intr_deftype[SABLE_MAX_IRQ] = { 119 1.3.2.2 nathanw IST_LEVEL, /* PCI slot 0 A */ 120 1.3.2.2 nathanw IST_LEVEL, /* on-board SCSI */ 121 1.3.2.2 nathanw IST_LEVEL, /* on-board Ethernet */ 122 1.3.2.2 nathanw IST_EDGE, /* mouse */ 123 1.3.2.2 nathanw IST_LEVEL, /* PCI slot 1 A */ 124 1.3.2.2 nathanw IST_LEVEL, /* PCI slot 2 A */ 125 1.3.2.2 nathanw IST_EDGE, /* keyboard */ 126 1.3.2.2 nathanw IST_EDGE, /* floppy (EISA IRQ 0) */ 127 1.3.2.2 nathanw IST_EDGE, /* serial port 1 (EISA IRQ 1) */ 128 1.3.2.2 nathanw IST_EDGE, /* parallel port (EISA IRQ 2) */ 129 1.3.2.2 nathanw IST_NONE, /* EISA IRQ 3 (edge/level) */ 130 1.3.2.2 nathanw IST_NONE, /* EISA IRQ 4 (edge/level) */ 131 1.3.2.2 nathanw IST_NONE, /* EISA IRQ 5 (edge/level) */ 132 1.3.2.2 nathanw IST_NONE, /* EISA IRQ 6 (edge/level) */ 133 1.3.2.2 nathanw IST_NONE, /* EISA IRQ 7 (edge/level) */ 134 1.3.2.2 nathanw IST_EDGE, /* serial port 0 (EISA IRQ 8) */ 135 1.3.2.2 nathanw IST_NONE, /* EISA IRQ 9 (edge/level) */ 136 1.3.2.2 nathanw IST_NONE, /* EISA IRQ 10 (edge/level) */ 137 1.3.2.2 nathanw IST_NONE, /* EISA IRQ 11 (edge/level) */ 138 1.3.2.2 nathanw IST_NONE, /* EISA IRQ 12 (edge/level) */ 139 1.3.2.2 nathanw IST_LEVEL, /* PCI slot 2 B (EISA IRQ 13 n/c) */ 140 1.3.2.2 nathanw IST_NONE, /* EISA IRQ 14 (edge/level) */ 141 1.3.2.2 nathanw IST_NONE, /* EISA IRQ 15 (edge/level) */ 142 1.3.2.2 nathanw IST_LEVEL, /* I2C (XXX double-check this) */ 143 1.3.2.2 nathanw IST_LEVEL, /* PCI slot 0 B */ 144 1.3.2.2 nathanw IST_LEVEL, /* PCI slot 1 B */ 145 1.3.2.2 nathanw IST_LEVEL, /* PCI slot 0 C */ 146 1.3.2.2 nathanw IST_LEVEL, /* PCI slot 1 C */ 147 1.3.2.2 nathanw IST_LEVEL, /* PCI slot 2 C */ 148 1.3.2.2 nathanw IST_LEVEL, /* PCI slot 0 D */ 149 1.3.2.2 nathanw IST_LEVEL, /* PCI slot 1 D */ 150 1.3.2.2 nathanw IST_LEVEL, /* PCI slot 2 D */ 151 1.3.2.2 nathanw 152 1.3.2.2 nathanw /* 153 1.3.2.2 nathanw * These are the PCI interrupts on the T3/T4 systems. See 154 1.3.2.2 nathanw * dec_2100_a500_icic_intr_map() for the mapping. 155 1.3.2.2 nathanw */ 156 1.3.2.2 nathanw IST_LEVEL, 157 1.3.2.2 nathanw IST_LEVEL, 158 1.3.2.2 nathanw IST_LEVEL, 159 1.3.2.2 nathanw IST_LEVEL, 160 1.3.2.2 nathanw IST_LEVEL, 161 1.3.2.2 nathanw IST_LEVEL, 162 1.3.2.2 nathanw IST_LEVEL, 163 1.3.2.2 nathanw IST_LEVEL, 164 1.3.2.2 nathanw IST_LEVEL, 165 1.3.2.2 nathanw IST_LEVEL, 166 1.3.2.2 nathanw IST_LEVEL, 167 1.3.2.2 nathanw IST_LEVEL, 168 1.3.2.2 nathanw IST_LEVEL, 169 1.3.2.2 nathanw IST_LEVEL, 170 1.3.2.2 nathanw IST_LEVEL, 171 1.3.2.2 nathanw IST_LEVEL, 172 1.3.2.2 nathanw IST_LEVEL, 173 1.3.2.2 nathanw IST_LEVEL, 174 1.3.2.2 nathanw IST_LEVEL, 175 1.3.2.2 nathanw IST_LEVEL, 176 1.3.2.2 nathanw IST_LEVEL, 177 1.3.2.2 nathanw IST_LEVEL, 178 1.3.2.2 nathanw IST_LEVEL, 179 1.3.2.2 nathanw IST_LEVEL, 180 1.3.2.2 nathanw IST_LEVEL, 181 1.3.2.2 nathanw IST_LEVEL, 182 1.3.2.2 nathanw IST_LEVEL, 183 1.3.2.2 nathanw IST_LEVEL, 184 1.3.2.2 nathanw IST_LEVEL, 185 1.3.2.2 nathanw IST_LEVEL, 186 1.3.2.2 nathanw IST_LEVEL, 187 1.3.2.2 nathanw IST_LEVEL, 188 1.3.2.2 nathanw }; 189 1.3.2.2 nathanw 190 1.3.2.2 nathanw void 191 1.3.2.2 nathanw pci_2100_a500_pickintr(struct ttwoga_config *tcp) 192 1.3.2.2 nathanw { 193 1.3.2.2 nathanw pci_chipset_tag_t pc = &tcp->tc_pc; 194 1.3.2.2 nathanw char *cp; 195 1.3.2.2 nathanw int i; 196 1.3.2.2 nathanw 197 1.3.2.2 nathanw pic_iot = &tcp->tc_iot; 198 1.3.2.2 nathanw 199 1.3.2.2 nathanw pc->pc_intr_v = tcp; 200 1.3.2.2 nathanw pc->pc_intr_string = dec_2100_a500_intr_string; 201 1.3.2.2 nathanw pc->pc_intr_evcnt = dec_2100_a500_intr_evcnt; 202 1.3.2.2 nathanw pc->pc_intr_establish = dec_2100_a500_intr_establish; 203 1.3.2.2 nathanw pc->pc_intr_disestablish = dec_2100_a500_intr_disestablish; 204 1.3.2.2 nathanw 205 1.3.2.2 nathanw /* Not supported on T2. */ 206 1.3.2.2 nathanw pc->pc_pciide_compat_intr_establish = NULL; 207 1.3.2.2 nathanw 208 1.3.2.2 nathanw tcp->tc_intrtab = alpha_shared_intr_alloc(SABLE_MAX_IRQ, 8); 209 1.3.2.2 nathanw for (i = 0; i < SABLE_MAX_IRQ; i++) { 210 1.3.2.2 nathanw alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab, 211 1.3.2.2 nathanw i, tcp->tc_hose == 0 ? 212 1.3.2.2 nathanw dec_2100_a500_intr_deftype[i] : IST_LEVEL); 213 1.3.2.2 nathanw alpha_shared_intr_set_maxstrays(tcp->tc_intrtab, 214 1.3.2.2 nathanw i, PCI_STRAY_MAX); 215 1.3.2.2 nathanw 216 1.3.2.2 nathanw cp = alpha_shared_intr_string(tcp->tc_intrtab, i); 217 1.3.2.2 nathanw sprintf(cp, "irq %d", T2_IRQ_IS_EISA(i) ? 218 1.3.2.2 nathanw i - T2_IRQ_EISA_START : i); 219 1.3.2.2 nathanw evcnt_attach_dynamic(alpha_shared_intr_evcnt( 220 1.3.2.2 nathanw tcp->tc_intrtab, i), EVCNT_TYPE_INTR, NULL, 221 1.3.2.2 nathanw T2_IRQ_IS_EISA(i) ? "eisa" : "T2", cp); 222 1.3.2.2 nathanw } 223 1.3.2.2 nathanw 224 1.3.2.2 nathanw /* 64 16-byte vectors per hose. */ 225 1.3.2.2 nathanw tcp->tc_vecbase = 0x800 + ((64 * 16) * tcp->tc_hose); 226 1.3.2.2 nathanw 227 1.3.2.2 nathanw /* 228 1.3.2.2 nathanw * T2 uses a custom layout of cascaded 8259 PICs for interrupt 229 1.3.2.2 nathanw * control. T3 and T4 use a built-in interrupt controller. 230 1.3.2.2 nathanw * 231 1.3.2.2 nathanw * Note that the external PCI bus (Hose 1) always uses 232 1.3.2.2 nathanw * the new interrupt controller. 233 1.3.2.2 nathanw */ 234 1.3.2.2 nathanw if (tcp->tc_rev < TRN_T3 && tcp->tc_hose == 0) { 235 1.3.2.2 nathanw pc->pc_intr_map = dec_2100_a500_pic_intr_map; 236 1.3.2.2 nathanw tcp->tc_enable_intr = dec_2100_a500_pic_enable_intr; 237 1.3.2.2 nathanw tcp->tc_setlevel = dec_2100_a500_pic_setlevel; 238 1.3.2.2 nathanw tcp->tc_eoi = dec_2100_a500_pic_eoi; 239 1.3.2.2 nathanw dec_2100_a500_pic_init_intr(tcp); 240 1.3.2.2 nathanw } else { 241 1.3.2.2 nathanw pc->pc_intr_map = dec_2100_a500_icic_intr_map; 242 1.3.2.2 nathanw tcp->tc_enable_intr = dec_2100_a500_icic_enable_intr; 243 1.3.2.2 nathanw tcp->tc_setlevel = dec_2100_a500_icic_setlevel; 244 1.3.2.2 nathanw tcp->tc_eoi = dec_2100_a500_icic_eoi; 245 1.3.2.2 nathanw dec_2100_a500_icic_init_intr(tcp); 246 1.3.2.2 nathanw } 247 1.3.2.2 nathanw } 248 1.3.2.2 nathanw 249 1.3.2.2 nathanw void 250 1.3.2.2 nathanw pci_2100_a500_eisa_pickintr(pci_chipset_tag_t pc, eisa_chipset_tag_t ec) 251 1.3.2.2 nathanw { 252 1.3.2.2 nathanw 253 1.3.2.2 nathanw ec->ec_v = pc->pc_intr_v; 254 1.3.2.2 nathanw ec->ec_intr_map = dec_2100_a500_eisa_intr_map; 255 1.3.2.2 nathanw ec->ec_intr_string = dec_2100_a500_eisa_intr_string; 256 1.3.2.2 nathanw ec->ec_intr_evcnt = dec_2100_a500_eisa_intr_evcnt; 257 1.3.2.2 nathanw ec->ec_intr_establish = dec_2100_a500_eisa_intr_establish; 258 1.3.2.2 nathanw ec->ec_intr_disestablish = dec_2100_a500_eisa_intr_disestablish; 259 1.3.2.2 nathanw } 260 1.3.2.2 nathanw 261 1.3.2.2 nathanw void 262 1.3.2.2 nathanw pci_2100_a500_isa_pickintr(pci_chipset_tag_t pc, isa_chipset_tag_t ic) 263 1.3.2.2 nathanw { 264 1.3.2.2 nathanw 265 1.3.2.2 nathanw ic->ic_v = pc->pc_intr_v; 266 1.3.2.2 nathanw ic->ic_intr_evcnt = dec_2100_a500_eisa_intr_evcnt; 267 1.3.2.2 nathanw ic->ic_intr_establish = dec_2100_a500_eisa_intr_establish; 268 1.3.2.2 nathanw ic->ic_intr_disestablish = dec_2100_a500_eisa_intr_disestablish; 269 1.3.2.2 nathanw ic->ic_intr_alloc = dec_2100_a500_eisa_intr_alloc; 270 1.3.2.2 nathanw } 271 1.3.2.2 nathanw 272 1.3.2.2 nathanw /***************************************************************************** 273 1.3.2.2 nathanw * PCI interrupt support. 274 1.3.2.2 nathanw *****************************************************************************/ 275 1.3.2.2 nathanw 276 1.3.2.2 nathanw int 277 1.3.2.2 nathanw dec_2100_a500_pic_intr_map(struct pci_attach_args *pa, 278 1.3.2.2 nathanw pci_intr_handle_t *ihp) 279 1.3.2.2 nathanw { 280 1.3.2.2 nathanw /* 281 1.3.2.2 nathanw * Interrupts in the Sable are even more of a pain than other 282 1.3.2.2 nathanw * Alpha systems. The interrupt logic is made up of 5 8259 283 1.3.2.2 nathanw * PICs, arranged as follows: 284 1.3.2.2 nathanw * 285 1.3.2.2 nathanw * Slave 0 --------------------------------+ 286 1.3.2.2 nathanw * 0 PCI slot 0 A | 287 1.3.2.2 nathanw * 1 on-board SCSI | 288 1.3.2.2 nathanw * 2 on-board Ethernet | 289 1.3.2.2 nathanw * 3 mouse | 290 1.3.2.2 nathanw * 4 PCI slot 1 A | 291 1.3.2.2 nathanw * 5 PCI slot 2 A | 292 1.3.2.2 nathanw * 6 keyboard | 293 1.3.2.2 nathanw * 7 floppy (EISA IRQ 0) | 294 1.3.2.2 nathanw * | 295 1.3.2.2 nathanw * Slave 1 ------------------------+ | Master 296 1.3.2.2 nathanw * 0 serial port 1 (EISA IRQ 1) | | 0 ESC interrupt 297 1.3.2.2 nathanw * 1 parallel port (EISA IRQ 2) | +-- 1 Slave 0 298 1.3.2.2 nathanw * 2 EISA IRQ 3 | 2 reserved 299 1.3.2.2 nathanw * 3 EISA IRQ 4 +---------- 3 Slave 1 300 1.3.2.2 nathanw * 4 EISA IRQ 5 +---------- 4 Slave 2 301 1.3.2.2 nathanw * 5 EISA IRQ 6 | +-- 5 Slave 3 302 1.3.2.2 nathanw * 6 EISA IRQ 7 | | 6 reserved 303 1.3.2.2 nathanw * 7 serial port 0 (EISA IRQ 8) | | 7 n/c 304 1.3.2.2 nathanw * | | 305 1.3.2.2 nathanw * Slave 2 ------------------------+ | 306 1.3.2.2 nathanw * 0 EISA IRQ 9 | 307 1.3.2.2 nathanw * 1 EISA IRQ 10 | 308 1.3.2.2 nathanw * 2 EISA IRQ 11 | 309 1.3.2.2 nathanw * 3 EISA IRQ 12 | 310 1.3.2.2 nathanw * 4 PCI slot 2 B (EISA IRQ 13 n/c) | 311 1.3.2.2 nathanw * 5 EISA IRQ 14 | 312 1.3.2.2 nathanw * 6 EISA IRQ 15 | 313 1.3.2.2 nathanw * 7 I2C | 314 1.3.2.2 nathanw * | 315 1.3.2.2 nathanw * Slave 3 --------------------------------+ 316 1.3.2.2 nathanw * 0 PCI slot 0 B 317 1.3.2.2 nathanw * 1 PCI slot 1 B 318 1.3.2.2 nathanw * 2 PCI slot 0 C 319 1.3.2.2 nathanw * 3 PCI slot 1 C 320 1.3.2.2 nathanw * 4 PCI slot 2 C 321 1.3.2.2 nathanw * 5 PCI slot 0 D 322 1.3.2.2 nathanw * 6 PCI slot 1 D 323 1.3.2.2 nathanw * 7 PCI slot 2 D 324 1.3.2.2 nathanw * 325 1.3.2.2 nathanw * Careful readers will note that the PCEB does not handle ISA 326 1.3.2.2 nathanw * interrupts at all; when ISA interrupts are established, they 327 1.3.2.2 nathanw * must be mapped to Sable interrupts. Thankfully, this is easy 328 1.3.2.2 nathanw * to do. 329 1.3.2.2 nathanw * 330 1.3.2.2 nathanw * The T3 and T4, generally found on Lynx, use a totally different 331 1.3.2.2 nathanw * scheme because they have more PCI interrupts to handle; see below. 332 1.3.2.2 nathanw */ 333 1.3.2.2 nathanw static const int irqmap[9/*device*/][4/*pin*/] = { 334 1.3.2.2 nathanw { 0x02, -1, -1, -1 }, /* 0: on-board Ethernet */ 335 1.3.2.2 nathanw { 0x01, -1, -1, -1 }, /* 1: on-board SCSI */ 336 1.3.2.2 nathanw { -1, -1, -1, -1 }, /* 2: invalid */ 337 1.3.2.2 nathanw { -1, -1, -1, -1 }, /* 3: invalid */ 338 1.3.2.2 nathanw { -1, -1, -1, -1 }, /* 4: invalid */ 339 1.3.2.2 nathanw { -1, -1, -1, -1 }, /* 5: invalid */ 340 1.3.2.2 nathanw { 0x00, 0x18, 0x1a, 0x1d }, /* 6: PCI slot 0 */ 341 1.3.2.2 nathanw { 0x04, 0x19, 0x1b, 0x1e }, /* 7: PCI slot 1 */ 342 1.3.2.2 nathanw { 0x05, 0x14, 0x1c, 0x1f }, /* 8: PCI slot 2 */ 343 1.3.2.2 nathanw }; 344 1.3.2.2 nathanw pcitag_t bustag = pa->pa_intrtag; 345 1.3.2.2 nathanw int buspin = pa->pa_intrpin; 346 1.3.2.2 nathanw pci_chipset_tag_t pc = pa->pa_pc; 347 1.3.2.2 nathanw int device, irq; 348 1.3.2.2 nathanw 349 1.3.2.2 nathanw if (buspin == 0) { 350 1.3.2.2 nathanw /* No IRQ used. */ 351 1.3.2.2 nathanw return (1); 352 1.3.2.2 nathanw } 353 1.3.2.2 nathanw 354 1.3.2.2 nathanw if (buspin > 4) { 355 1.3.2.2 nathanw printf("dec_2100_a500_pic_intr_map: bad interrupt pin %d\n", 356 1.3.2.2 nathanw buspin); 357 1.3.2.2 nathanw return (1); 358 1.3.2.2 nathanw } 359 1.3.2.2 nathanw 360 1.3.2.2 nathanw pci_decompose_tag(pc, bustag, NULL, &device, NULL); 361 1.3.2.2 nathanw if (device > 8) { 362 1.3.2.2 nathanw printf("dec_2100_a500_pic_intr_map: bad device %d\n", 363 1.3.2.2 nathanw device); 364 1.3.2.2 nathanw return (1); 365 1.3.2.2 nathanw } 366 1.3.2.2 nathanw 367 1.3.2.2 nathanw irq = irqmap[device][buspin - 1]; 368 1.3.2.2 nathanw if (irq == -1) { 369 1.3.2.2 nathanw printf("dec_2100_a500_pic_intr_map: no mapping for " 370 1.3.2.2 nathanw "device %d pin %d\n", device, buspin); 371 1.3.2.2 nathanw return (1); 372 1.3.2.2 nathanw } 373 1.3.2.2 nathanw *ihp = irq; 374 1.3.2.2 nathanw return (0); 375 1.3.2.2 nathanw } 376 1.3.2.2 nathanw 377 1.3.2.2 nathanw int 378 1.3.2.2 nathanw dec_2100_a500_icic_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 379 1.3.2.2 nathanw { 380 1.3.2.2 nathanw pcitag_t bustag = pa->pa_intrtag; 381 1.3.2.2 nathanw int buspin = pa->pa_intrpin; 382 1.3.2.2 nathanw pci_chipset_tag_t pc = pa->pa_pc; 383 1.3.2.2 nathanw int device, irq; 384 1.3.2.2 nathanw 385 1.3.2.2 nathanw if (buspin == 0) { 386 1.3.2.2 nathanw /* No IRQ used. */ 387 1.3.2.2 nathanw return (1); 388 1.3.2.2 nathanw } 389 1.3.2.2 nathanw 390 1.3.2.2 nathanw if (buspin > 4) { 391 1.3.2.2 nathanw printf("dec_2100_a500_icic_intr_map: bad interrupt in %d\n", 392 1.3.2.2 nathanw buspin); 393 1.3.2.2 nathanw return (1); 394 1.3.2.2 nathanw } 395 1.3.2.2 nathanw 396 1.3.2.2 nathanw pci_decompose_tag(pc, bustag, NULL, &device, NULL); 397 1.3.2.2 nathanw switch (device) { 398 1.3.2.2 nathanw case 0: /* on-board Ethernet */ 399 1.3.2.2 nathanw irq = 24; 400 1.3.2.2 nathanw break; 401 1.3.2.2 nathanw 402 1.3.2.2 nathanw case 1: /* on-board SCSI */ 403 1.3.2.2 nathanw irq = 28; 404 1.3.2.2 nathanw break; 405 1.3.2.2 nathanw 406 1.3.2.2 nathanw case 6: /* PCI slots */ 407 1.3.2.2 nathanw case 7: 408 1.3.2.2 nathanw case 8: 409 1.3.2.2 nathanw irq = (32 + (4 * (device - 6))) + (buspin - 1); 410 1.3.2.2 nathanw break; 411 1.3.2.2 nathanw 412 1.3.2.2 nathanw default: 413 1.3.2.2 nathanw printf("dec_2100_a500_icic_intr_map: bad device %d\n", 414 1.3.2.2 nathanw device); 415 1.3.2.2 nathanw return (1); 416 1.3.2.2 nathanw } 417 1.3.2.2 nathanw 418 1.3.2.2 nathanw *ihp = irq; 419 1.3.2.2 nathanw return (0); 420 1.3.2.2 nathanw } 421 1.3.2.2 nathanw 422 1.3.2.2 nathanw const char * 423 1.3.2.2 nathanw dec_2100_a500_intr_string(void *v, pci_intr_handle_t ih) 424 1.3.2.2 nathanw { 425 1.3.2.2 nathanw static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 426 1.3.2.2 nathanw 427 1.3.2.2 nathanw if (ih >= SABLE_MAX_IRQ) 428 1.3.2.3 nathanw panic("dec_2100_a500_intr_string: bogus T2 IRQ 0x%lx", ih); 429 1.3.2.2 nathanw 430 1.3.2.2 nathanw sprintf(irqstr, "T2 irq %ld", ih); 431 1.3.2.2 nathanw return (irqstr); 432 1.3.2.2 nathanw } 433 1.3.2.2 nathanw 434 1.3.2.2 nathanw const struct evcnt * 435 1.3.2.2 nathanw dec_2100_a500_intr_evcnt(void *v, pci_intr_handle_t ih) 436 1.3.2.2 nathanw { 437 1.3.2.2 nathanw struct ttwoga_config *tcp = v; 438 1.3.2.2 nathanw 439 1.3.2.2 nathanw if (ih >= SABLE_MAX_IRQ) 440 1.3.2.3 nathanw panic("dec_2100_a500_intr_evcnt: bogus T2 IRQ 0x%lx", ih); 441 1.3.2.2 nathanw 442 1.3.2.2 nathanw return (alpha_shared_intr_evcnt(tcp->tc_intrtab, ih)); 443 1.3.2.2 nathanw } 444 1.3.2.2 nathanw 445 1.3.2.2 nathanw void * 446 1.3.2.2 nathanw dec_2100_a500_intr_establish(void *v, pci_intr_handle_t ih, int level, 447 1.3.2.2 nathanw int (*func)(void *), void *arg) 448 1.3.2.2 nathanw { 449 1.3.2.2 nathanw struct ttwoga_config *tcp = v; 450 1.3.2.2 nathanw void *cookie; 451 1.3.2.2 nathanw 452 1.3.2.2 nathanw if (ih >= SABLE_MAX_IRQ) 453 1.3.2.3 nathanw panic("dec_2100_a500_intr_establish: bogus IRQ 0x%lx", 454 1.3.2.2 nathanw ih); 455 1.3.2.2 nathanw 456 1.3.2.2 nathanw cookie = alpha_shared_intr_establish(tcp->tc_intrtab, ih, 457 1.3.2.2 nathanw dec_2100_a500_intr_deftype[ih], level, func, arg, "T2 irq"); 458 1.3.2.2 nathanw 459 1.3.2.2 nathanw if (cookie != NULL && 460 1.3.2.2 nathanw alpha_shared_intr_firstactive(tcp->tc_intrtab, ih)) { 461 1.3.2.2 nathanw scb_set(tcp->tc_vecbase + SCB_IDXTOVEC(ih), 462 1.3.2.2 nathanw dec_2100_a500_iointr, tcp); 463 1.3.2.2 nathanw (*tcp->tc_enable_intr)(tcp, ih, 1); 464 1.3.2.2 nathanw } 465 1.3.2.2 nathanw 466 1.3.2.2 nathanw return (cookie); 467 1.3.2.2 nathanw } 468 1.3.2.2 nathanw 469 1.3.2.2 nathanw void 470 1.3.2.2 nathanw dec_2100_a500_intr_disestablish(void *v, void *cookie) 471 1.3.2.2 nathanw { 472 1.3.2.2 nathanw struct ttwoga_config *tcp = v; 473 1.3.2.2 nathanw struct alpha_shared_intrhand *ih = cookie; 474 1.3.2.2 nathanw unsigned int irq = ih->ih_num; 475 1.3.2.2 nathanw int s; 476 1.3.2.2 nathanw 477 1.3.2.2 nathanw s = splhigh(); 478 1.3.2.2 nathanw 479 1.3.2.2 nathanw alpha_shared_intr_disestablish(tcp->tc_intrtab, cookie, 480 1.3.2.2 nathanw "T2 irq"); 481 1.3.2.2 nathanw if (alpha_shared_intr_isactive(tcp->tc_intrtab, irq) == 0) { 482 1.3.2.2 nathanw (*tcp->tc_enable_intr)(tcp, irq, 0); 483 1.3.2.2 nathanw alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab, 484 1.3.2.2 nathanw irq, dec_2100_a500_intr_deftype[irq]); 485 1.3.2.2 nathanw scb_free(tcp->tc_vecbase + SCB_IDXTOVEC(irq)); 486 1.3.2.2 nathanw } 487 1.3.2.2 nathanw 488 1.3.2.2 nathanw splx(s); 489 1.3.2.2 nathanw } 490 1.3.2.2 nathanw 491 1.3.2.2 nathanw /***************************************************************************** 492 1.3.2.2 nathanw * EISA interrupt support. 493 1.3.2.2 nathanw *****************************************************************************/ 494 1.3.2.2 nathanw 495 1.3.2.2 nathanw int 496 1.3.2.2 nathanw dec_2100_a500_eisa_intr_map(void *v, u_int eirq, eisa_intr_handle_t *ihp) 497 1.3.2.2 nathanw { 498 1.3.2.2 nathanw 499 1.3.2.2 nathanw if (eirq > 15) { 500 1.3.2.2 nathanw printf("dec_2100_a500_eisa_intr_map: bad EISA IRQ %d\n", 501 1.3.2.2 nathanw eirq); 502 1.3.2.2 nathanw *ihp = -1; 503 1.3.2.2 nathanw return (1); 504 1.3.2.2 nathanw } 505 1.3.2.2 nathanw 506 1.3.2.2 nathanw /* 507 1.3.2.2 nathanw * EISA IRQ 13 is not connected. 508 1.3.2.2 nathanw */ 509 1.3.2.2 nathanw if (eirq == 13) { 510 1.3.2.2 nathanw printf("dec_2100_a500_eisa_intr_map: EISA IRQ 13 not " 511 1.3.2.2 nathanw "connected\n"); 512 1.3.2.2 nathanw *ihp = -1; 513 1.3.2.2 nathanw return (1); 514 1.3.2.2 nathanw } 515 1.3.2.2 nathanw 516 1.3.2.2 nathanw /* 517 1.3.2.2 nathanw * Don't map to a T2 IRQ here; we must do this when we hook the 518 1.3.2.2 nathanw * interrupt up, since ISA interrupts aren't explicitly translated. 519 1.3.2.2 nathanw */ 520 1.3.2.2 nathanw 521 1.3.2.2 nathanw *ihp = eirq; 522 1.3.2.2 nathanw return (0); 523 1.3.2.2 nathanw } 524 1.3.2.2 nathanw 525 1.3.2.2 nathanw const char * 526 1.3.2.2 nathanw dec_2100_a500_eisa_intr_string(void *v, int eirq) 527 1.3.2.2 nathanw { 528 1.3.2.2 nathanw static char irqstr[32]; 529 1.3.2.2 nathanw 530 1.3.2.2 nathanw if (eirq > 15 || eirq == 13) 531 1.3.2.3 nathanw panic("dec_2100_a500_eisa_intr_string: bogus EISA IRQ 0x%x", 532 1.3.2.2 nathanw eirq); 533 1.3.2.2 nathanw 534 1.3.2.2 nathanw sprintf(irqstr, "eisa irq %d (T2 irq %d)", eirq, 535 1.3.2.2 nathanw eirq + T2_IRQ_EISA_START); 536 1.3.2.2 nathanw return (irqstr); 537 1.3.2.2 nathanw } 538 1.3.2.2 nathanw 539 1.3.2.2 nathanw const struct evcnt * 540 1.3.2.2 nathanw dec_2100_a500_eisa_intr_evcnt(void *v, int eirq) 541 1.3.2.2 nathanw { 542 1.3.2.2 nathanw struct ttwoga_config *tcp = v; 543 1.3.2.2 nathanw 544 1.3.2.2 nathanw if (eirq > 15 || eirq == 13) 545 1.3.2.3 nathanw panic("dec_2100_a500_eisa_intr_evcnt: bogus EISA IRQ 0x%x", 546 1.3.2.2 nathanw eirq); 547 1.3.2.2 nathanw 548 1.3.2.2 nathanw return (alpha_shared_intr_evcnt(tcp->tc_intrtab, 549 1.3.2.2 nathanw eirq + T2_IRQ_EISA_START)); 550 1.3.2.2 nathanw } 551 1.3.2.2 nathanw 552 1.3.2.2 nathanw void * 553 1.3.2.2 nathanw dec_2100_a500_eisa_intr_establish(void *v, int eirq, int type, int level, 554 1.3.2.2 nathanw int (*fn)(void *), void *arg) 555 1.3.2.2 nathanw { 556 1.3.2.2 nathanw struct ttwoga_config *tcp = v; 557 1.3.2.2 nathanw void *cookie; 558 1.3.2.2 nathanw int irq; 559 1.3.2.2 nathanw 560 1.3.2.2 nathanw if (eirq > 15 || type == IST_NONE) 561 1.3.2.2 nathanw panic("dec_2100_a500_eisa_intr_establish: bogus irq or type"); 562 1.3.2.2 nathanw 563 1.3.2.2 nathanw if (eirq == 13) { 564 1.3.2.2 nathanw printf("dec_2100_a500_eisa_intr_establish: EISA IRQ 13 not " 565 1.3.2.2 nathanw "connected\n"); 566 1.3.2.2 nathanw return (NULL); 567 1.3.2.2 nathanw } 568 1.3.2.2 nathanw 569 1.3.2.2 nathanw irq = eirq + T2_IRQ_EISA_START; 570 1.3.2.2 nathanw 571 1.3.2.2 nathanw /* 572 1.3.2.2 nathanw * We can't change the trigger type of some interrupts. Don't allow 573 1.3.2.2 nathanw * level triggers to be hooked up to non-changeable edge triggers. 574 1.3.2.2 nathanw */ 575 1.3.2.2 nathanw if (dec_2100_a500_intr_deftype[irq] == IST_EDGE && type == IST_LEVEL) { 576 1.3.2.2 nathanw printf("dec_2100_a500_eisa_intr_establish: non-EDGE on EDGE\n"); 577 1.3.2.2 nathanw return (NULL); 578 1.3.2.2 nathanw } 579 1.3.2.2 nathanw 580 1.3.2.2 nathanw cookie = alpha_shared_intr_establish(tcp->tc_intrtab, irq, 581 1.3.2.2 nathanw type, level, fn, arg, "T2 irq"); 582 1.3.2.2 nathanw 583 1.3.2.2 nathanw if (cookie != NULL && 584 1.3.2.2 nathanw alpha_shared_intr_firstactive(tcp->tc_intrtab, irq)) { 585 1.3.2.2 nathanw scb_set(tcp->tc_vecbase + SCB_IDXTOVEC(irq), 586 1.3.2.2 nathanw dec_2100_a500_iointr, tcp); 587 1.3.2.2 nathanw (*tcp->tc_setlevel)(tcp, eirq, 588 1.3.2.2 nathanw alpha_shared_intr_get_sharetype(tcp->tc_intrtab, 589 1.3.2.2 nathanw irq) == IST_LEVEL); 590 1.3.2.2 nathanw (*tcp->tc_enable_intr)(tcp, irq, 1); 591 1.3.2.2 nathanw } 592 1.3.2.2 nathanw 593 1.3.2.2 nathanw return (cookie); 594 1.3.2.2 nathanw } 595 1.3.2.2 nathanw 596 1.3.2.2 nathanw void 597 1.3.2.2 nathanw dec_2100_a500_eisa_intr_disestablish(void *v, void *cookie) 598 1.3.2.2 nathanw { 599 1.3.2.2 nathanw struct ttwoga_config *tcp = v; 600 1.3.2.2 nathanw struct alpha_shared_intrhand *ih = cookie; 601 1.3.2.2 nathanw int s, irq = ih->ih_num; 602 1.3.2.2 nathanw 603 1.3.2.2 nathanw s = splhigh(); 604 1.3.2.2 nathanw 605 1.3.2.2 nathanw /* Remove it from the link. */ 606 1.3.2.2 nathanw alpha_shared_intr_disestablish(tcp->tc_intrtab, cookie, 607 1.3.2.2 nathanw "T2 irq"); 608 1.3.2.2 nathanw 609 1.3.2.2 nathanw if (alpha_shared_intr_isactive(tcp->tc_intrtab, irq) == 0) { 610 1.3.2.2 nathanw (*tcp->tc_enable_intr)(tcp, irq, 0); 611 1.3.2.2 nathanw alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab, 612 1.3.2.2 nathanw irq, dec_2100_a500_intr_deftype[irq]); 613 1.3.2.2 nathanw scb_free(tcp->tc_vecbase + SCB_IDXTOVEC(irq)); 614 1.3.2.2 nathanw } 615 1.3.2.2 nathanw 616 1.3.2.2 nathanw splx(s); 617 1.3.2.2 nathanw } 618 1.3.2.2 nathanw 619 1.3.2.2 nathanw int 620 1.3.2.2 nathanw dec_2100_a500_eisa_intr_alloc(void *v, int mask, int type, int *eirqp) 621 1.3.2.2 nathanw { 622 1.3.2.2 nathanw 623 1.3.2.2 nathanw /* XXX Not supported right now. */ 624 1.3.2.2 nathanw return (1); 625 1.3.2.2 nathanw } 626 1.3.2.2 nathanw 627 1.3.2.2 nathanw /***************************************************************************** 628 1.3.2.2 nathanw * Interrupt support routines. 629 1.3.2.2 nathanw *****************************************************************************/ 630 1.3.2.2 nathanw 631 1.3.2.2 nathanw #define ICIC_ADDR(tcp, addr) \ 632 1.3.2.2 nathanw do { \ 633 1.3.2.2 nathanw alpha_mb(); \ 634 1.3.2.2 nathanw T2GA((tcp), T2_AIR) = (addr); \ 635 1.3.2.2 nathanw alpha_mb(); \ 636 1.3.2.2 nathanw alpha_mb(); \ 637 1.3.2.2 nathanw (void) T2GA((tcp), T2_AIR); \ 638 1.3.2.2 nathanw alpha_mb(); \ 639 1.3.2.2 nathanw alpha_mb(); \ 640 1.3.2.2 nathanw } while (0) 641 1.3.2.2 nathanw 642 1.3.2.2 nathanw #define ICIC_READ(tcp) T2GA((tcp), T2_DIR) 643 1.3.2.2 nathanw #define ICIC_WRITE(tcp, val) \ 644 1.3.2.2 nathanw do { \ 645 1.3.2.2 nathanw alpha_mb(); \ 646 1.3.2.2 nathanw T2GA((tcp), T2_DIR) = (val); \ 647 1.3.2.2 nathanw alpha_mb(); \ 648 1.3.2.2 nathanw alpha_mb(); \ 649 1.3.2.2 nathanw } while (0) 650 1.3.2.2 nathanw 651 1.3.2.2 nathanw void 652 1.3.2.2 nathanw dec_2100_a500_iointr(void *arg, u_long vec) 653 1.3.2.2 nathanw { 654 1.3.2.2 nathanw struct ttwoga_config *tcp = arg; 655 1.3.2.2 nathanw int irq, rv; 656 1.3.2.2 nathanw 657 1.3.2.2 nathanw irq = SCB_VECTOIDX(vec - tcp->tc_vecbase); 658 1.3.2.2 nathanw 659 1.3.2.2 nathanw rv = alpha_shared_intr_dispatch(tcp->tc_intrtab, irq); 660 1.3.2.2 nathanw (*tcp->tc_eoi)(tcp, irq); 661 1.3.2.2 nathanw if (rv == 0) { 662 1.3.2.2 nathanw alpha_shared_intr_stray(tcp->tc_intrtab, irq, "T2 irq"); 663 1.3.2.2 nathanw if (ALPHA_SHARED_INTR_DISABLE(tcp->tc_intrtab, irq)) 664 1.3.2.2 nathanw (*tcp->tc_enable_intr)(tcp, irq, 0); 665 1.3.2.2 nathanw } 666 1.3.2.2 nathanw } 667 1.3.2.2 nathanw 668 1.3.2.2 nathanw void 669 1.3.2.2 nathanw dec_2100_a500_pic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff) 670 1.3.2.2 nathanw { 671 1.3.2.2 nathanw int pic; 672 1.3.2.2 nathanw u_int8_t bit, mask; 673 1.3.2.2 nathanw 674 1.3.2.2 nathanw pic = irq >> 3; 675 1.3.2.2 nathanw bit = 1 << (irq & 0x7); 676 1.3.2.2 nathanw 677 1.3.2.2 nathanw mask = bus_space_read_1(pic_iot, pic_slave_ioh[pic], 1); 678 1.3.2.2 nathanw if (onoff) 679 1.3.2.2 nathanw mask &= ~bit; 680 1.3.2.2 nathanw else 681 1.3.2.2 nathanw mask |= bit; 682 1.3.2.2 nathanw bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, mask); 683 1.3.2.2 nathanw } 684 1.3.2.2 nathanw 685 1.3.2.2 nathanw void 686 1.3.2.2 nathanw dec_2100_a500_icic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff) 687 1.3.2.2 nathanw { 688 1.3.2.2 nathanw u_int64_t bit, mask; 689 1.3.2.2 nathanw 690 1.3.2.2 nathanw bit = 1UL << irq; 691 1.3.2.2 nathanw 692 1.3.2.2 nathanw ICIC_ADDR(tcp, 0x40); 693 1.3.2.2 nathanw 694 1.3.2.2 nathanw mask = ICIC_READ(tcp); 695 1.3.2.2 nathanw if (onoff) 696 1.3.2.2 nathanw mask &= ~bit; 697 1.3.2.2 nathanw else 698 1.3.2.2 nathanw mask |= bit; 699 1.3.2.2 nathanw ICIC_WRITE(tcp, mask); 700 1.3.2.2 nathanw } 701 1.3.2.2 nathanw 702 1.3.2.2 nathanw void 703 1.3.2.2 nathanw dec_2100_a500_pic_init_intr(struct ttwoga_config *tcp) 704 1.3.2.2 nathanw { 705 1.3.2.2 nathanw static const int picaddr[4] = { 706 1.3.2.2 nathanw 0x536, 0x53a, 0x53c, 0x53e 707 1.3.2.2 nathanw }; 708 1.3.2.2 nathanw int pic; 709 1.3.2.2 nathanw 710 1.3.2.2 nathanw /* 711 1.3.2.2 nathanw * Map the master PIC. 712 1.3.2.2 nathanw */ 713 1.3.2.2 nathanw if (bus_space_map(pic_iot, 0x534, 2, 0, &pic_master_ioh)) 714 1.3.2.2 nathanw panic("dec_2100_a500_pic_init_intr: unable to map master PIC"); 715 1.3.2.2 nathanw 716 1.3.2.2 nathanw /* 717 1.3.2.2 nathanw * Map all slave PICs and mask off the interrupts on them. 718 1.3.2.2 nathanw */ 719 1.3.2.2 nathanw for (pic = 0; pic < 4; pic++) { 720 1.3.2.2 nathanw if (bus_space_map(pic_iot, picaddr[pic], 2, 0, 721 1.3.2.2 nathanw &pic_slave_ioh[pic])) 722 1.3.2.2 nathanw panic("dec_2100_a500_pic_init_intr: unable to map " 723 1.3.2.2 nathanw "slave PIC %d", pic); 724 1.3.2.2 nathanw bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, 0xff); 725 1.3.2.2 nathanw } 726 1.3.2.2 nathanw 727 1.3.2.2 nathanw /* 728 1.3.2.2 nathanw * Map the ELCR registers. 729 1.3.2.2 nathanw */ 730 1.3.2.2 nathanw if (bus_space_map(pic_iot, 0x26, 2, 0, &pic_elcr_ioh)) 731 1.3.2.2 nathanw panic("dec_2100_a500_pic_init_intr: unable to map ELCR " 732 1.3.2.2 nathanw "registers"); 733 1.3.2.2 nathanw } 734 1.3.2.2 nathanw 735 1.3.2.2 nathanw void 736 1.3.2.2 nathanw dec_2100_a500_icic_init_intr(struct ttwoga_config *tcp) 737 1.3.2.2 nathanw { 738 1.3.2.2 nathanw 739 1.3.2.2 nathanw ICIC_ADDR(tcp, 0x40); 740 1.3.2.2 nathanw ICIC_WRITE(tcp, 0xffffffffffffffffUL); 741 1.3.2.2 nathanw } 742 1.3.2.2 nathanw 743 1.3.2.2 nathanw void 744 1.3.2.2 nathanw dec_2100_a500_pic_setlevel(struct ttwoga_config *tcp, int eirq, int level) 745 1.3.2.2 nathanw { 746 1.3.2.2 nathanw int elcr; 747 1.3.2.2 nathanw u_int8_t bit, mask; 748 1.3.2.2 nathanw 749 1.3.2.2 nathanw switch (eirq) { /* EISA IRQ */ 750 1.3.2.2 nathanw case 3: 751 1.3.2.2 nathanw case 4: 752 1.3.2.2 nathanw case 5: 753 1.3.2.2 nathanw case 6: 754 1.3.2.2 nathanw case 7: 755 1.3.2.2 nathanw elcr = 0; 756 1.3.2.2 nathanw bit = 1 << (eirq - 3); 757 1.3.2.2 nathanw break; 758 1.3.2.2 nathanw 759 1.3.2.2 nathanw case 9: 760 1.3.2.2 nathanw case 10: 761 1.3.2.2 nathanw case 11: 762 1.3.2.2 nathanw elcr = 0; 763 1.3.2.2 nathanw bit = 1 << (eirq - 4); 764 1.3.2.2 nathanw break; 765 1.3.2.2 nathanw 766 1.3.2.2 nathanw case 12: 767 1.3.2.2 nathanw elcr = 1; 768 1.3.2.2 nathanw bit = 1 << (eirq - 12); 769 1.3.2.2 nathanw break; 770 1.3.2.2 nathanw 771 1.3.2.2 nathanw case 14: 772 1.3.2.2 nathanw case 15: 773 1.3.2.2 nathanw elcr = 1; 774 1.3.2.2 nathanw bit = 1 << (eirq - 13); 775 1.3.2.2 nathanw break; 776 1.3.2.2 nathanw 777 1.3.2.2 nathanw default: 778 1.3.2.2 nathanw panic("dec_2100_a500_pic_setlevel: bogus EISA IRQ %d", eirq); 779 1.3.2.2 nathanw } 780 1.3.2.2 nathanw 781 1.3.2.2 nathanw mask = bus_space_read_1(pic_iot, pic_elcr_ioh, elcr); 782 1.3.2.2 nathanw if (level) 783 1.3.2.2 nathanw mask |= bit; 784 1.3.2.2 nathanw else 785 1.3.2.2 nathanw mask &= ~bit; 786 1.3.2.2 nathanw bus_space_write_1(pic_iot, pic_elcr_ioh, elcr, mask); 787 1.3.2.2 nathanw } 788 1.3.2.2 nathanw 789 1.3.2.2 nathanw void 790 1.3.2.2 nathanw dec_2100_a500_icic_setlevel(struct ttwoga_config *tcp, int eirq, int level) 791 1.3.2.2 nathanw { 792 1.3.2.2 nathanw u_int64_t bit, mask; 793 1.3.2.2 nathanw 794 1.3.2.2 nathanw switch (eirq) { 795 1.3.2.2 nathanw case 3: 796 1.3.2.2 nathanw case 4: 797 1.3.2.2 nathanw case 5: 798 1.3.2.2 nathanw case 6: 799 1.3.2.2 nathanw case 7: 800 1.3.2.2 nathanw case 9: 801 1.3.2.2 nathanw case 10: 802 1.3.2.2 nathanw case 11: 803 1.3.2.2 nathanw case 12: 804 1.3.2.2 nathanw case 14: 805 1.3.2.2 nathanw case 15: 806 1.3.2.2 nathanw bit = 1UL << (eirq + T2_IRQ_EISA_START); 807 1.3.2.2 nathanw 808 1.3.2.2 nathanw ICIC_ADDR(tcp, 0x50); 809 1.3.2.2 nathanw mask = ICIC_READ(tcp); 810 1.3.2.2 nathanw if (level) 811 1.3.2.2 nathanw mask |= bit; 812 1.3.2.2 nathanw else 813 1.3.2.2 nathanw mask &= ~bit; 814 1.3.2.2 nathanw ICIC_WRITE(tcp, mask); 815 1.3.2.2 nathanw break; 816 1.3.2.2 nathanw 817 1.3.2.2 nathanw default: 818 1.3.2.2 nathanw panic("dec_2100_a500_icic_setlevel: bogus EISA IRQ %d", eirq); 819 1.3.2.2 nathanw } 820 1.3.2.2 nathanw } 821 1.3.2.2 nathanw 822 1.3.2.2 nathanw void 823 1.3.2.2 nathanw dec_2100_a500_pic_eoi(struct ttwoga_config *tcp, int irq) 824 1.3.2.2 nathanw { 825 1.3.2.2 nathanw int pic; 826 1.3.2.2 nathanw 827 1.3.2.2 nathanw if (irq >= 0 && irq <= 7) 828 1.3.2.2 nathanw pic = 0; 829 1.3.2.2 nathanw else if (irq >= 8 && irq <= 15) 830 1.3.2.2 nathanw pic = 1; 831 1.3.2.2 nathanw else if (irq >= 16 && irq <= 23) 832 1.3.2.2 nathanw pic = 2; 833 1.3.2.2 nathanw else 834 1.3.2.2 nathanw pic = 3; 835 1.3.2.2 nathanw 836 1.3.2.2 nathanw bus_space_write_1(pic_iot, pic_slave_ioh[pic], 0, 837 1.3.2.2 nathanw 0xe0 | (irq - (8 * pic))); 838 1.3.2.2 nathanw bus_space_write_1(pic_iot, pic_master_ioh, 0, 839 1.3.2.2 nathanw 0xe0 | pic_slave_to_master[pic]); 840 1.3.2.2 nathanw } 841 1.3.2.2 nathanw 842 1.3.2.2 nathanw void 843 1.3.2.2 nathanw dec_2100_a500_icic_eoi(struct ttwoga_config *tcp, int irq) 844 1.3.2.2 nathanw { 845 1.3.2.2 nathanw 846 1.3.2.2 nathanw T2GA(tcp, T2_VAR) = irq; 847 1.3.2.2 nathanw alpha_mb(); 848 1.3.2.2 nathanw alpha_mb(); /* MAGIC */ 849 1.3.2.2 nathanw } 850
Indexes created Mon Oct 27 20:09:55 GMT 2025