pci_2100_a500.c revision 1.12
1 /* $NetBSD: pci_2100_a500.c,v 1.12 2014/03/21 16:39:29 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 33 34 __KERNEL_RCSID(0, "$NetBSD: pci_2100_a500.c,v 1.12 2014/03/21 16:39:29 christos Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/param.h> 38 #include <sys/time.h> 39 #include <sys/systm.h> 40 #include <sys/errno.h> 41 #include <sys/malloc.h> 42 #include <sys/device.h> 43 #include <sys/syslog.h> 44 45 #include <machine/autoconf.h> 46 47 #include <dev/eisa/eisavar.h> 48 49 #include <dev/pci/pcireg.h> 50 #include <dev/pci/pcivar.h> 51 52 #include <alpha/pci/ttwogareg.h> 53 #include <alpha/pci/ttwogavar.h> 54 #include <alpha/pci/pci_2100_a500.h> 55 56 static bus_space_tag_t pic_iot; 57 static bus_space_handle_t pic_master_ioh; 58 static bus_space_handle_t pic_slave_ioh[4]; 59 static bus_space_handle_t pic_elcr_ioh; 60 61 static const int pic_slave_to_master[4] = { 1, 3, 4, 5 }; 62 63 int dec_2100_a500_pic_intr_map(const struct pci_attach_args *, 64 pci_intr_handle_t *); 65 66 int dec_2100_a500_icic_intr_map(const struct pci_attach_args *, 67 pci_intr_handle_t *); 68 69 const char *dec_2100_a500_intr_string(void *, pci_intr_handle_t, char *, size_t); 70 const struct evcnt *dec_2100_a500_intr_evcnt(void *, pci_intr_handle_t); 71 void *dec_2100_a500_intr_establish(void *, pci_intr_handle_t, 72 int, int (*)(void *), void *); 73 void dec_2100_a500_intr_disestablish(void *, void *); 74 75 int dec_2100_a500_eisa_intr_map(void *, u_int, eisa_intr_handle_t *); 76 const char *dec_2100_a500_eisa_intr_string(void *, int, char *, size_t); 77 const struct evcnt *dec_2100_a500_eisa_intr_evcnt(void *, int); 78 void *dec_2100_a500_eisa_intr_establish(void *, int, int, int, 79 int (*)(void *), void *); 80 void dec_2100_a500_eisa_intr_disestablish(void *, void *); 81 int dec_2100_a500_eisa_intr_alloc(void *, int, int, int *); 82 83 #define PCI_STRAY_MAX 5 84 85 /* 86 * On systems with cascaded 8259s, it's actually 32. Systems which 87 * use the ICIC interrupt logic have 64, however. 88 */ 89 #define SABLE_MAX_IRQ 64 90 #define SABLE_8259_MAX_IRQ 32 91 92 void dec_2100_a500_iointr(void *, u_long); 93 94 void dec_2100_a500_pic_enable_intr(struct ttwoga_config *, int, int); 95 void dec_2100_a500_pic_init_intr(struct ttwoga_config *); 96 void dec_2100_a500_pic_setlevel(struct ttwoga_config *, int, int); 97 void dec_2100_a500_pic_eoi(struct ttwoga_config *, int); 98 99 void dec_2100_a500_icic_enable_intr(struct ttwoga_config *, int, int); 100 void dec_2100_a500_icic_init_intr(struct ttwoga_config *); 101 void dec_2100_a500_icic_setlevel(struct ttwoga_config *, int, int); 102 void dec_2100_a500_icic_eoi(struct ttwoga_config *, int); 103 104 #define T2_IRQ_EISA_START 7 105 #define T2_IRQ_EISA_COUNT 16 106 107 #define T2_IRQ_IS_EISA(irq) \ 108 ((irq) >= T2_IRQ_EISA_START && \ 109 (irq) < (T2_IRQ_EISA_START + T2_IRQ_EISA_COUNT)) 110 111 const int dec_2100_a500_intr_deftype[SABLE_MAX_IRQ] = { 112 IST_LEVEL, /* PCI slot 0 A */ 113 IST_LEVEL, /* on-board SCSI */ 114 IST_LEVEL, /* on-board Ethernet */ 115 IST_EDGE, /* mouse */ 116 IST_LEVEL, /* PCI slot 1 A */ 117 IST_LEVEL, /* PCI slot 2 A */ 118 IST_EDGE, /* keyboard */ 119 IST_EDGE, /* floppy (EISA IRQ 0) */ 120 IST_EDGE, /* serial port 1 (EISA IRQ 1) */ 121 IST_EDGE, /* parallel port (EISA IRQ 2) */ 122 IST_NONE, /* EISA IRQ 3 (edge/level) */ 123 IST_NONE, /* EISA IRQ 4 (edge/level) */ 124 IST_NONE, /* EISA IRQ 5 (edge/level) */ 125 IST_NONE, /* EISA IRQ 6 (edge/level) */ 126 IST_NONE, /* EISA IRQ 7 (edge/level) */ 127 IST_EDGE, /* serial port 0 (EISA IRQ 8) */ 128 IST_NONE, /* EISA IRQ 9 (edge/level) */ 129 IST_NONE, /* EISA IRQ 10 (edge/level) */ 130 IST_NONE, /* EISA IRQ 11 (edge/level) */ 131 IST_NONE, /* EISA IRQ 12 (edge/level) */ 132 IST_LEVEL, /* PCI slot 2 B (EISA IRQ 13 n/c) */ 133 IST_NONE, /* EISA IRQ 14 (edge/level) */ 134 IST_NONE, /* EISA IRQ 15 (edge/level) */ 135 IST_LEVEL, /* I2C (XXX double-check this) */ 136 IST_LEVEL, /* PCI slot 0 B */ 137 IST_LEVEL, /* PCI slot 1 B */ 138 IST_LEVEL, /* PCI slot 0 C */ 139 IST_LEVEL, /* PCI slot 1 C */ 140 IST_LEVEL, /* PCI slot 2 C */ 141 IST_LEVEL, /* PCI slot 0 D */ 142 IST_LEVEL, /* PCI slot 1 D */ 143 IST_LEVEL, /* PCI slot 2 D */ 144 145 /* 146 * These are the PCI interrupts on the T3/T4 systems. See 147 * dec_2100_a500_icic_intr_map() for the mapping. 148 */ 149 IST_LEVEL, 150 IST_LEVEL, 151 IST_LEVEL, 152 IST_LEVEL, 153 IST_LEVEL, 154 IST_LEVEL, 155 IST_LEVEL, 156 IST_LEVEL, 157 IST_LEVEL, 158 IST_LEVEL, 159 IST_LEVEL, 160 IST_LEVEL, 161 IST_LEVEL, 162 IST_LEVEL, 163 IST_LEVEL, 164 IST_LEVEL, 165 IST_LEVEL, 166 IST_LEVEL, 167 IST_LEVEL, 168 IST_LEVEL, 169 IST_LEVEL, 170 IST_LEVEL, 171 IST_LEVEL, 172 IST_LEVEL, 173 IST_LEVEL, 174 IST_LEVEL, 175 IST_LEVEL, 176 IST_LEVEL, 177 IST_LEVEL, 178 IST_LEVEL, 179 IST_LEVEL, 180 IST_LEVEL, 181 }; 182 183 void 184 pci_2100_a500_pickintr(struct ttwoga_config *tcp) 185 { 186 pci_chipset_tag_t pc = &tcp->tc_pc; 187 char *cp; 188 int i; 189 190 pic_iot = &tcp->tc_iot; 191 192 pc->pc_intr_v = tcp; 193 pc->pc_intr_string = dec_2100_a500_intr_string; 194 pc->pc_intr_evcnt = dec_2100_a500_intr_evcnt; 195 pc->pc_intr_establish = dec_2100_a500_intr_establish; 196 pc->pc_intr_disestablish = dec_2100_a500_intr_disestablish; 197 198 /* Not supported on T2. */ 199 pc->pc_pciide_compat_intr_establish = NULL; 200 201 #define PCI_2100_IRQ_STR 8 202 tcp->tc_intrtab = alpha_shared_intr_alloc(SABLE_MAX_IRQ, 203 PCI_2100_IRQ_STR); 204 for (i = 0; i < SABLE_MAX_IRQ; i++) { 205 alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab, 206 i, tcp->tc_hose == 0 ? 207 dec_2100_a500_intr_deftype[i] : IST_LEVEL); 208 alpha_shared_intr_set_maxstrays(tcp->tc_intrtab, 209 i, PCI_STRAY_MAX); 210 211 cp = alpha_shared_intr_string(tcp->tc_intrtab, i); 212 snprintf(cp, PCI_2100_IRQ_STR, "irq %d", T2_IRQ_IS_EISA(i) ? 213 i - T2_IRQ_EISA_START : i); 214 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 215 tcp->tc_intrtab, i), EVCNT_TYPE_INTR, NULL, 216 T2_IRQ_IS_EISA(i) ? "eisa" : "T2", cp); 217 } 218 219 /* 64 16-byte vectors per hose. */ 220 tcp->tc_vecbase = 0x800 + ((64 * 16) * tcp->tc_hose); 221 222 /* 223 * T2 uses a custom layout of cascaded 8259 PICs for interrupt 224 * control. T3 and T4 use a built-in interrupt controller. 225 * 226 * Note that the external PCI bus (Hose 1) always uses 227 * the new interrupt controller. 228 */ 229 if (tcp->tc_rev < TRN_T3 && tcp->tc_hose == 0) { 230 pc->pc_intr_map = dec_2100_a500_pic_intr_map; 231 tcp->tc_enable_intr = dec_2100_a500_pic_enable_intr; 232 tcp->tc_setlevel = dec_2100_a500_pic_setlevel; 233 tcp->tc_eoi = dec_2100_a500_pic_eoi; 234 dec_2100_a500_pic_init_intr(tcp); 235 } else { 236 pc->pc_intr_map = dec_2100_a500_icic_intr_map; 237 tcp->tc_enable_intr = dec_2100_a500_icic_enable_intr; 238 tcp->tc_setlevel = dec_2100_a500_icic_setlevel; 239 tcp->tc_eoi = dec_2100_a500_icic_eoi; 240 dec_2100_a500_icic_init_intr(tcp); 241 } 242 } 243 244 void 245 pci_2100_a500_eisa_pickintr(pci_chipset_tag_t pc, eisa_chipset_tag_t ec) 246 { 247 248 ec->ec_v = pc->pc_intr_v; 249 ec->ec_intr_map = dec_2100_a500_eisa_intr_map; 250 ec->ec_intr_string = dec_2100_a500_eisa_intr_string; 251 ec->ec_intr_evcnt = dec_2100_a500_eisa_intr_evcnt; 252 ec->ec_intr_establish = dec_2100_a500_eisa_intr_establish; 253 ec->ec_intr_disestablish = dec_2100_a500_eisa_intr_disestablish; 254 } 255 256 void 257 pci_2100_a500_isa_pickintr(pci_chipset_tag_t pc, isa_chipset_tag_t ic) 258 { 259 260 ic->ic_v = pc->pc_intr_v; 261 ic->ic_intr_evcnt = dec_2100_a500_eisa_intr_evcnt; 262 ic->ic_intr_establish = dec_2100_a500_eisa_intr_establish; 263 ic->ic_intr_disestablish = dec_2100_a500_eisa_intr_disestablish; 264 ic->ic_intr_alloc = dec_2100_a500_eisa_intr_alloc; 265 } 266 267 /***************************************************************************** 268 * PCI interrupt support. 269 *****************************************************************************/ 270 271 int 272 dec_2100_a500_pic_intr_map(const struct pci_attach_args *pa, 273 pci_intr_handle_t *ihp) 274 { 275 /* 276 * Interrupts in the Sable are even more of a pain than other 277 * Alpha systems. The interrupt logic is made up of 5 8259 278 * PICs, arranged as follows: 279 * 280 * Slave 0 --------------------------------+ 281 * 0 PCI slot 0 A | 282 * 1 on-board SCSI | 283 * 2 on-board Ethernet | 284 * 3 mouse | 285 * 4 PCI slot 1 A | 286 * 5 PCI slot 2 A | 287 * 6 keyboard | 288 * 7 floppy (EISA IRQ 0) | 289 * | 290 * Slave 1 ------------------------+ | Master 291 * 0 serial port 1 (EISA IRQ 1) | | 0 ESC interrupt 292 * 1 parallel port (EISA IRQ 2) | +-- 1 Slave 0 293 * 2 EISA IRQ 3 | 2 reserved 294 * 3 EISA IRQ 4 +---------- 3 Slave 1 295 * 4 EISA IRQ 5 +---------- 4 Slave 2 296 * 5 EISA IRQ 6 | +-- 5 Slave 3 297 * 6 EISA IRQ 7 | | 6 reserved 298 * 7 serial port 0 (EISA IRQ 8) | | 7 n/c 299 * | | 300 * Slave 2 ------------------------+ | 301 * 0 EISA IRQ 9 | 302 * 1 EISA IRQ 10 | 303 * 2 EISA IRQ 11 | 304 * 3 EISA IRQ 12 | 305 * 4 PCI slot 2 B (EISA IRQ 13 n/c) | 306 * 5 EISA IRQ 14 | 307 * 6 EISA IRQ 15 | 308 * 7 I2C | 309 * | 310 * Slave 3 --------------------------------+ 311 * 0 PCI slot 0 B 312 * 1 PCI slot 1 B 313 * 2 PCI slot 0 C 314 * 3 PCI slot 1 C 315 * 4 PCI slot 2 C 316 * 5 PCI slot 0 D 317 * 6 PCI slot 1 D 318 * 7 PCI slot 2 D 319 * 320 * Careful readers will note that the PCEB does not handle ISA 321 * interrupts at all; when ISA interrupts are established, they 322 * must be mapped to Sable interrupts. Thankfully, this is easy 323 * to do. 324 * 325 * The T3 and T4, generally found on Lynx, use a totally different 326 * scheme because they have more PCI interrupts to handle; see below. 327 */ 328 static const int irqmap[9/*device*/][4/*pin*/] = { 329 { 0x02, -1, -1, -1 }, /* 0: on-board Ethernet */ 330 { 0x01, -1, -1, -1 }, /* 1: on-board SCSI */ 331 { -1, -1, -1, -1 }, /* 2: invalid */ 332 { -1, -1, -1, -1 }, /* 3: invalid */ 333 { -1, -1, -1, -1 }, /* 4: invalid */ 334 { -1, -1, -1, -1 }, /* 5: invalid */ 335 { 0x00, 0x18, 0x1a, 0x1d }, /* 6: PCI slot 0 */ 336 { 0x04, 0x19, 0x1b, 0x1e }, /* 7: PCI slot 1 */ 337 { 0x05, 0x14, 0x1c, 0x1f }, /* 8: PCI slot 2 */ 338 }; 339 pcitag_t bustag = pa->pa_intrtag; 340 int buspin = pa->pa_intrpin; 341 pci_chipset_tag_t pc = pa->pa_pc; 342 int device, irq; 343 344 if (buspin == 0) { 345 /* No IRQ used. */ 346 return (1); 347 } 348 349 if (buspin > 4) { 350 printf("dec_2100_a500_pic_intr_map: bad interrupt pin %d\n", 351 buspin); 352 return (1); 353 } 354 355 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 356 if (device > 8) { 357 printf("dec_2100_a500_pic_intr_map: bad device %d\n", 358 device); 359 return (1); 360 } 361 362 irq = irqmap[device][buspin - 1]; 363 if (irq == -1) { 364 printf("dec_2100_a500_pic_intr_map: no mapping for " 365 "device %d pin %d\n", device, buspin); 366 return (1); 367 } 368 *ihp = irq; 369 return (0); 370 } 371 372 int 373 dec_2100_a500_icic_intr_map(const struct pci_attach_args *pa, 374 pci_intr_handle_t *ihp) 375 { 376 pcitag_t bustag = pa->pa_intrtag; 377 int buspin = pa->pa_intrpin; 378 pci_chipset_tag_t pc = pa->pa_pc; 379 int device, irq; 380 381 if (buspin == 0) { 382 /* No IRQ used. */ 383 return (1); 384 } 385 386 if (buspin > 4) { 387 printf("dec_2100_a500_icic_intr_map: bad interrupt in %d\n", 388 buspin); 389 return (1); 390 } 391 392 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 393 switch (device) { 394 case 0: /* on-board Ethernet */ 395 irq = 24; 396 break; 397 398 case 1: /* on-board SCSI */ 399 irq = 28; 400 break; 401 402 case 6: /* PCI slots */ 403 case 7: 404 case 8: 405 irq = (32 + (4 * (device - 6))) + (buspin - 1); 406 break; 407 408 default: 409 printf("dec_2100_a500_icic_intr_map: bad device %d\n", 410 device); 411 return (1); 412 } 413 414 *ihp = irq; 415 return (0); 416 } 417 418 const char * 419 dec_2100_a500_intr_string(void *v, pci_intr_handle_t ih, char *buf, size_t len) 420 { 421 if (ih >= SABLE_MAX_IRQ) 422 panic("%s: bogus T2 IRQ 0x%lx", __func__, ih); 423 424 snprintf(buf, len, "T2 irq %ld", ih); 425 return buf; 426 } 427 428 const struct evcnt * 429 dec_2100_a500_intr_evcnt(void *v, pci_intr_handle_t ih) 430 { 431 struct ttwoga_config *tcp = v; 432 433 if (ih >= SABLE_MAX_IRQ) 434 panic("%s: bogus T2 IRQ 0x%lx", __func__, ih); 435 436 return (alpha_shared_intr_evcnt(tcp->tc_intrtab, ih)); 437 } 438 439 void * 440 dec_2100_a500_intr_establish(void *v, pci_intr_handle_t ih, int level, 441 int (*func)(void *), void *arg) 442 { 443 struct ttwoga_config *tcp = v; 444 void *cookie; 445 446 if (ih >= SABLE_MAX_IRQ) 447 panic("dec_2100_a500_intr_establish: bogus IRQ 0x%lx", 448 ih); 449 450 cookie = alpha_shared_intr_establish(tcp->tc_intrtab, ih, 451 dec_2100_a500_intr_deftype[ih], level, func, arg, "T2 irq"); 452 453 if (cookie != NULL && 454 alpha_shared_intr_firstactive(tcp->tc_intrtab, ih)) { 455 scb_set(tcp->tc_vecbase + SCB_IDXTOVEC(ih), 456 dec_2100_a500_iointr, tcp, level); 457 (*tcp->tc_enable_intr)(tcp, ih, 1); 458 } 459 460 return (cookie); 461 } 462 463 void 464 dec_2100_a500_intr_disestablish(void *v, void *cookie) 465 { 466 struct ttwoga_config *tcp = v; 467 struct alpha_shared_intrhand *ih = cookie; 468 unsigned int irq = ih->ih_num; 469 int s; 470 471 s = splhigh(); 472 473 alpha_shared_intr_disestablish(tcp->tc_intrtab, cookie, 474 "T2 irq"); 475 if (alpha_shared_intr_isactive(tcp->tc_intrtab, irq) == 0) { 476 (*tcp->tc_enable_intr)(tcp, irq, 0); 477 alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab, 478 irq, dec_2100_a500_intr_deftype[irq]); 479 scb_free(tcp->tc_vecbase + SCB_IDXTOVEC(irq)); 480 } 481 482 splx(s); 483 } 484 485 /***************************************************************************** 486 * EISA interrupt support. 487 *****************************************************************************/ 488 489 int 490 dec_2100_a500_eisa_intr_map(void *v, u_int eirq, eisa_intr_handle_t *ihp) 491 { 492 493 if (eirq > 15) { 494 printf("dec_2100_a500_eisa_intr_map: bad EISA IRQ %d\n", 495 eirq); 496 *ihp = -1; 497 return (1); 498 } 499 500 /* 501 * EISA IRQ 13 is not connected. 502 */ 503 if (eirq == 13) { 504 printf("dec_2100_a500_eisa_intr_map: EISA IRQ 13 not " 505 "connected\n"); 506 *ihp = -1; 507 return (1); 508 } 509 510 /* 511 * Don't map to a T2 IRQ here; we must do this when we hook the 512 * interrupt up, since ISA interrupts aren't explicitly translated. 513 */ 514 515 *ihp = eirq; 516 return (0); 517 } 518 519 const char * 520 dec_2100_a500_eisa_intr_string(void *v, int eirq, char *buf, size_t len) 521 { 522 if (eirq > 15 || eirq == 13) 523 panic("%s: bogus EISA IRQ 0x%x", __func__, eirq); 524 525 snprintf(buf, len, "eisa irq %d (T2 irq %d)", eirq, 526 eirq + T2_IRQ_EISA_START); 527 return buf; 528 } 529 530 const struct evcnt * 531 dec_2100_a500_eisa_intr_evcnt(void *v, int eirq) 532 { 533 struct ttwoga_config *tcp = v; 534 535 if (eirq > 15 || eirq == 13) 536 panic("%s: bogus EISA IRQ 0x%x", __func__, eirq); 537 538 return (alpha_shared_intr_evcnt(tcp->tc_intrtab, 539 eirq + T2_IRQ_EISA_START)); 540 } 541 542 void * 543 dec_2100_a500_eisa_intr_establish(void *v, int eirq, int type, int level, 544 int (*fn)(void *), void *arg) 545 { 546 struct ttwoga_config *tcp = v; 547 void *cookie; 548 int irq; 549 550 if (eirq > 15 || type == IST_NONE) 551 panic("dec_2100_a500_eisa_intr_establish: bogus irq or type"); 552 553 if (eirq == 13) { 554 printf("dec_2100_a500_eisa_intr_establish: EISA IRQ 13 not " 555 "connected\n"); 556 return (NULL); 557 } 558 559 irq = eirq + T2_IRQ_EISA_START; 560 561 /* 562 * We can't change the trigger type of some interrupts. Don't allow 563 * level triggers to be hooked up to non-changeable edge triggers. 564 */ 565 if (dec_2100_a500_intr_deftype[irq] == IST_EDGE && type == IST_LEVEL) { 566 printf("dec_2100_a500_eisa_intr_establish: non-EDGE on EDGE\n"); 567 return (NULL); 568 } 569 570 cookie = alpha_shared_intr_establish(tcp->tc_intrtab, irq, 571 type, level, fn, arg, "T2 irq"); 572 573 if (cookie != NULL && 574 alpha_shared_intr_firstactive(tcp->tc_intrtab, irq)) { 575 scb_set(tcp->tc_vecbase + SCB_IDXTOVEC(irq), 576 dec_2100_a500_iointr, tcp, level); 577 (*tcp->tc_setlevel)(tcp, eirq, 578 alpha_shared_intr_get_sharetype(tcp->tc_intrtab, 579 irq) == IST_LEVEL); 580 (*tcp->tc_enable_intr)(tcp, irq, 1); 581 } 582 583 return (cookie); 584 } 585 586 void 587 dec_2100_a500_eisa_intr_disestablish(void *v, void *cookie) 588 { 589 struct ttwoga_config *tcp = v; 590 struct alpha_shared_intrhand *ih = cookie; 591 int s, irq = ih->ih_num; 592 593 s = splhigh(); 594 595 /* Remove it from the link. */ 596 alpha_shared_intr_disestablish(tcp->tc_intrtab, cookie, 597 "T2 irq"); 598 599 if (alpha_shared_intr_isactive(tcp->tc_intrtab, irq) == 0) { 600 (*tcp->tc_enable_intr)(tcp, irq, 0); 601 alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab, 602 irq, dec_2100_a500_intr_deftype[irq]); 603 scb_free(tcp->tc_vecbase + SCB_IDXTOVEC(irq)); 604 } 605 606 splx(s); 607 } 608 609 int 610 dec_2100_a500_eisa_intr_alloc(void *v, int mask, int type, int *eirqp) 611 { 612 613 /* XXX Not supported right now. */ 614 return (1); 615 } 616 617 /***************************************************************************** 618 * Interrupt support routines. 619 *****************************************************************************/ 620 621 #define ICIC_ADDR(tcp, addr) \ 622 do { \ 623 alpha_mb(); \ 624 T2GA((tcp), T2_AIR) = (addr); \ 625 alpha_mb(); \ 626 alpha_mb(); \ 627 (void) T2GA((tcp), T2_AIR); \ 628 alpha_mb(); \ 629 alpha_mb(); \ 630 } while (0) 631 632 #define ICIC_READ(tcp) T2GA((tcp), T2_DIR) 633 #define ICIC_WRITE(tcp, val) \ 634 do { \ 635 alpha_mb(); \ 636 T2GA((tcp), T2_DIR) = (val); \ 637 alpha_mb(); \ 638 alpha_mb(); \ 639 } while (0) 640 641 void 642 dec_2100_a500_iointr(void *arg, u_long vec) 643 { 644 struct ttwoga_config *tcp = arg; 645 int irq, rv; 646 647 irq = SCB_VECTOIDX(vec - tcp->tc_vecbase); 648 649 rv = alpha_shared_intr_dispatch(tcp->tc_intrtab, irq); 650 (*tcp->tc_eoi)(tcp, irq); 651 if (rv == 0) { 652 alpha_shared_intr_stray(tcp->tc_intrtab, irq, "T2 irq"); 653 if (ALPHA_SHARED_INTR_DISABLE(tcp->tc_intrtab, irq)) 654 (*tcp->tc_enable_intr)(tcp, irq, 0); 655 } else 656 alpha_shared_intr_reset_strays(tcp->tc_intrtab, irq); 657 } 658 659 void 660 dec_2100_a500_pic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff) 661 { 662 int pic; 663 uint8_t bit, mask; 664 665 pic = irq >> 3; 666 bit = 1 << (irq & 0x7); 667 668 mask = bus_space_read_1(pic_iot, pic_slave_ioh[pic], 1); 669 if (onoff) 670 mask &= ~bit; 671 else 672 mask |= bit; 673 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, mask); 674 } 675 676 void 677 dec_2100_a500_icic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff) 678 { 679 uint64_t bit, mask; 680 681 bit = 1UL << irq; 682 683 ICIC_ADDR(tcp, 0x40); 684 685 mask = ICIC_READ(tcp); 686 if (onoff) 687 mask &= ~bit; 688 else 689 mask |= bit; 690 ICIC_WRITE(tcp, mask); 691 } 692 693 void 694 dec_2100_a500_pic_init_intr(struct ttwoga_config *tcp) 695 { 696 static const int picaddr[4] = { 697 0x536, 0x53a, 0x53c, 0x53e 698 }; 699 int pic; 700 701 /* 702 * Map the master PIC. 703 */ 704 if (bus_space_map(pic_iot, 0x534, 2, 0, &pic_master_ioh)) 705 panic("dec_2100_a500_pic_init_intr: unable to map master PIC"); 706 707 /* 708 * Map all slave PICs and mask off the interrupts on them. 709 */ 710 for (pic = 0; pic < 4; pic++) { 711 if (bus_space_map(pic_iot, picaddr[pic], 2, 0, 712 &pic_slave_ioh[pic])) 713 panic("dec_2100_a500_pic_init_intr: unable to map " 714 "slave PIC %d", pic); 715 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, 0xff); 716 } 717 718 /* 719 * Map the ELCR registers. 720 */ 721 if (bus_space_map(pic_iot, 0x26, 2, 0, &pic_elcr_ioh)) 722 panic("dec_2100_a500_pic_init_intr: unable to map ELCR " 723 "registers"); 724 } 725 726 void 727 dec_2100_a500_icic_init_intr(struct ttwoga_config *tcp) 728 { 729 730 ICIC_ADDR(tcp, 0x40); 731 ICIC_WRITE(tcp, 0xffffffffffffffffUL); 732 } 733 734 void 735 dec_2100_a500_pic_setlevel(struct ttwoga_config *tcp, int eirq, int level) 736 { 737 int elcr; 738 uint8_t bit, mask; 739 740 switch (eirq) { /* EISA IRQ */ 741 case 3: 742 case 4: 743 case 5: 744 case 6: 745 case 7: 746 elcr = 0; 747 bit = 1 << (eirq - 3); 748 break; 749 750 case 9: 751 case 10: 752 case 11: 753 elcr = 0; 754 bit = 1 << (eirq - 4); 755 break; 756 757 case 12: 758 elcr = 1; 759 bit = 1 << (eirq - 12); 760 break; 761 762 case 14: 763 case 15: 764 elcr = 1; 765 bit = 1 << (eirq - 13); 766 break; 767 768 default: 769 panic("dec_2100_a500_pic_setlevel: bogus EISA IRQ %d", eirq); 770 } 771 772 mask = bus_space_read_1(pic_iot, pic_elcr_ioh, elcr); 773 if (level) 774 mask |= bit; 775 else 776 mask &= ~bit; 777 bus_space_write_1(pic_iot, pic_elcr_ioh, elcr, mask); 778 } 779 780 void 781 dec_2100_a500_icic_setlevel(struct ttwoga_config *tcp, int eirq, int level) 782 { 783 uint64_t bit, mask; 784 785 switch (eirq) { 786 case 3: 787 case 4: 788 case 5: 789 case 6: 790 case 7: 791 case 9: 792 case 10: 793 case 11: 794 case 12: 795 case 14: 796 case 15: 797 bit = 1UL << (eirq + T2_IRQ_EISA_START); 798 799 ICIC_ADDR(tcp, 0x50); 800 mask = ICIC_READ(tcp); 801 if (level) 802 mask |= bit; 803 else 804 mask &= ~bit; 805 ICIC_WRITE(tcp, mask); 806 break; 807 808 default: 809 panic("dec_2100_a500_icic_setlevel: bogus EISA IRQ %d", eirq); 810 } 811 } 812 813 void 814 dec_2100_a500_pic_eoi(struct ttwoga_config *tcp, int irq) 815 { 816 int pic; 817 818 if (irq >= 0 && irq <= 7) 819 pic = 0; 820 else if (irq >= 8 && irq <= 15) 821 pic = 1; 822 else if (irq >= 16 && irq <= 23) 823 pic = 2; 824 else 825 pic = 3; 826 827 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 0, 828 0xe0 | (irq - (8 * pic))); 829 bus_space_write_1(pic_iot, pic_master_ioh, 0, 830 0xe0 | pic_slave_to_master[pic]); 831 } 832 833 void 834 dec_2100_a500_icic_eoi(struct ttwoga_config *tcp, int irq) 835 { 836 837 T2GA(tcp, T2_VAR) = irq; 838 alpha_mb(); 839 alpha_mb(); /* MAGIC */ 840 } 841
Indexes created Wed Oct 01 07:09:59 GMT 2025