pci_2100_a500.c revision 1.14
1 /* $NetBSD: pci_2100_a500.c,v 1.14 2020/09/25 03:40:11 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 33 34 __KERNEL_RCSID(0, "$NetBSD: pci_2100_a500.c,v 1.14 2020/09/25 03:40:11 thorpej Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/param.h> 38 #include <sys/time.h> 39 #include <sys/systm.h> 40 #include <sys/errno.h> 41 #include <sys/malloc.h> 42 #include <sys/device.h> 43 #include <sys/cpu.h> 44 #include <sys/syslog.h> 45 46 #include <machine/autoconf.h> 47 48 #include <dev/eisa/eisavar.h> 49 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcivar.h> 52 53 #include <alpha/pci/ttwogareg.h> 54 #include <alpha/pci/ttwogavar.h> 55 #include <alpha/pci/pci_2100_a500.h> 56 57 static bus_space_tag_t pic_iot; 58 static bus_space_handle_t pic_master_ioh; 59 static bus_space_handle_t pic_slave_ioh[4]; 60 static bus_space_handle_t pic_elcr_ioh; 61 62 static const int pic_slave_to_master[4] = { 1, 3, 4, 5 }; 63 64 static int dec_2100_a500_pic_intr_map(const struct pci_attach_args *, 65 pci_intr_handle_t *); 66 67 static int dec_2100_a500_icic_intr_map(const struct pci_attach_args *, 68 pci_intr_handle_t *); 69 70 static void *dec_2100_a500_intr_establish(pci_chipset_tag_t, 71 pci_intr_handle_t, int, int (*)(void *), void *); 72 static void dec_2100_a500_intr_disestablish(pci_chipset_tag_t, void *); 73 74 static int dec_2100_a500_eisa_intr_map(void *, u_int, 75 eisa_intr_handle_t *); 76 static const char *dec_2100_a500_eisa_intr_string(void *, int, char *, size_t); 77 static const struct evcnt *dec_2100_a500_eisa_intr_evcnt(void *, int); 78 static void *dec_2100_a500_eisa_intr_establish(void *, int, int, int, 79 int (*)(void *), void *); 80 static void dec_2100_a500_eisa_intr_disestablish(void *, void *); 81 static int dec_2100_a500_eisa_intr_alloc(void *, int, int, int *); 82 83 #define PCI_STRAY_MAX 5 84 85 /* 86 * On systems with cascaded 8259s, it's actually 32. Systems which 87 * use the ICIC interrupt logic have 64, however. 88 */ 89 #define SABLE_MAX_IRQ 64 90 #define SABLE_8259_MAX_IRQ 32 91 92 static void dec_2100_a500_iointr(void *, u_long); 93 94 static void dec_2100_a500_pic_enable_intr(struct ttwoga_config *, 95 int, int); 96 static void dec_2100_a500_pic_init_intr(struct ttwoga_config *); 97 static void dec_2100_a500_pic_setlevel(struct ttwoga_config *, int, int); 98 static void dec_2100_a500_pic_eoi(struct ttwoga_config *, int); 99 100 static void dec_2100_a500_icic_enable_intr(struct ttwoga_config *, 101 int, int); 102 static void dec_2100_a500_icic_init_intr(struct ttwoga_config *); 103 static void dec_2100_a500_icic_setlevel(struct ttwoga_config *, int, int); 104 static void dec_2100_a500_icic_eoi(struct ttwoga_config *, int); 105 106 #define T2_IRQ_EISA_START 7 107 #define T2_IRQ_EISA_COUNT 16 108 109 #define T2_IRQ_IS_EISA(irq) \ 110 ((irq) >= T2_IRQ_EISA_START && \ 111 (irq) < (T2_IRQ_EISA_START + T2_IRQ_EISA_COUNT)) 112 113 static const int dec_2100_a500_intr_deftype[SABLE_MAX_IRQ] = { 114 IST_LEVEL, /* PCI slot 0 A */ 115 IST_LEVEL, /* on-board SCSI */ 116 IST_LEVEL, /* on-board Ethernet */ 117 IST_EDGE, /* mouse */ 118 IST_LEVEL, /* PCI slot 1 A */ 119 IST_LEVEL, /* PCI slot 2 A */ 120 IST_EDGE, /* keyboard */ 121 IST_EDGE, /* floppy (EISA IRQ 0) */ 122 IST_EDGE, /* serial port 1 (EISA IRQ 1) */ 123 IST_EDGE, /* parallel port (EISA IRQ 2) */ 124 IST_NONE, /* EISA IRQ 3 (edge/level) */ 125 IST_NONE, /* EISA IRQ 4 (edge/level) */ 126 IST_NONE, /* EISA IRQ 5 (edge/level) */ 127 IST_NONE, /* EISA IRQ 6 (edge/level) */ 128 IST_NONE, /* EISA IRQ 7 (edge/level) */ 129 IST_EDGE, /* serial port 0 (EISA IRQ 8) */ 130 IST_NONE, /* EISA IRQ 9 (edge/level) */ 131 IST_NONE, /* EISA IRQ 10 (edge/level) */ 132 IST_NONE, /* EISA IRQ 11 (edge/level) */ 133 IST_NONE, /* EISA IRQ 12 (edge/level) */ 134 IST_LEVEL, /* PCI slot 2 B (EISA IRQ 13 n/c) */ 135 IST_NONE, /* EISA IRQ 14 (edge/level) */ 136 IST_NONE, /* EISA IRQ 15 (edge/level) */ 137 IST_LEVEL, /* I2C (XXX double-check this) */ 138 IST_LEVEL, /* PCI slot 0 B */ 139 IST_LEVEL, /* PCI slot 1 B */ 140 IST_LEVEL, /* PCI slot 0 C */ 141 IST_LEVEL, /* PCI slot 1 C */ 142 IST_LEVEL, /* PCI slot 2 C */ 143 IST_LEVEL, /* PCI slot 0 D */ 144 IST_LEVEL, /* PCI slot 1 D */ 145 IST_LEVEL, /* PCI slot 2 D */ 146 147 /* 148 * These are the PCI interrupts on the T3/T4 systems. See 149 * dec_2100_a500_icic_intr_map() for the mapping. 150 */ 151 IST_LEVEL, 152 IST_LEVEL, 153 IST_LEVEL, 154 IST_LEVEL, 155 IST_LEVEL, 156 IST_LEVEL, 157 IST_LEVEL, 158 IST_LEVEL, 159 IST_LEVEL, 160 IST_LEVEL, 161 IST_LEVEL, 162 IST_LEVEL, 163 IST_LEVEL, 164 IST_LEVEL, 165 IST_LEVEL, 166 IST_LEVEL, 167 IST_LEVEL, 168 IST_LEVEL, 169 IST_LEVEL, 170 IST_LEVEL, 171 IST_LEVEL, 172 IST_LEVEL, 173 IST_LEVEL, 174 IST_LEVEL, 175 IST_LEVEL, 176 IST_LEVEL, 177 IST_LEVEL, 178 IST_LEVEL, 179 IST_LEVEL, 180 IST_LEVEL, 181 IST_LEVEL, 182 IST_LEVEL, 183 }; 184 185 void 186 pci_2100_a500_pickintr(struct ttwoga_config *tcp) 187 { 188 pci_chipset_tag_t pc = &tcp->tc_pc; 189 char *cp; 190 int i; 191 192 pic_iot = &tcp->tc_iot; 193 194 pc->pc_intr_v = tcp; 195 pc->pc_intr_string = alpha_pci_generic_intr_string; 196 pc->pc_intr_evcnt = alpha_pci_generic_intr_evcnt; 197 pc->pc_intr_establish = dec_2100_a500_intr_establish; 198 pc->pc_intr_disestablish = dec_2100_a500_intr_disestablish; 199 200 /* Not supported on T2. */ 201 pc->pc_pciide_compat_intr_establish = NULL; 202 203 #define PCI_2100_IRQ_STR 8 204 pc->pc_shared_intrs = alpha_shared_intr_alloc(SABLE_MAX_IRQ, 205 PCI_2100_IRQ_STR); 206 207 pc->pc_intr_desc = "T2 irq"; 208 209 /* 64 16-byte vectors per hose. */ 210 pc->pc_vecbase = 0x800 + ((64 * 16) * tcp->tc_hose); 211 pc->pc_nirq = SABLE_MAX_IRQ; 212 213 for (i = 0; i < SABLE_MAX_IRQ; i++) { 214 alpha_shared_intr_set_dfltsharetype(pc->pc_shared_intrs, 215 i, tcp->tc_hose == 0 ? 216 dec_2100_a500_intr_deftype[i] : IST_LEVEL); 217 alpha_shared_intr_set_maxstrays(pc->pc_shared_intrs, 218 i, PCI_STRAY_MAX); 219 220 cp = alpha_shared_intr_string(pc->pc_shared_intrs, i); 221 snprintf(cp, PCI_2100_IRQ_STR, "irq %d", T2_IRQ_IS_EISA(i) ? 222 i - T2_IRQ_EISA_START : i); 223 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 224 pc->pc_shared_intrs, i), EVCNT_TYPE_INTR, NULL, 225 T2_IRQ_IS_EISA(i) ? "eisa" : "T2", cp); 226 } 227 228 /* 229 * T2 uses a custom layout of cascaded 8259 PICs for interrupt 230 * control. T3 and T4 use a built-in interrupt controller. 231 * 232 * Note that the external PCI bus (Hose 1) always uses 233 * the new interrupt controller. 234 */ 235 if (tcp->tc_rev < TRN_T3 && tcp->tc_hose == 0) { 236 pc->pc_intr_map = dec_2100_a500_pic_intr_map; 237 tcp->tc_enable_intr = dec_2100_a500_pic_enable_intr; 238 tcp->tc_setlevel = dec_2100_a500_pic_setlevel; 239 tcp->tc_eoi = dec_2100_a500_pic_eoi; 240 dec_2100_a500_pic_init_intr(tcp); 241 } else { 242 pc->pc_intr_map = dec_2100_a500_icic_intr_map; 243 tcp->tc_enable_intr = dec_2100_a500_icic_enable_intr; 244 tcp->tc_setlevel = dec_2100_a500_icic_setlevel; 245 tcp->tc_eoi = dec_2100_a500_icic_eoi; 246 dec_2100_a500_icic_init_intr(tcp); 247 } 248 } 249 250 void 251 pci_2100_a500_eisa_pickintr(pci_chipset_tag_t pc, eisa_chipset_tag_t ec) 252 { 253 254 ec->ec_v = pc->pc_intr_v; 255 ec->ec_intr_map = dec_2100_a500_eisa_intr_map; 256 ec->ec_intr_string = dec_2100_a500_eisa_intr_string; 257 ec->ec_intr_evcnt = dec_2100_a500_eisa_intr_evcnt; 258 ec->ec_intr_establish = dec_2100_a500_eisa_intr_establish; 259 ec->ec_intr_disestablish = dec_2100_a500_eisa_intr_disestablish; 260 } 261 262 void 263 pci_2100_a500_isa_pickintr(pci_chipset_tag_t pc, isa_chipset_tag_t ic) 264 { 265 266 ic->ic_v = pc->pc_intr_v; 267 ic->ic_intr_evcnt = dec_2100_a500_eisa_intr_evcnt; 268 ic->ic_intr_establish = dec_2100_a500_eisa_intr_establish; 269 ic->ic_intr_disestablish = dec_2100_a500_eisa_intr_disestablish; 270 ic->ic_intr_alloc = dec_2100_a500_eisa_intr_alloc; 271 } 272 273 /***************************************************************************** 274 * PCI interrupt support. 275 *****************************************************************************/ 276 277 static int 278 dec_2100_a500_pic_intr_map(const struct pci_attach_args *pa, 279 pci_intr_handle_t *ihp) 280 { 281 /* 282 * Interrupts in the Sable are even more of a pain than other 283 * Alpha systems. The interrupt logic is made up of 5 8259 284 * PICs, arranged as follows: 285 * 286 * Slave 0 --------------------------------+ 287 * 0 PCI slot 0 A | 288 * 1 on-board SCSI | 289 * 2 on-board Ethernet | 290 * 3 mouse | 291 * 4 PCI slot 1 A | 292 * 5 PCI slot 2 A | 293 * 6 keyboard | 294 * 7 floppy (EISA IRQ 0) | 295 * | 296 * Slave 1 ------------------------+ | Master 297 * 0 serial port 1 (EISA IRQ 1) | | 0 ESC interrupt 298 * 1 parallel port (EISA IRQ 2) | +-- 1 Slave 0 299 * 2 EISA IRQ 3 | 2 reserved 300 * 3 EISA IRQ 4 +---------- 3 Slave 1 301 * 4 EISA IRQ 5 +---------- 4 Slave 2 302 * 5 EISA IRQ 6 | +-- 5 Slave 3 303 * 6 EISA IRQ 7 | | 6 reserved 304 * 7 serial port 0 (EISA IRQ 8) | | 7 n/c 305 * | | 306 * Slave 2 ------------------------+ | 307 * 0 EISA IRQ 9 | 308 * 1 EISA IRQ 10 | 309 * 2 EISA IRQ 11 | 310 * 3 EISA IRQ 12 | 311 * 4 PCI slot 2 B (EISA IRQ 13 n/c) | 312 * 5 EISA IRQ 14 | 313 * 6 EISA IRQ 15 | 314 * 7 I2C | 315 * | 316 * Slave 3 --------------------------------+ 317 * 0 PCI slot 0 B 318 * 1 PCI slot 1 B 319 * 2 PCI slot 0 C 320 * 3 PCI slot 1 C 321 * 4 PCI slot 2 C 322 * 5 PCI slot 0 D 323 * 6 PCI slot 1 D 324 * 7 PCI slot 2 D 325 * 326 * Careful readers will note that the PCEB does not handle ISA 327 * interrupts at all; when ISA interrupts are established, they 328 * must be mapped to Sable interrupts. Thankfully, this is easy 329 * to do. 330 * 331 * The T3 and T4, generally found on Lynx, use a totally different 332 * scheme because they have more PCI interrupts to handle; see below. 333 */ 334 static const int irqmap[9/*device*/][4/*pin*/] = { 335 { 0x02, -1, -1, -1 }, /* 0: on-board Ethernet */ 336 { 0x01, -1, -1, -1 }, /* 1: on-board SCSI */ 337 { -1, -1, -1, -1 }, /* 2: invalid */ 338 { -1, -1, -1, -1 }, /* 3: invalid */ 339 { -1, -1, -1, -1 }, /* 4: invalid */ 340 { -1, -1, -1, -1 }, /* 5: invalid */ 341 { 0x00, 0x18, 0x1a, 0x1d }, /* 6: PCI slot 0 */ 342 { 0x04, 0x19, 0x1b, 0x1e }, /* 7: PCI slot 1 */ 343 { 0x05, 0x14, 0x1c, 0x1f }, /* 8: PCI slot 2 */ 344 }; 345 pcitag_t bustag = pa->pa_intrtag; 346 int buspin = pa->pa_intrpin; 347 pci_chipset_tag_t pc = pa->pa_pc; 348 int device, irq; 349 350 if (buspin == 0) { 351 /* No IRQ used. */ 352 return (1); 353 } 354 355 if (buspin < 0 || buspin > 4) { 356 printf("dec_2100_a500_pic_intr_map: bad interrupt pin %d\n", 357 buspin); 358 return (1); 359 } 360 361 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 362 if (device > 8) { 363 printf("dec_2100_a500_pic_intr_map: bad device %d\n", 364 device); 365 return (1); 366 } 367 368 irq = irqmap[device][buspin - 1]; 369 if (irq == -1) { 370 printf("dec_2100_a500_pic_intr_map: no mapping for " 371 "device %d pin %d\n", device, buspin); 372 return (1); 373 } 374 alpha_pci_intr_handle_init(ihp, irq, 0); 375 return (0); 376 } 377 378 static int 379 dec_2100_a500_icic_intr_map(const struct pci_attach_args *pa, 380 pci_intr_handle_t *ihp) 381 { 382 pcitag_t bustag = pa->pa_intrtag; 383 int buspin = pa->pa_intrpin; 384 pci_chipset_tag_t pc = pa->pa_pc; 385 int device, irq; 386 387 if (buspin == 0) { 388 /* No IRQ used. */ 389 return (1); 390 } 391 392 if (buspin > 4) { 393 printf("dec_2100_a500_icic_intr_map: bad interrupt in %d\n", 394 buspin); 395 return (1); 396 } 397 398 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 399 switch (device) { 400 case 0: /* on-board Ethernet */ 401 irq = 24; 402 break; 403 404 case 1: /* on-board SCSI */ 405 irq = 28; 406 break; 407 408 case 6: /* PCI slots */ 409 case 7: 410 case 8: 411 irq = (32 + (4 * (device - 6))) + (buspin - 1); 412 break; 413 414 default: 415 printf("dec_2100_a500_icic_intr_map: bad device %d\n", 416 device); 417 return (1); 418 } 419 420 alpha_pci_intr_handle_init(ihp, irq, 0); 421 return (0); 422 } 423 424 static void * 425 dec_2100_a500_intr_establish(pci_chipset_tag_t const pc, 426 pci_intr_handle_t const ih, int const level, 427 int (*func)(void *), void *arg) 428 { 429 struct ttwoga_config *tcp = pc->pc_intr_v; 430 void *cookie; 431 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 432 const u_int flags = alpha_pci_intr_handle_get_flags(&ih); 433 434 KASSERT(irq < SABLE_MAX_IRQ); 435 436 cookie = alpha_shared_intr_alloc_intrhand(pc->pc_shared_intrs, irq, 437 dec_2100_a500_intr_deftype[irq], level, flags, func, arg, "T2 irq"); 438 439 if (cookie == NULL) 440 return NULL; 441 442 mutex_enter(&cpu_lock); 443 444 if (! alpha_shared_intr_link(pc->pc_shared_intrs, cookie, "T2 irq")) { 445 mutex_exit(&cpu_lock); 446 alpha_shared_intr_free_intrhand(cookie); 447 return NULL; 448 } 449 450 if (alpha_shared_intr_firstactive(pc->pc_shared_intrs, irq)) { 451 scb_set(pc->pc_vecbase + SCB_IDXTOVEC(irq), 452 dec_2100_a500_iointr, tcp); 453 (*tcp->tc_enable_intr)(tcp, irq, 1); 454 } 455 456 mutex_exit(&cpu_lock); 457 458 return cookie; 459 } 460 461 static void 462 dec_2100_a500_intr_disestablish(pci_chipset_tag_t const pc, void * const cookie) 463 { 464 struct ttwoga_config *tcp = pc->pc_intr_v; 465 struct alpha_shared_intrhand *ih = cookie; 466 unsigned int irq = ih->ih_num; 467 468 mutex_enter(&cpu_lock); 469 470 if (alpha_shared_intr_firstactive(pc->pc_shared_intrs, irq)) { 471 (*tcp->tc_enable_intr)(tcp, irq, 0); 472 alpha_shared_intr_set_dfltsharetype(pc->pc_shared_intrs, 473 irq, dec_2100_a500_intr_deftype[irq]); 474 scb_free(pc->pc_vecbase + SCB_IDXTOVEC(irq)); 475 } 476 477 alpha_shared_intr_unlink(pc->pc_shared_intrs, cookie, "T2 irq"); 478 479 mutex_exit(&cpu_lock); 480 481 alpha_shared_intr_free_intrhand(cookie); 482 } 483 484 /***************************************************************************** 485 * EISA interrupt support. 486 *****************************************************************************/ 487 488 static int 489 dec_2100_a500_eisa_intr_map(void *v, u_int eirq, eisa_intr_handle_t *ihp) 490 { 491 492 if (eirq > 15) { 493 printf("dec_2100_a500_eisa_intr_map: bad EISA IRQ %d\n", 494 eirq); 495 *ihp = -1; 496 return (1); 497 } 498 499 /* 500 * EISA IRQ 13 is not connected. 501 */ 502 if (eirq == 13) { 503 printf("dec_2100_a500_eisa_intr_map: EISA IRQ 13 not " 504 "connected\n"); 505 *ihp = -1; 506 return (1); 507 } 508 509 /* 510 * Don't map to a T2 IRQ here; we must do this when we hook the 511 * interrupt up, since ISA interrupts aren't explicitly translated. 512 */ 513 514 *ihp = eirq; 515 return (0); 516 } 517 518 static const char * 519 dec_2100_a500_eisa_intr_string(void *v, int eirq, char *buf, size_t len) 520 { 521 if (eirq > 15 || eirq == 13) 522 panic("%s: bogus EISA IRQ 0x%x", __func__, eirq); 523 524 snprintf(buf, len, "eisa irq %d (T2 irq %d)", eirq, 525 eirq + T2_IRQ_EISA_START); 526 return buf; 527 } 528 529 static const struct evcnt * 530 dec_2100_a500_eisa_intr_evcnt(void *v, int eirq) 531 { 532 struct ttwoga_config *tcp = v; 533 pci_chipset_tag_t const pc = &tcp->tc_pc; 534 535 if (eirq > 15 || eirq == 13) 536 panic("%s: bogus EISA IRQ 0x%x", __func__, eirq); 537 538 return (alpha_shared_intr_evcnt(pc->pc_shared_intrs, 539 eirq + T2_IRQ_EISA_START)); 540 } 541 542 static void * 543 dec_2100_a500_eisa_intr_establish(void *v, int eirq, int type, int level, 544 int (*fn)(void *), void *arg) 545 { 546 struct ttwoga_config *tcp = v; 547 pci_chipset_tag_t const pc = &tcp->tc_pc; 548 void *cookie; 549 int irq; 550 551 if (eirq > 15 || type == IST_NONE) 552 panic("dec_2100_a500_eisa_intr_establish: bogus irq or type"); 553 554 if (eirq == 13) { 555 printf("dec_2100_a500_eisa_intr_establish: EISA IRQ 13 not " 556 "connected\n"); 557 return (NULL); 558 } 559 560 irq = eirq + T2_IRQ_EISA_START; 561 562 /* 563 * We can't change the trigger type of some interrupts. Don't allow 564 * level triggers to be hooked up to non-changeable edge triggers. 565 */ 566 if (dec_2100_a500_intr_deftype[irq] == IST_EDGE && type == IST_LEVEL) { 567 printf("dec_2100_a500_eisa_intr_establish: non-EDGE on EDGE\n"); 568 return (NULL); 569 } 570 571 cookie = alpha_shared_intr_alloc_intrhand(pc->pc_shared_intrs, irq, 572 type, level, 0, fn, arg, "T2 irq"); 573 574 if (cookie == NULL) 575 return NULL; 576 577 mutex_enter(&cpu_lock); 578 579 if (! alpha_shared_intr_link(pc->pc_shared_intrs, cookie, "T2 irq")) { 580 mutex_exit(&cpu_lock); 581 alpha_shared_intr_free_intrhand(cookie); 582 return NULL; 583 } 584 585 if (alpha_shared_intr_firstactive(pc->pc_shared_intrs, irq)) { 586 scb_set(pc->pc_vecbase + SCB_IDXTOVEC(irq), 587 dec_2100_a500_iointr, tcp); 588 (*tcp->tc_setlevel)(tcp, eirq, 589 alpha_shared_intr_get_sharetype(pc->pc_shared_intrs, 590 irq) == IST_LEVEL); 591 (*tcp->tc_enable_intr)(tcp, irq, 1); 592 } 593 594 mutex_exit(&cpu_lock); 595 596 return cookie; 597 } 598 599 static void 600 dec_2100_a500_eisa_intr_disestablish(void *v, void *cookie) 601 { 602 struct ttwoga_config *tcp = v; 603 pci_chipset_tag_t const pc = &tcp->tc_pc; 604 struct alpha_shared_intrhand *ih = cookie; 605 int irq = ih->ih_num; 606 607 mutex_enter(&cpu_lock); 608 609 if (alpha_shared_intr_firstactive(pc->pc_shared_intrs, irq)) { 610 (*tcp->tc_enable_intr)(tcp, irq, 0); 611 alpha_shared_intr_set_dfltsharetype(pc->pc_shared_intrs, 612 irq, dec_2100_a500_intr_deftype[irq]); 613 scb_free(pc->pc_vecbase + SCB_IDXTOVEC(irq)); 614 } 615 616 /* Remove it from the link. */ 617 alpha_shared_intr_unlink(pc->pc_shared_intrs, cookie, "T2 irq"); 618 619 mutex_exit(&cpu_lock); 620 621 alpha_shared_intr_free_intrhand(cookie); 622 } 623 624 static int 625 dec_2100_a500_eisa_intr_alloc(void *v, int mask, int type, int *eirqp) 626 { 627 628 /* XXX Not supported right now. */ 629 return (1); 630 } 631 632 /***************************************************************************** 633 * Interrupt support routines. 634 *****************************************************************************/ 635 636 #define ICIC_ADDR(tcp, addr) \ 637 do { \ 638 alpha_mb(); \ 639 T2GA((tcp), T2_AIR) = (addr); \ 640 alpha_mb(); \ 641 alpha_mb(); \ 642 (void) T2GA((tcp), T2_AIR); \ 643 alpha_mb(); \ 644 alpha_mb(); \ 645 } while (0) 646 647 #define ICIC_READ(tcp) T2GA((tcp), T2_DIR) 648 #define ICIC_WRITE(tcp, val) \ 649 do { \ 650 alpha_mb(); \ 651 T2GA((tcp), T2_DIR) = (val); \ 652 alpha_mb(); \ 653 alpha_mb(); \ 654 } while (0) 655 656 static void 657 dec_2100_a500_iointr(void *arg, u_long vec) 658 { 659 struct ttwoga_config *tcp = arg; 660 pci_chipset_tag_t const pc = &tcp->tc_pc; 661 int irq, rv; 662 663 irq = SCB_VECTOIDX(vec - pc->pc_vecbase); 664 665 rv = alpha_shared_intr_dispatch(pc->pc_shared_intrs, irq); 666 (*tcp->tc_eoi)(tcp, irq); 667 if (rv == 0) { 668 alpha_shared_intr_stray(pc->pc_shared_intrs, irq, "T2 irq"); 669 if (ALPHA_SHARED_INTR_DISABLE(pc->pc_shared_intrs, irq)) 670 (*tcp->tc_enable_intr)(tcp, irq, 0); 671 } else 672 alpha_shared_intr_reset_strays(pc->pc_shared_intrs, irq); 673 } 674 675 static void 676 dec_2100_a500_pic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff) 677 { 678 int pic; 679 uint8_t bit, mask; 680 681 pic = irq >> 3; 682 bit = 1 << (irq & 0x7); 683 684 mask = bus_space_read_1(pic_iot, pic_slave_ioh[pic], 1); 685 if (onoff) 686 mask &= ~bit; 687 else 688 mask |= bit; 689 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, mask); 690 } 691 692 static void 693 dec_2100_a500_icic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff) 694 { 695 uint64_t bit, mask; 696 697 bit = 1UL << irq; 698 699 ICIC_ADDR(tcp, 0x40); 700 701 mask = ICIC_READ(tcp); 702 if (onoff) 703 mask &= ~bit; 704 else 705 mask |= bit; 706 ICIC_WRITE(tcp, mask); 707 } 708 709 static void 710 dec_2100_a500_pic_init_intr(struct ttwoga_config *tcp) 711 { 712 static const int picaddr[4] = { 713 0x536, 0x53a, 0x53c, 0x53e 714 }; 715 int pic; 716 717 /* 718 * Map the master PIC. 719 */ 720 if (bus_space_map(pic_iot, 0x534, 2, 0, &pic_master_ioh)) 721 panic("dec_2100_a500_pic_init_intr: unable to map master PIC"); 722 723 /* 724 * Map all slave PICs and mask off the interrupts on them. 725 */ 726 for (pic = 0; pic < 4; pic++) { 727 if (bus_space_map(pic_iot, picaddr[pic], 2, 0, 728 &pic_slave_ioh[pic])) 729 panic("dec_2100_a500_pic_init_intr: unable to map " 730 "slave PIC %d", pic); 731 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, 0xff); 732 } 733 734 /* 735 * Map the ELCR registers. 736 */ 737 if (bus_space_map(pic_iot, 0x26, 2, 0, &pic_elcr_ioh)) 738 panic("dec_2100_a500_pic_init_intr: unable to map ELCR " 739 "registers"); 740 } 741 742 static void 743 dec_2100_a500_icic_init_intr(struct ttwoga_config *tcp) 744 { 745 746 ICIC_ADDR(tcp, 0x40); 747 ICIC_WRITE(tcp, 0xffffffffffffffffUL); 748 } 749 750 static void 751 dec_2100_a500_pic_setlevel(struct ttwoga_config *tcp, int eirq, int level) 752 { 753 int elcr; 754 uint8_t bit, mask; 755 756 switch (eirq) { /* EISA IRQ */ 757 case 3: 758 case 4: 759 case 5: 760 case 6: 761 case 7: 762 elcr = 0; 763 bit = 1 << (eirq - 3); 764 break; 765 766 case 9: 767 case 10: 768 case 11: 769 elcr = 0; 770 bit = 1 << (eirq - 4); 771 break; 772 773 case 12: 774 elcr = 1; 775 bit = 1 << (eirq - 12); 776 break; 777 778 case 14: 779 case 15: 780 elcr = 1; 781 bit = 1 << (eirq - 13); 782 break; 783 784 default: 785 panic("dec_2100_a500_pic_setlevel: bogus EISA IRQ %d", eirq); 786 } 787 788 mask = bus_space_read_1(pic_iot, pic_elcr_ioh, elcr); 789 if (level) 790 mask |= bit; 791 else 792 mask &= ~bit; 793 bus_space_write_1(pic_iot, pic_elcr_ioh, elcr, mask); 794 } 795 796 static void 797 dec_2100_a500_icic_setlevel(struct ttwoga_config *tcp, int eirq, int level) 798 { 799 uint64_t bit, mask; 800 801 switch (eirq) { 802 case 3: 803 case 4: 804 case 5: 805 case 6: 806 case 7: 807 case 9: 808 case 10: 809 case 11: 810 case 12: 811 case 14: 812 case 15: 813 bit = 1UL << (eirq + T2_IRQ_EISA_START); 814 815 ICIC_ADDR(tcp, 0x50); 816 mask = ICIC_READ(tcp); 817 if (level) 818 mask |= bit; 819 else 820 mask &= ~bit; 821 ICIC_WRITE(tcp, mask); 822 break; 823 824 default: 825 panic("dec_2100_a500_icic_setlevel: bogus EISA IRQ %d", eirq); 826 } 827 } 828 829 static void 830 dec_2100_a500_pic_eoi(struct ttwoga_config *tcp, int irq) 831 { 832 int pic; 833 834 if (irq >= 0 && irq <= 7) 835 pic = 0; 836 else if (irq >= 8 && irq <= 15) 837 pic = 1; 838 else if (irq >= 16 && irq <= 23) 839 pic = 2; 840 else 841 pic = 3; 842 843 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 0, 844 0xe0 | (irq - (8 * pic))); 845 bus_space_write_1(pic_iot, pic_master_ioh, 0, 846 0xe0 | pic_slave_to_master[pic]); 847 } 848 849 static void 850 dec_2100_a500_icic_eoi(struct ttwoga_config *tcp, int irq) 851 { 852 853 T2GA(tcp, T2_VAR) = irq; 854 alpha_mb(); 855 alpha_mb(); /* MAGIC */ 856 } 857
Indexes created Tue Sep 30 11:09:46 GMT 2025