pci_2100_a500.c revision 1.15
1 /* $NetBSD: pci_2100_a500.c,v 1.15 2021/06/19 16:59:07 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 33 34 __KERNEL_RCSID(0, "$NetBSD: pci_2100_a500.c,v 1.15 2021/06/19 16:59:07 thorpej Exp $"); 35 36 #include <sys/types.h> 37 #include <sys/param.h> 38 #include <sys/time.h> 39 #include <sys/systm.h> 40 #include <sys/errno.h> 41 #include <sys/malloc.h> 42 #include <sys/device.h> 43 #include <sys/cpu.h> 44 #include <sys/syslog.h> 45 46 #include <machine/autoconf.h> 47 #include <machine/rpb.h> 48 49 #include <dev/eisa/eisavar.h> 50 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcivar.h> 53 54 #include <alpha/pci/ttwogareg.h> 55 #include <alpha/pci/ttwogavar.h> 56 #include <alpha/pci/pci_2100_a500.h> 57 58 static bus_space_tag_t pic_iot; 59 static bus_space_handle_t pic_master_ioh; 60 static bus_space_handle_t pic_slave_ioh[4]; 61 static bus_space_handle_t pic_elcr_ioh; 62 63 static const int pic_slave_to_master[4] = { 1, 3, 4, 5 }; 64 65 static int dec_2100_a500_pic_intr_map(const struct pci_attach_args *, 66 pci_intr_handle_t *); 67 68 static int dec_2100_a500_icic_intr_map(const struct pci_attach_args *, 69 pci_intr_handle_t *); 70 71 static void *dec_2100_a500_intr_establish(pci_chipset_tag_t, 72 pci_intr_handle_t, int, int (*)(void *), void *); 73 static void dec_2100_a500_intr_disestablish(pci_chipset_tag_t, void *); 74 75 static int dec_2100_a500_eisa_intr_map(void *, u_int, 76 eisa_intr_handle_t *); 77 static const char *dec_2100_a500_eisa_intr_string(void *, int, char *, size_t); 78 static const struct evcnt *dec_2100_a500_eisa_intr_evcnt(void *, int); 79 static void *dec_2100_a500_eisa_intr_establish(void *, int, int, int, 80 int (*)(void *), void *); 81 static void dec_2100_a500_eisa_intr_disestablish(void *, void *); 82 static int dec_2100_a500_eisa_intr_alloc(void *, int, int, int *); 83 84 #define PCI_STRAY_MAX 5 85 86 /* 87 * On systems with cascaded 8259s, it's actually 32. Systems which 88 * use the ICIC interrupt logic have 64, however. 89 */ 90 #define SABLE_MAX_IRQ 64 91 #define SABLE_8259_MAX_IRQ 32 92 93 static void dec_2100_a500_iointr(void *, u_long); 94 95 static void dec_2100_a500_pic_enable_intr(struct ttwoga_config *, 96 int, int); 97 static void dec_2100_a500_pic_init_intr(struct ttwoga_config *); 98 static void dec_2100_a500_pic_setlevel(struct ttwoga_config *, int, int); 99 static void dec_2100_a500_pic_eoi(struct ttwoga_config *, int); 100 101 static void dec_2100_a500_icic_enable_intr(struct ttwoga_config *, 102 int, int); 103 static void dec_2100_a500_icic_init_intr(struct ttwoga_config *); 104 static void dec_2100_a500_icic_setlevel(struct ttwoga_config *, int, int); 105 static void dec_2100_a500_icic_eoi(struct ttwoga_config *, int); 106 107 #define T2_IRQ_EISA_START 7 108 #define T2_IRQ_EISA_COUNT 16 109 110 #define T2_IRQ_IS_EISA(irq) \ 111 ((irq) >= T2_IRQ_EISA_START && \ 112 (irq) < (T2_IRQ_EISA_START + T2_IRQ_EISA_COUNT)) 113 114 static const int dec_2100_a500_intr_deftype[SABLE_MAX_IRQ] = { 115 IST_LEVEL, /* PCI slot 0 A */ 116 IST_LEVEL, /* on-board SCSI */ 117 IST_LEVEL, /* on-board Ethernet */ 118 IST_EDGE, /* mouse */ 119 IST_LEVEL, /* PCI slot 1 A */ 120 IST_LEVEL, /* PCI slot 2 A */ 121 IST_EDGE, /* keyboard */ 122 IST_EDGE, /* floppy (EISA IRQ 0) */ 123 IST_EDGE, /* serial port 1 (EISA IRQ 1) */ 124 IST_EDGE, /* parallel port (EISA IRQ 2) */ 125 IST_NONE, /* EISA IRQ 3 (edge/level) */ 126 IST_NONE, /* EISA IRQ 4 (edge/level) */ 127 IST_NONE, /* EISA IRQ 5 (edge/level) */ 128 IST_NONE, /* EISA IRQ 6 (edge/level) */ 129 IST_NONE, /* EISA IRQ 7 (edge/level) */ 130 IST_EDGE, /* serial port 0 (EISA IRQ 8) */ 131 IST_NONE, /* EISA IRQ 9 (edge/level) */ 132 IST_NONE, /* EISA IRQ 10 (edge/level) */ 133 IST_NONE, /* EISA IRQ 11 (edge/level) */ 134 IST_NONE, /* EISA IRQ 12 (edge/level) */ 135 IST_LEVEL, /* PCI slot 2 B (EISA IRQ 13 n/c) */ 136 IST_NONE, /* EISA IRQ 14 (edge/level) */ 137 IST_NONE, /* EISA IRQ 15 (edge/level) */ 138 IST_LEVEL, /* I2C (XXX double-check this) */ 139 IST_LEVEL, /* PCI slot 0 B */ 140 IST_LEVEL, /* PCI slot 1 B */ 141 IST_LEVEL, /* PCI slot 0 C */ 142 IST_LEVEL, /* PCI slot 1 C */ 143 IST_LEVEL, /* PCI slot 2 C */ 144 IST_LEVEL, /* PCI slot 0 D */ 145 IST_LEVEL, /* PCI slot 1 D */ 146 IST_LEVEL, /* PCI slot 2 D */ 147 148 /* 149 * These are the PCI interrupts on the T3/T4 systems. See 150 * dec_2100_a500_icic_intr_map() for the mapping. 151 */ 152 IST_LEVEL, 153 IST_LEVEL, 154 IST_LEVEL, 155 IST_LEVEL, 156 IST_LEVEL, 157 IST_LEVEL, 158 IST_LEVEL, 159 IST_LEVEL, 160 IST_LEVEL, 161 IST_LEVEL, 162 IST_LEVEL, 163 IST_LEVEL, 164 IST_LEVEL, 165 IST_LEVEL, 166 IST_LEVEL, 167 IST_LEVEL, 168 IST_LEVEL, 169 IST_LEVEL, 170 IST_LEVEL, 171 IST_LEVEL, 172 IST_LEVEL, 173 IST_LEVEL, 174 IST_LEVEL, 175 IST_LEVEL, 176 IST_LEVEL, 177 IST_LEVEL, 178 IST_LEVEL, 179 IST_LEVEL, 180 IST_LEVEL, 181 IST_LEVEL, 182 IST_LEVEL, 183 IST_LEVEL, 184 }; 185 186 static void 187 pci_2100_a500_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt, 188 pci_chipset_tag_t pc) 189 { 190 struct ttwoga_config *tcp = core; 191 char *cp; 192 int i; 193 194 pic_iot = iot; 195 196 pc->pc_intr_v = core; 197 pc->pc_intr_string = alpha_pci_generic_intr_string; 198 pc->pc_intr_evcnt = alpha_pci_generic_intr_evcnt; 199 pc->pc_intr_establish = dec_2100_a500_intr_establish; 200 pc->pc_intr_disestablish = dec_2100_a500_intr_disestablish; 201 202 /* Not supported on T2. */ 203 pc->pc_pciide_compat_intr_establish = NULL; 204 205 #define PCI_2100_IRQ_STR 8 206 pc->pc_shared_intrs = alpha_shared_intr_alloc(SABLE_MAX_IRQ, 207 PCI_2100_IRQ_STR); 208 209 pc->pc_intr_desc = "T2 irq"; 210 211 /* 64 16-byte vectors per hose. */ 212 pc->pc_vecbase = 0x800 + ((64 * 16) * tcp->tc_hose); 213 pc->pc_nirq = SABLE_MAX_IRQ; 214 215 for (i = 0; i < SABLE_MAX_IRQ; i++) { 216 alpha_shared_intr_set_dfltsharetype(pc->pc_shared_intrs, 217 i, tcp->tc_hose == 0 ? 218 dec_2100_a500_intr_deftype[i] : IST_LEVEL); 219 alpha_shared_intr_set_maxstrays(pc->pc_shared_intrs, 220 i, PCI_STRAY_MAX); 221 222 cp = alpha_shared_intr_string(pc->pc_shared_intrs, i); 223 snprintf(cp, PCI_2100_IRQ_STR, "irq %d", T2_IRQ_IS_EISA(i) ? 224 i - T2_IRQ_EISA_START : i); 225 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 226 pc->pc_shared_intrs, i), EVCNT_TYPE_INTR, NULL, 227 T2_IRQ_IS_EISA(i) ? "eisa" : "T2", cp); 228 } 229 230 /* 231 * T2 uses a custom layout of cascaded 8259 PICs for interrupt 232 * control. T3 and T4 use a built-in interrupt controller. 233 * 234 * Note that the external PCI bus (Hose 1) always uses 235 * the new interrupt controller. 236 */ 237 if (tcp->tc_rev < TRN_T3 && tcp->tc_hose == 0) { 238 pc->pc_intr_map = dec_2100_a500_pic_intr_map; 239 tcp->tc_enable_intr = dec_2100_a500_pic_enable_intr; 240 tcp->tc_setlevel = dec_2100_a500_pic_setlevel; 241 tcp->tc_eoi = dec_2100_a500_pic_eoi; 242 dec_2100_a500_pic_init_intr(tcp); 243 } else { 244 pc->pc_intr_map = dec_2100_a500_icic_intr_map; 245 tcp->tc_enable_intr = dec_2100_a500_icic_enable_intr; 246 tcp->tc_setlevel = dec_2100_a500_icic_setlevel; 247 tcp->tc_eoi = dec_2100_a500_icic_eoi; 248 dec_2100_a500_icic_init_intr(tcp); 249 } 250 } 251 ALPHA_PCI_INTR_INIT(ST_DEC_2100_A500, pci_2100_a500_pickintr) 252 ALPHA_PCI_INTR_INIT(ST_DEC_2100A_A500, pci_2100_a500_pickintr) 253 254 void 255 pci_2100_a500_eisa_pickintr(pci_chipset_tag_t pc, eisa_chipset_tag_t ec) 256 { 257 258 ec->ec_v = pc->pc_intr_v; 259 ec->ec_intr_map = dec_2100_a500_eisa_intr_map; 260 ec->ec_intr_string = dec_2100_a500_eisa_intr_string; 261 ec->ec_intr_evcnt = dec_2100_a500_eisa_intr_evcnt; 262 ec->ec_intr_establish = dec_2100_a500_eisa_intr_establish; 263 ec->ec_intr_disestablish = dec_2100_a500_eisa_intr_disestablish; 264 } 265 266 void 267 pci_2100_a500_isa_pickintr(pci_chipset_tag_t pc, isa_chipset_tag_t ic) 268 { 269 270 ic->ic_v = pc->pc_intr_v; 271 ic->ic_intr_evcnt = dec_2100_a500_eisa_intr_evcnt; 272 ic->ic_intr_establish = dec_2100_a500_eisa_intr_establish; 273 ic->ic_intr_disestablish = dec_2100_a500_eisa_intr_disestablish; 274 ic->ic_intr_alloc = dec_2100_a500_eisa_intr_alloc; 275 } 276 277 /***************************************************************************** 278 * PCI interrupt support. 279 *****************************************************************************/ 280 281 static int 282 dec_2100_a500_pic_intr_map(const struct pci_attach_args *pa, 283 pci_intr_handle_t *ihp) 284 { 285 /* 286 * Interrupts in the Sable are even more of a pain than other 287 * Alpha systems. The interrupt logic is made up of 5 8259 288 * PICs, arranged as follows: 289 * 290 * Slave 0 --------------------------------+ 291 * 0 PCI slot 0 A | 292 * 1 on-board SCSI | 293 * 2 on-board Ethernet | 294 * 3 mouse | 295 * 4 PCI slot 1 A | 296 * 5 PCI slot 2 A | 297 * 6 keyboard | 298 * 7 floppy (EISA IRQ 0) | 299 * | 300 * Slave 1 ------------------------+ | Master 301 * 0 serial port 1 (EISA IRQ 1) | | 0 ESC interrupt 302 * 1 parallel port (EISA IRQ 2) | +-- 1 Slave 0 303 * 2 EISA IRQ 3 | 2 reserved 304 * 3 EISA IRQ 4 +---------- 3 Slave 1 305 * 4 EISA IRQ 5 +---------- 4 Slave 2 306 * 5 EISA IRQ 6 | +-- 5 Slave 3 307 * 6 EISA IRQ 7 | | 6 reserved 308 * 7 serial port 0 (EISA IRQ 8) | | 7 n/c 309 * | | 310 * Slave 2 ------------------------+ | 311 * 0 EISA IRQ 9 | 312 * 1 EISA IRQ 10 | 313 * 2 EISA IRQ 11 | 314 * 3 EISA IRQ 12 | 315 * 4 PCI slot 2 B (EISA IRQ 13 n/c) | 316 * 5 EISA IRQ 14 | 317 * 6 EISA IRQ 15 | 318 * 7 I2C | 319 * | 320 * Slave 3 --------------------------------+ 321 * 0 PCI slot 0 B 322 * 1 PCI slot 1 B 323 * 2 PCI slot 0 C 324 * 3 PCI slot 1 C 325 * 4 PCI slot 2 C 326 * 5 PCI slot 0 D 327 * 6 PCI slot 1 D 328 * 7 PCI slot 2 D 329 * 330 * Careful readers will note that the PCEB does not handle ISA 331 * interrupts at all; when ISA interrupts are established, they 332 * must be mapped to Sable interrupts. Thankfully, this is easy 333 * to do. 334 * 335 * The T3 and T4, generally found on Lynx, use a totally different 336 * scheme because they have more PCI interrupts to handle; see below. 337 */ 338 static const int irqmap[9/*device*/][4/*pin*/] = { 339 { 0x02, -1, -1, -1 }, /* 0: on-board Ethernet */ 340 { 0x01, -1, -1, -1 }, /* 1: on-board SCSI */ 341 { -1, -1, -1, -1 }, /* 2: invalid */ 342 { -1, -1, -1, -1 }, /* 3: invalid */ 343 { -1, -1, -1, -1 }, /* 4: invalid */ 344 { -1, -1, -1, -1 }, /* 5: invalid */ 345 { 0x00, 0x18, 0x1a, 0x1d }, /* 6: PCI slot 0 */ 346 { 0x04, 0x19, 0x1b, 0x1e }, /* 7: PCI slot 1 */ 347 { 0x05, 0x14, 0x1c, 0x1f }, /* 8: PCI slot 2 */ 348 }; 349 pcitag_t bustag = pa->pa_intrtag; 350 int buspin = pa->pa_intrpin; 351 pci_chipset_tag_t pc = pa->pa_pc; 352 int device, irq; 353 354 if (buspin == 0) { 355 /* No IRQ used. */ 356 return (1); 357 } 358 359 if (buspin < 0 || buspin > 4) { 360 printf("dec_2100_a500_pic_intr_map: bad interrupt pin %d\n", 361 buspin); 362 return (1); 363 } 364 365 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 366 if (device > 8) { 367 printf("dec_2100_a500_pic_intr_map: bad device %d\n", 368 device); 369 return (1); 370 } 371 372 irq = irqmap[device][buspin - 1]; 373 if (irq == -1) { 374 printf("dec_2100_a500_pic_intr_map: no mapping for " 375 "device %d pin %d\n", device, buspin); 376 return (1); 377 } 378 alpha_pci_intr_handle_init(ihp, irq, 0); 379 return (0); 380 } 381 382 static int 383 dec_2100_a500_icic_intr_map(const struct pci_attach_args *pa, 384 pci_intr_handle_t *ihp) 385 { 386 pcitag_t bustag = pa->pa_intrtag; 387 int buspin = pa->pa_intrpin; 388 pci_chipset_tag_t pc = pa->pa_pc; 389 int device, irq; 390 391 if (buspin == 0) { 392 /* No IRQ used. */ 393 return (1); 394 } 395 396 if (buspin > 4) { 397 printf("dec_2100_a500_icic_intr_map: bad interrupt in %d\n", 398 buspin); 399 return (1); 400 } 401 402 pci_decompose_tag(pc, bustag, NULL, &device, NULL); 403 switch (device) { 404 case 0: /* on-board Ethernet */ 405 irq = 24; 406 break; 407 408 case 1: /* on-board SCSI */ 409 irq = 28; 410 break; 411 412 case 6: /* PCI slots */ 413 case 7: 414 case 8: 415 irq = (32 + (4 * (device - 6))) + (buspin - 1); 416 break; 417 418 default: 419 printf("dec_2100_a500_icic_intr_map: bad device %d\n", 420 device); 421 return (1); 422 } 423 424 alpha_pci_intr_handle_init(ihp, irq, 0); 425 return (0); 426 } 427 428 static void * 429 dec_2100_a500_intr_establish(pci_chipset_tag_t const pc, 430 pci_intr_handle_t const ih, int const level, 431 int (*func)(void *), void *arg) 432 { 433 struct ttwoga_config *tcp = pc->pc_intr_v; 434 void *cookie; 435 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 436 const u_int flags = alpha_pci_intr_handle_get_flags(&ih); 437 438 KASSERT(irq < SABLE_MAX_IRQ); 439 440 cookie = alpha_shared_intr_alloc_intrhand(pc->pc_shared_intrs, irq, 441 dec_2100_a500_intr_deftype[irq], level, flags, func, arg, "T2 irq"); 442 443 if (cookie == NULL) 444 return NULL; 445 446 mutex_enter(&cpu_lock); 447 448 if (! alpha_shared_intr_link(pc->pc_shared_intrs, cookie, "T2 irq")) { 449 mutex_exit(&cpu_lock); 450 alpha_shared_intr_free_intrhand(cookie); 451 return NULL; 452 } 453 454 if (alpha_shared_intr_firstactive(pc->pc_shared_intrs, irq)) { 455 scb_set(pc->pc_vecbase + SCB_IDXTOVEC(irq), 456 dec_2100_a500_iointr, tcp); 457 (*tcp->tc_enable_intr)(tcp, irq, 1); 458 } 459 460 mutex_exit(&cpu_lock); 461 462 return cookie; 463 } 464 465 static void 466 dec_2100_a500_intr_disestablish(pci_chipset_tag_t const pc, void * const cookie) 467 { 468 struct ttwoga_config *tcp = pc->pc_intr_v; 469 struct alpha_shared_intrhand *ih = cookie; 470 unsigned int irq = ih->ih_num; 471 472 mutex_enter(&cpu_lock); 473 474 if (alpha_shared_intr_firstactive(pc->pc_shared_intrs, irq)) { 475 (*tcp->tc_enable_intr)(tcp, irq, 0); 476 alpha_shared_intr_set_dfltsharetype(pc->pc_shared_intrs, 477 irq, dec_2100_a500_intr_deftype[irq]); 478 scb_free(pc->pc_vecbase + SCB_IDXTOVEC(irq)); 479 } 480 481 alpha_shared_intr_unlink(pc->pc_shared_intrs, cookie, "T2 irq"); 482 483 mutex_exit(&cpu_lock); 484 485 alpha_shared_intr_free_intrhand(cookie); 486 } 487 488 /***************************************************************************** 489 * EISA interrupt support. 490 *****************************************************************************/ 491 492 static int 493 dec_2100_a500_eisa_intr_map(void *v, u_int eirq, eisa_intr_handle_t *ihp) 494 { 495 496 if (eirq > 15) { 497 printf("dec_2100_a500_eisa_intr_map: bad EISA IRQ %d\n", 498 eirq); 499 *ihp = -1; 500 return (1); 501 } 502 503 /* 504 * EISA IRQ 13 is not connected. 505 */ 506 if (eirq == 13) { 507 printf("dec_2100_a500_eisa_intr_map: EISA IRQ 13 not " 508 "connected\n"); 509 *ihp = -1; 510 return (1); 511 } 512 513 /* 514 * Don't map to a T2 IRQ here; we must do this when we hook the 515 * interrupt up, since ISA interrupts aren't explicitly translated. 516 */ 517 518 *ihp = eirq; 519 return (0); 520 } 521 522 static const char * 523 dec_2100_a500_eisa_intr_string(void *v, int eirq, char *buf, size_t len) 524 { 525 if (eirq > 15 || eirq == 13) 526 panic("%s: bogus EISA IRQ 0x%x", __func__, eirq); 527 528 snprintf(buf, len, "eisa irq %d (T2 irq %d)", eirq, 529 eirq + T2_IRQ_EISA_START); 530 return buf; 531 } 532 533 static const struct evcnt * 534 dec_2100_a500_eisa_intr_evcnt(void *v, int eirq) 535 { 536 struct ttwoga_config *tcp = v; 537 pci_chipset_tag_t const pc = &tcp->tc_pc; 538 539 if (eirq > 15 || eirq == 13) 540 panic("%s: bogus EISA IRQ 0x%x", __func__, eirq); 541 542 return (alpha_shared_intr_evcnt(pc->pc_shared_intrs, 543 eirq + T2_IRQ_EISA_START)); 544 } 545 546 static void * 547 dec_2100_a500_eisa_intr_establish(void *v, int eirq, int type, int level, 548 int (*fn)(void *), void *arg) 549 { 550 struct ttwoga_config *tcp = v; 551 pci_chipset_tag_t const pc = &tcp->tc_pc; 552 void *cookie; 553 int irq; 554 555 if (eirq > 15 || type == IST_NONE) 556 panic("dec_2100_a500_eisa_intr_establish: bogus irq or type"); 557 558 if (eirq == 13) { 559 printf("dec_2100_a500_eisa_intr_establish: EISA IRQ 13 not " 560 "connected\n"); 561 return (NULL); 562 } 563 564 irq = eirq + T2_IRQ_EISA_START; 565 566 /* 567 * We can't change the trigger type of some interrupts. Don't allow 568 * level triggers to be hooked up to non-changeable edge triggers. 569 */ 570 if (dec_2100_a500_intr_deftype[irq] == IST_EDGE && type == IST_LEVEL) { 571 printf("dec_2100_a500_eisa_intr_establish: non-EDGE on EDGE\n"); 572 return (NULL); 573 } 574 575 cookie = alpha_shared_intr_alloc_intrhand(pc->pc_shared_intrs, irq, 576 type, level, 0, fn, arg, "T2 irq"); 577 578 if (cookie == NULL) 579 return NULL; 580 581 mutex_enter(&cpu_lock); 582 583 if (! alpha_shared_intr_link(pc->pc_shared_intrs, cookie, "T2 irq")) { 584 mutex_exit(&cpu_lock); 585 alpha_shared_intr_free_intrhand(cookie); 586 return NULL; 587 } 588 589 if (alpha_shared_intr_firstactive(pc->pc_shared_intrs, irq)) { 590 scb_set(pc->pc_vecbase + SCB_IDXTOVEC(irq), 591 dec_2100_a500_iointr, tcp); 592 (*tcp->tc_setlevel)(tcp, eirq, 593 alpha_shared_intr_get_sharetype(pc->pc_shared_intrs, 594 irq) == IST_LEVEL); 595 (*tcp->tc_enable_intr)(tcp, irq, 1); 596 } 597 598 mutex_exit(&cpu_lock); 599 600 return cookie; 601 } 602 603 static void 604 dec_2100_a500_eisa_intr_disestablish(void *v, void *cookie) 605 { 606 struct ttwoga_config *tcp = v; 607 pci_chipset_tag_t const pc = &tcp->tc_pc; 608 struct alpha_shared_intrhand *ih = cookie; 609 int irq = ih->ih_num; 610 611 mutex_enter(&cpu_lock); 612 613 if (alpha_shared_intr_firstactive(pc->pc_shared_intrs, irq)) { 614 (*tcp->tc_enable_intr)(tcp, irq, 0); 615 alpha_shared_intr_set_dfltsharetype(pc->pc_shared_intrs, 616 irq, dec_2100_a500_intr_deftype[irq]); 617 scb_free(pc->pc_vecbase + SCB_IDXTOVEC(irq)); 618 } 619 620 /* Remove it from the link. */ 621 alpha_shared_intr_unlink(pc->pc_shared_intrs, cookie, "T2 irq"); 622 623 mutex_exit(&cpu_lock); 624 625 alpha_shared_intr_free_intrhand(cookie); 626 } 627 628 static int 629 dec_2100_a500_eisa_intr_alloc(void *v, int mask, int type, int *eirqp) 630 { 631 632 /* XXX Not supported right now. */ 633 return (1); 634 } 635 636 /***************************************************************************** 637 * Interrupt support routines. 638 *****************************************************************************/ 639 640 #define ICIC_ADDR(tcp, addr) \ 641 do { \ 642 alpha_mb(); \ 643 T2GA((tcp), T2_AIR) = (addr); \ 644 alpha_mb(); \ 645 alpha_mb(); \ 646 (void) T2GA((tcp), T2_AIR); \ 647 alpha_mb(); \ 648 alpha_mb(); \ 649 } while (0) 650 651 #define ICIC_READ(tcp) T2GA((tcp), T2_DIR) 652 #define ICIC_WRITE(tcp, val) \ 653 do { \ 654 alpha_mb(); \ 655 T2GA((tcp), T2_DIR) = (val); \ 656 alpha_mb(); \ 657 alpha_mb(); \ 658 } while (0) 659 660 static void 661 dec_2100_a500_iointr(void *arg, u_long vec) 662 { 663 struct ttwoga_config *tcp = arg; 664 pci_chipset_tag_t const pc = &tcp->tc_pc; 665 int irq, rv; 666 667 irq = SCB_VECTOIDX(vec - pc->pc_vecbase); 668 669 rv = alpha_shared_intr_dispatch(pc->pc_shared_intrs, irq); 670 (*tcp->tc_eoi)(tcp, irq); 671 if (rv == 0) { 672 alpha_shared_intr_stray(pc->pc_shared_intrs, irq, "T2 irq"); 673 if (ALPHA_SHARED_INTR_DISABLE(pc->pc_shared_intrs, irq)) 674 (*tcp->tc_enable_intr)(tcp, irq, 0); 675 } else 676 alpha_shared_intr_reset_strays(pc->pc_shared_intrs, irq); 677 } 678 679 static void 680 dec_2100_a500_pic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff) 681 { 682 int pic; 683 uint8_t bit, mask; 684 685 pic = irq >> 3; 686 bit = 1 << (irq & 0x7); 687 688 mask = bus_space_read_1(pic_iot, pic_slave_ioh[pic], 1); 689 if (onoff) 690 mask &= ~bit; 691 else 692 mask |= bit; 693 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, mask); 694 } 695 696 static void 697 dec_2100_a500_icic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff) 698 { 699 uint64_t bit, mask; 700 701 bit = 1UL << irq; 702 703 ICIC_ADDR(tcp, 0x40); 704 705 mask = ICIC_READ(tcp); 706 if (onoff) 707 mask &= ~bit; 708 else 709 mask |= bit; 710 ICIC_WRITE(tcp, mask); 711 } 712 713 static void 714 dec_2100_a500_pic_init_intr(struct ttwoga_config *tcp) 715 { 716 static const int picaddr[4] = { 717 0x536, 0x53a, 0x53c, 0x53e 718 }; 719 int pic; 720 721 /* 722 * Map the master PIC. 723 */ 724 if (bus_space_map(pic_iot, 0x534, 2, 0, &pic_master_ioh)) 725 panic("dec_2100_a500_pic_init_intr: unable to map master PIC"); 726 727 /* 728 * Map all slave PICs and mask off the interrupts on them. 729 */ 730 for (pic = 0; pic < 4; pic++) { 731 if (bus_space_map(pic_iot, picaddr[pic], 2, 0, 732 &pic_slave_ioh[pic])) 733 panic("dec_2100_a500_pic_init_intr: unable to map " 734 "slave PIC %d", pic); 735 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, 0xff); 736 } 737 738 /* 739 * Map the ELCR registers. 740 */ 741 if (bus_space_map(pic_iot, 0x26, 2, 0, &pic_elcr_ioh)) 742 panic("dec_2100_a500_pic_init_intr: unable to map ELCR " 743 "registers"); 744 } 745 746 static void 747 dec_2100_a500_icic_init_intr(struct ttwoga_config *tcp) 748 { 749 750 ICIC_ADDR(tcp, 0x40); 751 ICIC_WRITE(tcp, 0xffffffffffffffffUL); 752 } 753 754 static void 755 dec_2100_a500_pic_setlevel(struct ttwoga_config *tcp, int eirq, int level) 756 { 757 int elcr; 758 uint8_t bit, mask; 759 760 switch (eirq) { /* EISA IRQ */ 761 case 3: 762 case 4: 763 case 5: 764 case 6: 765 case 7: 766 elcr = 0; 767 bit = 1 << (eirq - 3); 768 break; 769 770 case 9: 771 case 10: 772 case 11: 773 elcr = 0; 774 bit = 1 << (eirq - 4); 775 break; 776 777 case 12: 778 elcr = 1; 779 bit = 1 << (eirq - 12); 780 break; 781 782 case 14: 783 case 15: 784 elcr = 1; 785 bit = 1 << (eirq - 13); 786 break; 787 788 default: 789 panic("dec_2100_a500_pic_setlevel: bogus EISA IRQ %d", eirq); 790 } 791 792 mask = bus_space_read_1(pic_iot, pic_elcr_ioh, elcr); 793 if (level) 794 mask |= bit; 795 else 796 mask &= ~bit; 797 bus_space_write_1(pic_iot, pic_elcr_ioh, elcr, mask); 798 } 799 800 static void 801 dec_2100_a500_icic_setlevel(struct ttwoga_config *tcp, int eirq, int level) 802 { 803 uint64_t bit, mask; 804 805 switch (eirq) { 806 case 3: 807 case 4: 808 case 5: 809 case 6: 810 case 7: 811 case 9: 812 case 10: 813 case 11: 814 case 12: 815 case 14: 816 case 15: 817 bit = 1UL << (eirq + T2_IRQ_EISA_START); 818 819 ICIC_ADDR(tcp, 0x50); 820 mask = ICIC_READ(tcp); 821 if (level) 822 mask |= bit; 823 else 824 mask &= ~bit; 825 ICIC_WRITE(tcp, mask); 826 break; 827 828 default: 829 panic("dec_2100_a500_icic_setlevel: bogus EISA IRQ %d", eirq); 830 } 831 } 832 833 static void 834 dec_2100_a500_pic_eoi(struct ttwoga_config *tcp, int irq) 835 { 836 int pic; 837 838 if (irq >= 0 && irq <= 7) 839 pic = 0; 840 else if (irq >= 8 && irq <= 15) 841 pic = 1; 842 else if (irq >= 16 && irq <= 23) 843 pic = 2; 844 else 845 pic = 3; 846 847 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 0, 848 0xe0 | (irq - (8 * pic))); 849 bus_space_write_1(pic_iot, pic_master_ioh, 0, 850 0xe0 | pic_slave_to_master[pic]); 851 } 852 853 static void 854 dec_2100_a500_icic_eoi(struct ttwoga_config *tcp, int irq) 855 { 856 857 T2GA(tcp, T2_VAR) = irq; 858 alpha_mb(); 859 alpha_mb(); /* MAGIC */ 860 } 861
Indexes created Wed Oct 01 07:09:59 GMT 2025