pci_2100_a500.c revision 1.2
1 /* $NetBSD: pci_2100_a500.c,v 1.2 2000/12/28 22:59:07 sommerfeld Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 40 41 __KERNEL_RCSID(0, "$NetBSD: pci_2100_a500.c,v 1.2 2000/12/28 22:59:07 sommerfeld Exp $"); 42 43 #include <sys/types.h> 44 #include <sys/param.h> 45 #include <sys/time.h> 46 #include <sys/systm.h> 47 #include <sys/errno.h> 48 #include <sys/malloc.h> 49 #include <sys/device.h> 50 #include <sys/syslog.h> 51 52 #include <machine/autoconf.h> 53 54 #include <dev/eisa/eisavar.h> 55 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcivar.h> 58 59 #include <alpha/pci/ttwogareg.h> 60 #include <alpha/pci/ttwogavar.h> 61 #include <alpha/pci/pci_2100_a500.h> 62 63 static bus_space_tag_t pic_iot; 64 static bus_space_handle_t pic_master_ioh; 65 static bus_space_handle_t pic_slave_ioh[4]; 66 static bus_space_handle_t pic_elcr_ioh; 67 68 static const int pic_slave_to_master[4] = { 1, 3, 4, 5 }; 69 70 int dec_2100_a500_pic_intr_map(struct pci_attach_args *, 71 pci_intr_handle_t *); 72 73 int dec_2100_a500_icic_intr_map(struct pci_attach_args *, 74 pci_intr_handle_t *); 75 76 const char *dec_2100_a500_intr_string(void *, pci_intr_handle_t); 77 const struct evcnt *dec_2100_a500_intr_evcnt(void *, pci_intr_handle_t); 78 void *dec_2100_a500_intr_establish(void *, pci_intr_handle_t, 79 int, int (*)(void *), void *); 80 void dec_2100_a500_intr_disestablish(void *, void *); 81 82 int dec_2100_a500_eisa_intr_map(void *, u_int, eisa_intr_handle_t *); 83 const char *dec_2100_a500_eisa_intr_string(void *, int); 84 const struct evcnt *dec_2100_a500_eisa_intr_evcnt(void *, int); 85 void *dec_2100_a500_eisa_intr_establish(void *, int, int, int, 86 int (*)(void *), void *); 87 void dec_2100_a500_eisa_intr_disestablish(void *, void *); 88 int dec_2100_a500_eisa_intr_alloc(void *, int, int, int *); 89 90 #define PCI_STRAY_MAX 5 91 92 /* 93 * On systems with cascaded 8259s, it's actually 32. Systems which 94 * use the ICIC interrupt logic have 64, however. 95 */ 96 #define SABLE_MAX_IRQ 64 97 #define SABLE_8259_MAX_IRQ 32 98 99 void dec_2100_a500_iointr(void *, u_long); 100 101 void dec_2100_a500_pic_enable_intr(struct ttwoga_config *, int, int); 102 void dec_2100_a500_pic_init_intr(struct ttwoga_config *); 103 void dec_2100_a500_pic_setlevel(struct ttwoga_config *, int, int); 104 void dec_2100_a500_pic_eoi(struct ttwoga_config *, int); 105 106 void dec_2100_a500_icic_enable_intr(struct ttwoga_config *, int, int); 107 void dec_2100_a500_icic_init_intr(struct ttwoga_config *); 108 void dec_2100_a500_icic_setlevel(struct ttwoga_config *, int, int); 109 void dec_2100_a500_icic_eoi(struct ttwoga_config *, int); 110 111 #define T2_IRQ_EISA_START 7 112 #define T2_IRQ_EISA_COUNT 16 113 114 #define T2_IRQ_IS_EISA(irq) \ 115 ((irq) >= T2_IRQ_EISA_START && \ 116 (irq) < (T2_IRQ_EISA_START + T2_IRQ_EISA_COUNT)) 117 118 const int dec_2100_a500_intr_deftype[SABLE_MAX_IRQ] = { 119 IST_LEVEL, /* PCI slot 0 A */ 120 IST_LEVEL, /* on-board SCSI */ 121 IST_LEVEL, /* on-board Ethernet */ 122 IST_EDGE, /* mouse */ 123 IST_LEVEL, /* PCI slot 1 A */ 124 IST_LEVEL, /* PCI slot 2 A */ 125 IST_EDGE, /* keyboard */ 126 IST_EDGE, /* floppy (EISA IRQ 0) */ 127 IST_EDGE, /* serial port 1 (EISA IRQ 1) */ 128 IST_EDGE, /* parallel port (EISA IRQ 2) */ 129 IST_NONE, /* EISA IRQ 3 (edge/level) */ 130 IST_NONE, /* EISA IRQ 4 (edge/level) */ 131 IST_NONE, /* EISA IRQ 5 (edge/level) */ 132 IST_NONE, /* EISA IRQ 6 (edge/level) */ 133 IST_NONE, /* EISA IRQ 7 (edge/level) */ 134 IST_EDGE, /* serial port 0 (EISA IRQ 8) */ 135 IST_NONE, /* EISA IRQ 9 (edge/level) */ 136 IST_NONE, /* EISA IRQ 10 (edge/level) */ 137 IST_NONE, /* EISA IRQ 11 (edge/level) */ 138 IST_NONE, /* EISA IRQ 12 (edge/level) */ 139 IST_LEVEL, /* PCI slot 2 B (EISA IRQ 13 n/c) */ 140 IST_NONE, /* EISA IRQ 14 (edge/level) */ 141 IST_NONE, /* EISA IRQ 15 (edge/level) */ 142 IST_LEVEL, /* I2C (XXX double-check this) */ 143 IST_LEVEL, /* PCI slot 0 B */ 144 IST_LEVEL, /* PCI slot 1 B */ 145 IST_LEVEL, /* PCI slot 0 C */ 146 IST_LEVEL, /* PCI slot 1 C */ 147 IST_LEVEL, /* PCI slot 2 C */ 148 IST_LEVEL, /* PCI slot 0 D */ 149 IST_LEVEL, /* PCI slot 1 D */ 150 IST_LEVEL, /* PCI slot 2 D */ 151 152 /* 153 * These are the PCI interrupts on the T3/T4 systems. See 154 * dec_2100_a500_icic_intr_map() for the mapping. 155 */ 156 IST_LEVEL, 157 IST_LEVEL, 158 IST_LEVEL, 159 IST_LEVEL, 160 IST_LEVEL, 161 IST_LEVEL, 162 IST_LEVEL, 163 IST_LEVEL, 164 IST_LEVEL, 165 IST_LEVEL, 166 IST_LEVEL, 167 IST_LEVEL, 168 IST_LEVEL, 169 IST_LEVEL, 170 IST_LEVEL, 171 IST_LEVEL, 172 IST_LEVEL, 173 IST_LEVEL, 174 IST_LEVEL, 175 IST_LEVEL, 176 IST_LEVEL, 177 IST_LEVEL, 178 IST_LEVEL, 179 IST_LEVEL, 180 IST_LEVEL, 181 IST_LEVEL, 182 IST_LEVEL, 183 IST_LEVEL, 184 IST_LEVEL, 185 IST_LEVEL, 186 IST_LEVEL, 187 IST_LEVEL, 188 }; 189 190 void 191 pci_2100_a500_pickintr(struct ttwoga_config *tcp) 192 { 193 pci_chipset_tag_t pc = &tcp->tc_pc; 194 char *cp; 195 int i; 196 197 pic_iot = &tcp->tc_iot; 198 199 pc->pc_intr_v = tcp; 200 pc->pc_intr_string = dec_2100_a500_intr_string; 201 pc->pc_intr_evcnt = dec_2100_a500_intr_evcnt; 202 pc->pc_intr_establish = dec_2100_a500_intr_establish; 203 pc->pc_intr_disestablish = dec_2100_a500_intr_disestablish; 204 205 /* Not supported on T2. */ 206 pc->pc_pciide_compat_intr_establish = NULL; 207 208 tcp->tc_intrtab = alpha_shared_intr_alloc(SABLE_MAX_IRQ, 8); 209 for (i = 0; i < SABLE_MAX_IRQ; i++) { 210 alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab, 211 i, tcp->tc_hose == 0 ? 212 dec_2100_a500_intr_deftype[i] : IST_LEVEL); 213 alpha_shared_intr_set_maxstrays(tcp->tc_intrtab, 214 i, PCI_STRAY_MAX); 215 216 cp = alpha_shared_intr_string(tcp->tc_intrtab, i); 217 sprintf(cp, "irq %d", T2_IRQ_IS_EISA(i) ? 218 i - T2_IRQ_EISA_START : i); 219 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 220 tcp->tc_intrtab, i), EVCNT_TYPE_INTR, NULL, 221 T2_IRQ_IS_EISA(i) ? "eisa" : "T2", cp); 222 } 223 224 /* 225 * T2 uses a custom layout of cascaded 8259 PICs for interrupt 226 * control. T3 and T4 use a built-in interrupt controller. 227 * 228 * Note that the external PCI bus (Hose 1) always uses 229 * the new interrupt controller. 230 */ 231 if (tcp->tc_rev < TRN_T3 && tcp->tc_hose == 0) { 232 pc->pc_intr_map = dec_2100_a500_pic_intr_map; 233 tcp->tc_enable_intr = dec_2100_a500_pic_enable_intr; 234 tcp->tc_setlevel = dec_2100_a500_pic_setlevel; 235 tcp->tc_eoi = dec_2100_a500_pic_eoi; 236 dec_2100_a500_pic_init_intr(tcp); 237 } else { 238 pc->pc_intr_map = dec_2100_a500_icic_intr_map; 239 tcp->tc_enable_intr = dec_2100_a500_icic_enable_intr; 240 tcp->tc_setlevel = dec_2100_a500_icic_setlevel; 241 tcp->tc_eoi = dec_2100_a500_icic_eoi; 242 dec_2100_a500_icic_init_intr(tcp); 243 } 244 245 set_iointr(dec_2100_a500_iointr); 246 } 247 248 void 249 pci_2100_a500_eisa_pickintr(pci_chipset_tag_t pc, eisa_chipset_tag_t ec) 250 { 251 252 ec->ec_v = pc->pc_intr_v; 253 ec->ec_intr_map = dec_2100_a500_eisa_intr_map; 254 ec->ec_intr_string = dec_2100_a500_eisa_intr_string; 255 ec->ec_intr_evcnt = dec_2100_a500_eisa_intr_evcnt; 256 ec->ec_intr_establish = dec_2100_a500_eisa_intr_establish; 257 ec->ec_intr_disestablish = dec_2100_a500_eisa_intr_disestablish; 258 } 259 260 void 261 pci_2100_a500_isa_pickintr(pci_chipset_tag_t pc, isa_chipset_tag_t ic) 262 { 263 264 ic->ic_v = pc->pc_intr_v; 265 ic->ic_intr_evcnt = dec_2100_a500_eisa_intr_evcnt; 266 ic->ic_intr_establish = dec_2100_a500_eisa_intr_establish; 267 ic->ic_intr_disestablish = dec_2100_a500_eisa_intr_disestablish; 268 ic->ic_intr_alloc = dec_2100_a500_eisa_intr_alloc; 269 } 270 271 /***************************************************************************** 272 * PCI interrupt support. 273 *****************************************************************************/ 274 275 int 276 dec_2100_a500_pic_intr_map(struct pci_attach_args *pa, 277 pci_intr_handle_t *ihp) 278 { 279 /* 280 * Interrupts in the Sable are even more of a pain than other 281 * Alpha systems. The interrupt logic is made up of 5 8259 282 * PICs, arranged as follows: 283 * 284 * Slave 0 --------------------------------+ 285 * 0 PCI slot 0 A | 286 * 1 on-board SCSI | 287 * 2 on-board Ethernet | 288 * 3 mouse | 289 * 4 PCI slot 1 A | 290 * 5 PCI slot 2 A | 291 * 6 keyboard | 292 * 7 floppy (EISA IRQ 0) | 293 * | 294 * Slave 1 ------------------------+ | Master 295 * 0 serial port 1 (EISA IRQ 1) | | 0 ESC interrupt 296 * 1 parallel port (EISA IRQ 2) | +-- 1 Slave 0 297 * 2 EISA IRQ 3 | 2 reserved 298 * 3 EISA IRQ 4 +---------- 3 Slave 1 299 * 4 EISA IRQ 5 +---------- 4 Slave 2 300 * 5 EISA IRQ 6 | +-- 5 Slave 3 301 * 6 EISA IRQ 7 | | 6 reserved 302 * 7 serial port 0 (EISA IRQ 8) | | 7 n/c 303 * | | 304 * Slave 2 ------------------------+ | 305 * 0 EISA IRQ 9 | 306 * 1 EISA IRQ 10 | 307 * 2 EISA IRQ 11 | 308 * 3 EISA IRQ 12 | 309 * 4 PCI slot 2 B (EISA IRQ 13 n/c) | 310 * 5 EISA IRQ 14 | 311 * 6 EISA IRQ 15 | 312 * 7 I2C | 313 * | 314 * Slave 3 --------------------------------+ 315 * 0 PCI slot 0 B 316 * 1 PCI slot 1 B 317 * 2 PCI slot 0 C 318 * 3 PCI slot 1 C 319 * 4 PCI slot 2 C 320 * 5 PCI slot 0 D 321 * 6 PCI slot 1 D 322 * 7 PCI slot 2 D 323 * 324 * Careful readers will note that the PCEB does not handle ISA 325 * interrupts at all; when ISA interrupts are established, they 326 * must be mapped to Sable interrupts. Thankfully, this is easy 327 * to do. 328 * 329 * The T3 and T4, generally found on Lynx, use a totally different 330 * scheme because they have more PCI interrupts to handle; see below. 331 */ 332 static const int irqmap[9/*device*/][4/*pin*/] = { 333 { 0x02, -1, -1, -1 }, /* 0: on-board Ethernet */ 334 { 0x01, -1, -1, -1 }, /* 1: on-board SCSI */ 335 { -1, -1, -1, -1 }, /* 2: invalid */ 336 { -1, -1, -1, -1 }, /* 3: invalid */ 337 { -1, -1, -1, -1 }, /* 4: invalid */ 338 { -1, -1, -1, -1 }, /* 5: invalid */ 339 { 0x00, 0x18, 0x1a, 0x1d }, /* 6: PCI slot 0 */ 340 { 0x04, 0x19, 0x1b, 0x1e }, /* 7: PCI slot 1 */ 341 { 0x05, 0x14, 0x1c, 0x1f }, /* 8: PCI slot 2 */ 342 }; 343 pcitag_t bustag = pa->pa_intrtag; 344 int buspin = pa->pa_intrpin; 345 pci_chipset_tag_t pc = pa->pa_pc; 346 int device, irq; 347 348 if (buspin == 0) { 349 /* No IRQ used. */ 350 return (1); 351 } 352 353 if (buspin > 4) { 354 printf("dec_2100_a500_pic_intr_map: bad interrupt pin %d\n", 355 buspin); 356 return (1); 357 } 358 359 alpha_pci_decompose_tag(pc, bustag, NULL, &device, NULL); 360 if (device > 8) { 361 printf("dec_2100_a500_pic_intr_map: bad device %d\n", 362 device); 363 return (1); 364 } 365 366 irq = irqmap[device][buspin - 1]; 367 if (irq == -1) { 368 printf("dec_2100_a500_pic_intr_map: no mapping for " 369 "device %d pin %d\n", device, buspin); 370 return (1); 371 } 372 *ihp = irq; 373 return (0); 374 } 375 376 int 377 dec_2100_a500_icic_intr_map(struct pci_attach_args *pa, pci_intr_handle_t *ihp) 378 { 379 pcitag_t bustag = pa->pa_intrtag; 380 int buspin = pa->pa_intrpin; 381 pci_chipset_tag_t pc = pa->pa_pc; 382 int device, irq; 383 384 if (buspin == 0) { 385 /* No IRQ used. */ 386 return (1); 387 } 388 389 if (buspin > 4) { 390 printf("dec_2100_a500_icic_intr_map: bad interrupt in %d\n", 391 buspin); 392 return (1); 393 } 394 395 alpha_pci_decompose_tag(pc, bustag, NULL, &device, NULL); 396 switch (device) { 397 case 0: /* on-board Ethernet */ 398 irq = 24; 399 break; 400 401 case 1: /* on-board SCSI */ 402 irq = 28; 403 break; 404 405 case 6: /* PCI slots */ 406 case 7: 407 case 8: 408 irq = (32 + (4 * (device - 6))) + (buspin - 1); 409 break; 410 411 default: 412 printf("dec_2100_a500_icic_intr_map: bad device %d\n", 413 device); 414 return (1); 415 } 416 417 *ihp = irq; 418 return (0); 419 } 420 421 const char * 422 dec_2100_a500_intr_string(void *v, pci_intr_handle_t ih) 423 { 424 static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 425 426 if (ih >= SABLE_MAX_IRQ) 427 panic("dec_2100_a500_intr_string: bogus T2 IRQ 0x%lx\n", ih); 428 429 sprintf(irqstr, "T2 irq %ld", ih); 430 return (irqstr); 431 } 432 433 const struct evcnt * 434 dec_2100_a500_intr_evcnt(void *v, pci_intr_handle_t ih) 435 { 436 struct ttwoga_config *tcp = v; 437 438 if (ih >= SABLE_MAX_IRQ) 439 panic("dec_2100_a500_intr_evcnt: bogus T2 IRQ 0x%lx\n", ih); 440 441 return (alpha_shared_intr_evcnt(tcp->tc_intrtab, ih)); 442 } 443 444 void * 445 dec_2100_a500_intr_establish(void *v, pci_intr_handle_t ih, int level, 446 int (*func)(void *), void *arg) 447 { 448 struct ttwoga_config *tcp = v; 449 void *cookie; 450 451 if (ih >= SABLE_MAX_IRQ) 452 panic("dec_2100_a500_intr_establish: bogus IRQ 0x%lx\n", 453 ih); 454 455 cookie = alpha_shared_intr_establish(tcp->tc_intrtab, ih, 456 dec_2100_a500_intr_deftype[ih], level, func, arg, "T2 irq"); 457 458 if (cookie != NULL && 459 alpha_shared_intr_isactive(tcp->tc_intrtab, ih)) 460 (*tcp->tc_enable_intr)(tcp, ih, 1); 461 462 return (cookie); 463 } 464 465 void 466 dec_2100_a500_intr_disestablish(void *v, void *cookie) 467 { 468 struct ttwoga_config *tcp = v; 469 struct alpha_shared_intrhand *ih = cookie; 470 unsigned int irq = ih->ih_num; 471 int s; 472 473 s = splhigh(); 474 475 alpha_shared_intr_disestablish(tcp->tc_intrtab, cookie, 476 "T2 irq"); 477 if (alpha_shared_intr_isactive(tcp->tc_intrtab, irq) == 0) { 478 (*tcp->tc_enable_intr)(tcp, irq, 0); 479 alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab, 480 irq, dec_2100_a500_intr_deftype[irq]); 481 } 482 483 splx(s); 484 } 485 486 /***************************************************************************** 487 * EISA interrupt support. 488 *****************************************************************************/ 489 490 int 491 dec_2100_a500_eisa_intr_map(void *v, u_int eirq, eisa_intr_handle_t *ihp) 492 { 493 494 if (eirq > 15) { 495 printf("dec_2100_a500_eisa_intr_map: bad EISA IRQ %d\n", 496 eirq); 497 *ihp = -1; 498 return (1); 499 } 500 501 /* 502 * EISA IRQ 13 is not connected. 503 */ 504 if (eirq == 13) { 505 printf("dec_2100_a500_eisa_intr_map: EISA IRQ 13 not " 506 "connected\n"); 507 *ihp = -1; 508 return (1); 509 } 510 511 /* 512 * Don't map to a T2 IRQ here; we must do this when we hook the 513 * interrupt up, since ISA interrupts aren't explicitly translated. 514 */ 515 516 *ihp = eirq; 517 return (0); 518 } 519 520 const char * 521 dec_2100_a500_eisa_intr_string(void *v, int eirq) 522 { 523 static char irqstr[32]; 524 525 if (eirq > 15 || eirq == 13) 526 panic("dec_2100_a500_eisa_intr_string: bogus EISA IRQ 0x%x\n", 527 eirq); 528 529 sprintf(irqstr, "eisa irq %d (T2 irq %d)", eirq, 530 eirq + T2_IRQ_EISA_START); 531 return (irqstr); 532 } 533 534 const struct evcnt * 535 dec_2100_a500_eisa_intr_evcnt(void *v, int eirq) 536 { 537 struct ttwoga_config *tcp = v; 538 539 if (eirq > 15 || eirq == 13) 540 panic("dec_2100_a500_eisa_intr_evcnt: bogus EISA IRQ 0x%x\n", 541 eirq); 542 543 return (alpha_shared_intr_evcnt(tcp->tc_intrtab, 544 eirq + T2_IRQ_EISA_START)); 545 } 546 547 void * 548 dec_2100_a500_eisa_intr_establish(void *v, int eirq, int type, int level, 549 int (*fn)(void *), void *arg) 550 { 551 struct ttwoga_config *tcp = v; 552 void *cookie; 553 int irq; 554 555 if (eirq > 15 || type == IST_NONE) 556 panic("dec_2100_a500_eisa_intr_establish: bogus irq or type"); 557 558 if (eirq == 13) { 559 printf("dec_2100_a500_eisa_intr_establish: EISA IRQ 13 not " 560 "connected\n"); 561 return (NULL); 562 } 563 564 irq = eirq + T2_IRQ_EISA_START; 565 566 /* 567 * We can't change the trigger type of some interrupts. Don't allow 568 * level triggers to be hooked up to non-changeable edge triggers. 569 */ 570 if (dec_2100_a500_intr_deftype[irq] == IST_EDGE && type == IST_LEVEL) { 571 printf("dec_2100_a500_eisa_intr_establish: non-EDGE on EDGE\n"); 572 return (NULL); 573 } 574 575 cookie = alpha_shared_intr_establish(tcp->tc_intrtab, irq, 576 type, level, fn, arg, "T2 irq"); 577 578 if (cookie != NULL && 579 alpha_shared_intr_isactive(tcp->tc_intrtab, irq)) { 580 (*tcp->tc_setlevel)(tcp, eirq, 581 alpha_shared_intr_get_sharetype(tcp->tc_intrtab, 582 irq) == IST_LEVEL); 583 (*tcp->tc_enable_intr)(tcp, irq, 1); 584 } 585 586 return (cookie); 587 } 588 589 void 590 dec_2100_a500_eisa_intr_disestablish(void *v, void *cookie) 591 { 592 struct ttwoga_config *tcp = v; 593 struct alpha_shared_intrhand *ih = cookie; 594 int s, irq = ih->ih_num; 595 596 s = splhigh(); 597 598 /* Remove it from the link. */ 599 alpha_shared_intr_disestablish(tcp->tc_intrtab, cookie, 600 "T2 irq"); 601 602 if (alpha_shared_intr_isactive(tcp->tc_intrtab, irq) == 0) { 603 (*tcp->tc_enable_intr)(tcp, irq, 0); 604 alpha_shared_intr_set_dfltsharetype(tcp->tc_intrtab, 605 irq, dec_2100_a500_intr_deftype[irq]); 606 } 607 608 splx(s); 609 } 610 611 int 612 dec_2100_a500_eisa_intr_alloc(void *v, int mask, int type, int *eirqp) 613 { 614 615 /* XXX Not supported right now. */ 616 return (1); 617 } 618 619 /***************************************************************************** 620 * Interrupt support routines. 621 *****************************************************************************/ 622 623 #define ICIC_ADDR(tcp, addr) \ 624 do { \ 625 alpha_mb(); \ 626 T2GA((tcp), T2_AIR) = (addr); \ 627 alpha_mb(); \ 628 alpha_mb(); \ 629 (void) T2GA((tcp), T2_AIR); \ 630 alpha_mb(); \ 631 alpha_mb(); \ 632 } while (0) 633 634 #define ICIC_READ(tcp) T2GA((tcp), T2_DIR) 635 #define ICIC_WRITE(tcp, val) \ 636 do { \ 637 alpha_mb(); \ 638 T2GA((tcp), T2_DIR) = (val); \ 639 alpha_mb(); \ 640 alpha_mb(); \ 641 } while (0) 642 643 void 644 dec_2100_a500_iointr(void *framep, u_long vec) 645 { 646 struct ttwoga_config *tcp; 647 int irq, hose, vecbase, rv; 648 649 if (vec >= 0xc00) { 650 hose = 1; 651 vecbase = 0xc00; 652 } else if (vec >= 0x800) { 653 hose = 0; 654 vecbase = 0x800; 655 } else 656 panic("dec_2100_a500_iointr: weird vec 0x%lx\n", vec); 657 658 tcp = &ttwoga_configuration[hose]; 659 660 if (vec >= vecbase + (SABLE_MAX_IRQ << 4)) 661 panic("dec_2100_a500_iointr: vec 0x%lx out of range\n", 662 vec); 663 irq = (vec - vecbase) >> 4; 664 rv = alpha_shared_intr_dispatch(tcp->tc_intrtab, irq); 665 (*tcp->tc_eoi)(tcp, irq); 666 if (rv == 0) { 667 alpha_shared_intr_stray(tcp->tc_intrtab, irq, "T2 irq"); 668 if (ALPHA_SHARED_INTR_DISABLE(tcp->tc_intrtab, irq)) 669 (*tcp->tc_enable_intr)(tcp, irq, 0); 670 } 671 } 672 673 void 674 dec_2100_a500_pic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff) 675 { 676 int pic; 677 u_int8_t bit, mask; 678 679 pic = irq >> 3; 680 bit = 1 << (irq & 0x7); 681 682 mask = bus_space_read_1(pic_iot, pic_slave_ioh[pic], 1); 683 if (onoff) 684 mask &= ~bit; 685 else 686 mask |= bit; 687 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, mask); 688 } 689 690 void 691 dec_2100_a500_icic_enable_intr(struct ttwoga_config *tcp, int irq, int onoff) 692 { 693 u_int64_t bit, mask; 694 695 bit = 1UL << irq; 696 697 ICIC_ADDR(tcp, 0x40); 698 699 mask = ICIC_READ(tcp); 700 if (onoff) 701 mask &= ~bit; 702 else 703 mask |= bit; 704 ICIC_WRITE(tcp, mask); 705 } 706 707 void 708 dec_2100_a500_pic_init_intr(struct ttwoga_config *tcp) 709 { 710 static const int picaddr[4] = { 711 0x536, 0x53a, 0x53c, 0x53e 712 }; 713 int pic; 714 715 /* 716 * Map the master PIC. 717 */ 718 if (bus_space_map(pic_iot, 0x534, 2, 0, &pic_master_ioh)) 719 panic("dec_2100_a500_pic_init_intr: unable to map master PIC"); 720 721 /* 722 * Map all slave PICs and mask off the interrupts on them. 723 */ 724 for (pic = 0; pic < 4; pic++) { 725 if (bus_space_map(pic_iot, picaddr[pic], 2, 0, 726 &pic_slave_ioh[pic])) 727 panic("dec_2100_a500_pic_init_intr: unable to map " 728 "slave PIC %d", pic); 729 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 1, 0xff); 730 } 731 732 /* 733 * Map the ELCR registers. 734 */ 735 if (bus_space_map(pic_iot, 0x26, 2, 0, &pic_elcr_ioh)) 736 panic("dec_2100_a500_pic_init_intr: unable to map ELCR " 737 "registers"); 738 } 739 740 void 741 dec_2100_a500_icic_init_intr(struct ttwoga_config *tcp) 742 { 743 744 ICIC_ADDR(tcp, 0x40); 745 ICIC_WRITE(tcp, 0xffffffffffffffffUL); 746 } 747 748 void 749 dec_2100_a500_pic_setlevel(struct ttwoga_config *tcp, int eirq, int level) 750 { 751 int elcr; 752 u_int8_t bit, mask; 753 754 switch (eirq) { /* EISA IRQ */ 755 case 3: 756 case 4: 757 case 5: 758 case 6: 759 case 7: 760 elcr = 0; 761 bit = 1 << (eirq - 3); 762 break; 763 764 case 9: 765 case 10: 766 case 11: 767 elcr = 0; 768 bit = 1 << (eirq - 4); 769 break; 770 771 case 12: 772 elcr = 1; 773 bit = 1 << (eirq - 12); 774 break; 775 776 case 14: 777 case 15: 778 elcr = 1; 779 bit = 1 << (eirq - 13); 780 break; 781 782 default: 783 panic("dec_2100_a500_pic_setlevel: bogus EISA IRQ %d", eirq); 784 } 785 786 mask = bus_space_read_1(pic_iot, pic_elcr_ioh, elcr); 787 if (level) 788 mask |= bit; 789 else 790 mask &= ~bit; 791 bus_space_write_1(pic_iot, pic_elcr_ioh, elcr, mask); 792 } 793 794 void 795 dec_2100_a500_icic_setlevel(struct ttwoga_config *tcp, int eirq, int level) 796 { 797 u_int64_t bit, mask; 798 799 switch (eirq) { 800 case 3: 801 case 4: 802 case 5: 803 case 6: 804 case 7: 805 case 9: 806 case 10: 807 case 11: 808 case 12: 809 case 14: 810 case 15: 811 bit = 1UL << (eirq + T2_IRQ_EISA_START); 812 813 ICIC_ADDR(tcp, 0x50); 814 mask = ICIC_READ(tcp); 815 if (level) 816 mask |= bit; 817 else 818 mask &= ~bit; 819 ICIC_WRITE(tcp, mask); 820 break; 821 822 default: 823 panic("dec_2100_a500_icic_setlevel: bogus EISA IRQ %d", eirq); 824 } 825 } 826 827 void 828 dec_2100_a500_pic_eoi(struct ttwoga_config *tcp, int irq) 829 { 830 int pic; 831 832 if (irq >= 0 && irq <= 7) 833 pic = 0; 834 else if (irq >= 8 && irq <= 15) 835 pic = 1; 836 else if (irq >= 16 && irq <= 23) 837 pic = 2; 838 else 839 pic = 3; 840 841 bus_space_write_1(pic_iot, pic_slave_ioh[pic], 0, 842 0xe0 | (irq - (8 * pic))); 843 bus_space_write_1(pic_iot, pic_master_ioh, 0, 844 0xe0 | pic_slave_to_master[pic]); 845 } 846 847 void 848 dec_2100_a500_icic_eoi(struct ttwoga_config *tcp, int irq) 849 { 850 851 T2GA(tcp, T2_VAR) = irq; 852 alpha_mb(); 853 alpha_mb(); /* MAGIC */ 854 } 855
Indexes created Tue Sep 30 10:09:55 GMT 2025