1 /* $NetBSD: pci_550.c,v 1.42 2021/07/04 22:42:36 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center, and by Andrew Gallatin. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 61 62 __KERNEL_RCSID(0, "$NetBSD: pci_550.c,v 1.42 2021/07/04 22:42:36 thorpej Exp $"); 63 64 #include <sys/types.h> 65 #include <sys/param.h> 66 #include <sys/time.h> 67 #include <sys/systm.h> 68 #include <sys/errno.h> 69 #include <sys/device.h> 70 #include <sys/syslog.h> 71 72 #include <machine/autoconf.h> 73 #include <machine/rpb.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pciidereg.h> 78 #include <dev/pci/pciidevar.h> 79 80 #include <alpha/pci/ciareg.h> 81 #include <alpha/pci/ciavar.h> 82 83 #include "sio.h" 84 #if NSIO 85 #include <alpha/pci/siovar.h> 86 #endif 87 88 static int dec_550_intr_map(const struct pci_attach_args *, 89 pci_intr_handle_t *); 90 static const char *dec_550_intr_string(pci_chipset_tag_t, pci_intr_handle_t, 91 char *, size_t); 92 static const struct evcnt *dec_550_intr_evcnt(pci_chipset_tag_t, 93 pci_intr_handle_t); 94 static void *dec_550_intr_establish(pci_chipset_tag_t, pci_intr_handle_t, 95 int, int (*func)(void *), void *); 96 static void dec_550_intr_disestablish(pci_chipset_tag_t, void *); 97 98 #define DEC_550_PCI_IRQ_BEGIN 8 99 #define DEC_550_MAX_IRQ (64 - DEC_550_PCI_IRQ_BEGIN) 100 101 /* 102 * The Miata has a Pyxis, which seems to have problems with stray 103 * interrupts. Work around this by just ignoring strays. 104 */ 105 #define PCI_STRAY_MAX 0 106 107 /* 108 * Some Miata models, notably models with a Cypress PCI-ISA bridge, have 109 * a PCI device (the OHCI USB controller) with interrupts tied to ISA IRQ 110 * lines. This IRQ is encoded as: line = FLAG | isa_irq. Usually FLAG 111 * is 0xe0, however, it can be 0xf0. We don't allow 0xf0 | irq15. 112 */ 113 #define DEC_550_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xfe) 114 #define DEC_550_LINE_ISA_IRQ(line) ((line) & 0x0f) 115 116 static void dec_550_intr_enable(pci_chipset_tag_t, int irq); 117 static void dec_550_intr_disable(pci_chipset_tag_t, int irq); 118 119 static void 120 pci_550_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt, 121 pci_chipset_tag_t pc) 122 { 123 int i; 124 125 pc->pc_intr_v = core; 126 pc->pc_intr_map = dec_550_intr_map; 127 pc->pc_intr_string = dec_550_intr_string; 128 pc->pc_intr_evcnt = dec_550_intr_evcnt; 129 pc->pc_intr_establish = dec_550_intr_establish; 130 pc->pc_intr_disestablish = dec_550_intr_disestablish; 131 132 pc->pc_pciide_compat_intr_establish = 133 sio_pciide_compat_intr_establish; 134 135 pc->pc_intr_desc = "dec 550"; 136 pc->pc_vecbase = 0x900; 137 pc->pc_nirq = DEC_550_MAX_IRQ; 138 139 pc->pc_intr_enable = dec_550_intr_enable; 140 pc->pc_intr_disable = dec_550_intr_disable; 141 142 for (i = 0; i < DEC_550_MAX_IRQ; i++) { 143 dec_550_intr_disable(pc, i); 144 } 145 146 alpha_pci_intr_alloc(pc, PCI_STRAY_MAX); 147 148 #if NSIO 149 sio_intr_setup(pc, iot); 150 #endif 151 } 152 ALPHA_PCI_INTR_INIT(ST_DEC_550, pci_550_pickintr) 153 154 static int 155 dec_550_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 156 { 157 pcitag_t bustag = pa->pa_intrtag; 158 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 159 pci_chipset_tag_t pc = pa->pa_pc; 160 int bus, device, function; 161 162 if (buspin == 0) { 163 /* No IRQ used. */ 164 return 1; 165 } 166 if (buspin < 0 || buspin > 4) { 167 printf("dec_550_intr_map: bad interrupt pin %d\n", buspin); 168 return 1; 169 } 170 171 pci_decompose_tag(pc, bustag, &bus, &device, &function); 172 173 /* 174 * There are two main variants of Miata: Miata 1 (Intel SIO) 175 * and Miata {1.5,2} (Cypress). 176 * 177 * The Miata 1 has a CMD PCI IDE wired to compatibility mode at 178 * device 4 of bus 0. This variant apparently also has the 179 * Pyxis DMA bug. 180 * 181 * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives 182 * on device 7 of bus 0. This device has PCI IDE wired to 183 * compatibility mode on functions 1 and 2. 184 * 185 * There will be no interrupt mapping for these devices, so just 186 * bail out now. 187 */ 188 if (bus == 0) { 189 if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 190 /* Miata 1 */ 191 if (device == 7) 192 panic("dec_550_intr_map: SIO device"); 193 else if (device == 4) 194 return (1); 195 } else { 196 /* Miata 1.5 or Miata 2 */ 197 if (device == 7) { 198 if (function == 0) 199 panic("dec_550_intr_map: SIO device"); 200 if (function == 1 || function == 2) 201 return (1); 202 } 203 } 204 } 205 206 /* 207 * The console places the interrupt mapping in the "line" value. 208 * A value of (char)-1 indicates there is no mapping. 209 */ 210 if (line == 0xff) { 211 printf("dec_550_intr_map: no mapping for %d/%d/%d\n", 212 bus, device, function); 213 return (1); 214 } 215 216 #if NSIO == 0 217 if (DEC_550_LINE_IS_ISA(line)) { 218 printf("dec_550_intr_map: ISA IRQ %d for %d/%d/%d\n", 219 DEC_550_LINE_ISA_IRQ(line), bus, device, function); 220 return (1); 221 } 222 #endif 223 224 if (DEC_550_LINE_IS_ISA(line) == 0 && line >= DEC_550_MAX_IRQ) { 225 printf("dec_550_intr_map: irq %d out of range %d/%d/%d\n", 226 line, bus, device, function); 227 return (1); 228 } 229 alpha_pci_intr_handle_init(ihp, line, 0); 230 return (0); 231 } 232 233 static const char * 234 dec_550_intr_string(pci_chipset_tag_t const pc, pci_intr_handle_t const ih, 235 char * const buf, size_t const len) 236 { 237 #if NSIO 238 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 239 240 if (DEC_550_LINE_IS_ISA(irq)) 241 return sio_intr_string(NULL /*XXX*/, 242 DEC_550_LINE_ISA_IRQ(irq), buf, len); 243 #endif 244 245 return alpha_pci_generic_intr_string(pc, ih, buf, len); 246 } 247 248 static const struct evcnt * 249 dec_550_intr_evcnt(pci_chipset_tag_t const pc, pci_intr_handle_t const ih) 250 { 251 #if NSIO 252 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 253 254 if (DEC_550_LINE_IS_ISA(irq)) 255 return (sio_intr_evcnt(NULL /*XXX*/, 256 DEC_550_LINE_ISA_IRQ(irq))); 257 #endif 258 259 return alpha_pci_generic_intr_evcnt(pc, ih); 260 } 261 262 static void * 263 dec_550_intr_establish(pci_chipset_tag_t const pc, pci_intr_handle_t const ih, 264 int const level, int (*func)(void *), void *arg) 265 { 266 #if NSIO 267 const u_int irq = alpha_pci_intr_handle_get_irq(&ih); 268 const u_int flags = alpha_pci_intr_handle_get_flags(&ih); 269 270 if (DEC_550_LINE_IS_ISA(irq)) 271 return (sio_intr_establish(NULL /*XXX*/, 272 DEC_550_LINE_ISA_IRQ(irq), IST_LEVEL, level, flags, 273 func, arg)); 274 #endif 275 276 return alpha_pci_generic_intr_establish(pc, ih, level, func, arg); 277 } 278 279 static void 280 dec_550_intr_disestablish(pci_chipset_tag_t const pc, void * const cookie) 281 { 282 #if NSIO 283 struct alpha_shared_intrhand * const ih = cookie; 284 285 /* 286 * We have to determine if this is an ISA IRQ or not! We do this 287 * by checking to see if the intrhand points back to an intrhead 288 * that points to our cia_config. If not, it's an ISA IRQ. Pretty 289 * disgusting, eh? 290 */ 291 if (ih->ih_intrhead->intr_private != pc->pc_intr_v) { 292 sio_intr_disestablish(NULL /*XXX*/, cookie); 293 return; 294 } 295 #endif 296 297 alpha_pci_generic_intr_disestablish(pc, cookie); 298 } 299 300 static void 301 dec_550_intr_enable(pci_chipset_tag_t const pc __unused, int const irq) 302 { 303 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 1); 304 } 305 306 static void 307 dec_550_intr_disable(pci_chipset_tag_t const pc __unused, int const irq) 308 { 309 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 0); 310 } 311
Indexes created Sat Sep 20 22:09:52 GMT 2025