pci_550.c revision 1.13
1 /* $NetBSD: pci_550.c,v 1.13 1999/02/12 06:25:13 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center, and by Andrew Gallatin. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: pci_550.c,v 1.13 1999/02/12 06:25:13 thorpej Exp $"); 70 71 #include <sys/types.h> 72 #include <sys/param.h> 73 #include <sys/time.h> 74 #include <sys/systm.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/syslog.h> 79 80 #include <vm/vm.h> 81 82 #include <machine/autoconf.h> 83 #include <machine/rpb.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pciidereg.h> 88 #include <dev/pci/pciidevar.h> 89 90 #include <alpha/pci/ciareg.h> 91 #include <alpha/pci/ciavar.h> 92 93 #include <alpha/pci/pci_550.h> 94 95 #ifndef EVCNT_COUNTERS 96 #include <machine/intrcnt.h> 97 #endif 98 99 #include "sio.h" 100 #if NSIO 101 #include <alpha/pci/siovar.h> 102 #endif 103 104 int dec_550_intr_map __P((void *, pcitag_t, int, int, 105 pci_intr_handle_t *)); 106 const char *dec_550_intr_string __P((void *, pci_intr_handle_t)); 107 void *dec_550_intr_establish __P((void *, pci_intr_handle_t, 108 int, int (*func)(void *), void *)); 109 void dec_550_intr_disestablish __P((void *, void *)); 110 111 void *dec_550_pciide_compat_intr_establish __P((void *, struct device *, 112 struct pci_attach_args *, int, int (*)(void *), void *)); 113 114 #define DEC_550_PCI_IRQ_BEGIN 8 115 #define DEC_550_MAX_IRQ 48 116 117 /* 118 * The Miata has a Pyxis, which seems to have problems with stray 119 * interrupts. Work around this by just ignoring strays. 120 */ 121 #define PCI_STRAY_MAX 0 122 123 struct alpha_shared_intr *dec_550_pci_intr; 124 #ifdef EVCNT_COUNTERS 125 struct evcnt dec_550_intr_evcnt; 126 #endif 127 128 void dec_550_iointr __P((void *framep, unsigned long vec)); 129 void dec_550_intr_enable __P((int irq)); 130 void dec_550_intr_disable __P((int irq)); 131 132 void 133 pci_550_pickintr(ccp) 134 struct cia_config *ccp; 135 { 136 bus_space_tag_t iot = &ccp->cc_iot; 137 pci_chipset_tag_t pc = &ccp->cc_pc; 138 int i; 139 140 pc->pc_intr_v = ccp; 141 pc->pc_intr_map = dec_550_intr_map; 142 pc->pc_intr_string = dec_550_intr_string; 143 pc->pc_intr_establish = dec_550_intr_establish; 144 pc->pc_intr_disestablish = dec_550_intr_disestablish; 145 146 pc->pc_pciide_compat_intr_establish = 147 dec_550_pciide_compat_intr_establish; 148 149 /* 150 * DEC 550's interrupts are enabled via the Pyxis interrupt 151 * mask register. Nothing to map. 152 */ 153 154 for (i = DEC_550_PCI_IRQ_BEGIN; i < DEC_550_MAX_IRQ; i++) 155 dec_550_intr_disable(i); 156 157 dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ); 158 for (i = 0; i < DEC_550_MAX_IRQ; i++) 159 alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i, 160 PCI_STRAY_MAX); 161 162 #if NSIO 163 sio_intr_setup(pc, iot); 164 #endif 165 166 set_iointr(dec_550_iointr); 167 } 168 169 int 170 dec_550_intr_map(ccv, bustag, buspin, line, ihp) 171 void *ccv; 172 pcitag_t bustag; 173 int buspin, line; 174 pci_intr_handle_t *ihp; 175 { 176 struct cia_config *ccp = ccv; 177 pci_chipset_tag_t pc = &ccp->cc_pc; 178 int bus, device, function; 179 180 if (buspin == 0) { 181 /* No IRQ used. */ 182 return 1; 183 } 184 if (buspin > 4) { 185 printf("dec_550_intr_map: bad interrupt pin %d\n", buspin); 186 return 1; 187 } 188 189 alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function); 190 191 /* 192 * There are two main variants of Miata: Miata 1 (Intel SIO) 193 * and Miata {1.5,2} (Cypress). 194 * 195 * The Miata 1 has a CMD PCI IDE wired to compatibility mode at 196 * device 4 of bus 0. This variant apparently also has the 197 * Pyxis DMA bug. 198 * 199 * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives 200 * on device 7 of bus 0. This device has PCI IDE wired to 201 * compatibility mode on functions 1 and 2. 202 * 203 * There will be no interrupt mapping for these devices, so just 204 * bail out now. 205 */ 206 if (bus == 0) { 207 if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 208 /* Miata 1 */ 209 if (device == 7) 210 panic("dec_550_intr_map: SIO device"); 211 else if (device == 4) 212 return (1); 213 } else { 214 /* Miata 1.5 or Miata 2 */ 215 if (device == 7) { 216 if (function == 0) 217 panic("dec_550_intr_map: SIO device"); 218 return (1); 219 } 220 } 221 } 222 223 /* 224 * The console places the interrupt mapping in the "line" value. 225 * A value of (char)-1 indicates there is no mapping. 226 */ 227 if (line == 0xff) { 228 printf("dec_550_intr_map: no mapping for %d/%d/%d\n", 229 bus, device, function); 230 return (1); 231 } 232 233 /* Account for the PCI interrupt offset. */ 234 line += DEC_550_PCI_IRQ_BEGIN; 235 236 if (line >= DEC_550_MAX_IRQ) 237 panic("dec_550_intr_map: dec 550 irq too large (%d)\n", 238 line); 239 240 *ihp = line; 241 return (0); 242 } 243 244 const char * 245 dec_550_intr_string(ccv, ih) 246 void *ccv; 247 pci_intr_handle_t ih; 248 { 249 #if 0 250 struct cia_config *ccp = ccv; 251 #endif 252 static char irqstr[16]; /* 12 + 2 + NULL + sanity */ 253 254 if (ih >= DEC_550_MAX_IRQ) 255 panic("dec_550_intr_string: bogus 550 IRQ 0x%lx\n", ih); 256 sprintf(irqstr, "dec 550 irq %ld", ih); 257 return (irqstr); 258 } 259 260 void * 261 dec_550_intr_establish(ccv, ih, level, func, arg) 262 void *ccv, *arg; 263 pci_intr_handle_t ih; 264 int level; 265 int (*func) __P((void *)); 266 { 267 #if 0 268 struct cia_config *ccp = ccv; 269 #endif 270 void *cookie; 271 272 if (ih >= DEC_550_MAX_IRQ) 273 panic("dec_550_intr_establish: bogus dec 550 IRQ 0x%lx\n", ih); 274 275 cookie = alpha_shared_intr_establish(dec_550_pci_intr, ih, IST_LEVEL, 276 level, func, arg, "dec 550 irq"); 277 278 if (cookie != NULL && alpha_shared_intr_isactive(dec_550_pci_intr, ih)) 279 dec_550_intr_enable(ih); 280 return (cookie); 281 } 282 283 void 284 dec_550_intr_disestablish(ccv, cookie) 285 void *ccv, *cookie; 286 { 287 #if 0 288 struct cia_config *ccp = ccv; 289 #endif 290 struct alpha_shared_intrhand *ih = cookie; 291 unsigned int irq = ih->ih_num; 292 int s; 293 294 s = splhigh(); 295 296 alpha_shared_intr_disestablish(dec_550_pci_intr, cookie, 297 "dec 550 irq"); 298 if (alpha_shared_intr_isactive(dec_550_pci_intr, irq) == 0) { 299 dec_550_intr_disable(irq); 300 alpha_shared_intr_set_dfltsharetype(dec_550_pci_intr, irq, 301 IST_NONE); 302 } 303 304 splx(s); 305 } 306 307 void * 308 dec_550_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 309 void *v; 310 struct device *dev; 311 struct pci_attach_args *pa; 312 int chan; 313 int (*func) __P((void *)); 314 void *arg; 315 { 316 pci_chipset_tag_t pc = pa->pa_pc; 317 void *cookie = NULL; 318 int bus, irq; 319 320 alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 321 322 /* 323 * If this isn't PCI bus #0, all bets are off. 324 */ 325 if (bus != 0) 326 return (NULL); 327 328 irq = PCIIDE_COMPAT_IRQ(chan); 329 #if NSIO 330 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 331 func, arg); 332 #endif 333 return (cookie); 334 } 335 336 void 337 dec_550_iointr(framep, vec) 338 void *framep; 339 unsigned long vec; 340 { 341 int irq; 342 343 if (vec >= 0x900) { 344 irq = ((vec - 0x900) >> 4) + DEC_550_PCI_IRQ_BEGIN; 345 346 if (irq >= DEC_550_MAX_IRQ) 347 panic("550_iointr: vec 0x%lx out of range\n", vec); 348 349 #ifdef EVCNT_COUNTERS 350 dec_550_intr_evcnt.ev_count++; 351 #else 352 if (DEC_550_MAX_IRQ != INTRCNT_DEC_550_IRQ_LEN) 353 panic("dec_550 interrupt counter sizes inconsistent"); 354 intrcnt[INTRCNT_DEC_550_IRQ + irq]++; 355 #endif 356 357 if (!alpha_shared_intr_dispatch(dec_550_pci_intr, irq)) { 358 alpha_shared_intr_stray(dec_550_pci_intr, irq, 359 "dec 550 irq"); 360 if (ALPHA_SHARED_INTR_DISABLE(dec_550_pci_intr, irq)) 361 dec_550_intr_disable(irq); 362 } 363 return; 364 } 365 #if NSIO 366 if (vec >= 0x800) { 367 sio_iointr(framep, vec); 368 return; 369 } 370 #endif 371 panic("dec_550_iointr: weird vec 0x%lx\n", vec); 372 } 373 374 void 375 dec_550_intr_enable(irq) 376 int irq; 377 { 378 u_int64_t imask; 379 int s; 380 381 #if 0 382 printf("dec_550_intr_enable: enabling %d\n", irq); 383 #endif 384 385 s = splhigh(); 386 alpha_mb(); 387 imask = REGVAL64(PYXIS_INT_MASK); 388 imask |= (1UL << irq); 389 REGVAL64(PYXIS_INT_MASK) = imask; 390 alpha_mb(); 391 splx(s); 392 } 393 394 void 395 dec_550_intr_disable(irq) 396 int irq; 397 { 398 u_int64_t imask; 399 int s; 400 401 #if 0 402 printf("dec_550_intr_disable: disabling %d\n", irq); 403 #endif 404 405 s = splhigh(); 406 alpha_mb(); 407 imask = REGVAL64(PYXIS_INT_MASK); 408 imask &= ~(1UL << irq); 409 REGVAL64(PYXIS_INT_MASK) = imask; 410 alpha_mb(); 411 splx(s); 412 } 413
Indexes created Mon Sep 29 21:09:56 GMT 2025