pci_550.c revision 1.15
1 /* $NetBSD: pci_550.c,v 1.15 2000/06/04 19:14:21 cgd Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center, and by Andrew Gallatin. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: pci_550.c,v 1.15 2000/06/04 19:14:21 cgd Exp $"); 70 71 #include <sys/types.h> 72 #include <sys/param.h> 73 #include <sys/time.h> 74 #include <sys/systm.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/syslog.h> 79 80 #include <vm/vm.h> 81 82 #include <machine/autoconf.h> 83 #include <machine/rpb.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pciidereg.h> 88 #include <dev/pci/pciidevar.h> 89 90 #include <alpha/pci/ciareg.h> 91 #include <alpha/pci/ciavar.h> 92 93 #include <alpha/pci/pci_550.h> 94 95 #ifndef EVCNT_COUNTERS 96 #include <machine/intrcnt.h> 97 #endif 98 99 #include "sio.h" 100 #if NSIO 101 #include <alpha/pci/siovar.h> 102 #endif 103 104 int dec_550_intr_map __P((void *, pcitag_t, int, int, 105 pci_intr_handle_t *)); 106 const char *dec_550_intr_string __P((void *, pci_intr_handle_t)); 107 const struct evcnt *dec_550_intr_evcnt __P((void *, pci_intr_handle_t)); 108 void *dec_550_intr_establish __P((void *, pci_intr_handle_t, 109 int, int (*func)(void *), void *)); 110 void dec_550_intr_disestablish __P((void *, void *)); 111 112 void *dec_550_pciide_compat_intr_establish __P((void *, struct device *, 113 struct pci_attach_args *, int, int (*)(void *), void *)); 114 115 #define DEC_550_PCI_IRQ_BEGIN 8 116 #define DEC_550_MAX_IRQ (64 - DEC_550_PCI_IRQ_BEGIN) 117 118 /* 119 * The Miata has a Pyxis, which seems to have problems with stray 120 * interrupts. Work around this by just ignoring strays. 121 */ 122 #define PCI_STRAY_MAX 0 123 124 /* 125 * Some Miata models, notably models with a Cypress PCI-ISA bridge, have 126 * a PCI device (the OHCI USB controller) with interrupts tied to ISA IRQ 127 * lines. This IRQ is encoded as: 128 * 129 * line = 0xe0 | isa_irq; 130 */ 131 #define DEC_550_LINE_IS_ISA(line) ((line) >= 0xe0 && (line) <= 0xef) 132 #define DEC_550_LINE_ISA_IRQ(line) ((line) & 0x0f) 133 134 struct alpha_shared_intr *dec_550_pci_intr; 135 #ifdef EVCNT_COUNTERS 136 struct evcnt dec_550_intr_evcnt; 137 #endif 138 139 void dec_550_iointr __P((void *framep, unsigned long vec)); 140 void dec_550_intr_enable __P((int irq)); 141 void dec_550_intr_disable __P((int irq)); 142 143 void 144 pci_550_pickintr(ccp) 145 struct cia_config *ccp; 146 { 147 bus_space_tag_t iot = &ccp->cc_iot; 148 pci_chipset_tag_t pc = &ccp->cc_pc; 149 int i; 150 151 pc->pc_intr_v = ccp; 152 pc->pc_intr_map = dec_550_intr_map; 153 pc->pc_intr_string = dec_550_intr_string; 154 pc->pc_intr_evcnt = dec_550_intr_evcnt; 155 pc->pc_intr_establish = dec_550_intr_establish; 156 pc->pc_intr_disestablish = dec_550_intr_disestablish; 157 158 pc->pc_pciide_compat_intr_establish = 159 dec_550_pciide_compat_intr_establish; 160 161 /* 162 * DEC 550's interrupts are enabled via the Pyxis interrupt 163 * mask register. Nothing to map. 164 */ 165 166 for (i = 0; i < DEC_550_MAX_IRQ; i++) 167 dec_550_intr_disable(i); 168 169 dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ); 170 for (i = 0; i < DEC_550_MAX_IRQ; i++) { 171 alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i, 172 PCI_STRAY_MAX); 173 alpha_shared_intr_set_private(dec_550_pci_intr, i, ccp); 174 } 175 176 #if NSIO 177 sio_intr_setup(pc, iot); 178 #endif 179 180 set_iointr(dec_550_iointr); 181 } 182 183 int 184 dec_550_intr_map(ccv, bustag, buspin, line, ihp) 185 void *ccv; 186 pcitag_t bustag; 187 int buspin, line; 188 pci_intr_handle_t *ihp; 189 { 190 struct cia_config *ccp = ccv; 191 pci_chipset_tag_t pc = &ccp->cc_pc; 192 int bus, device, function; 193 194 if (buspin == 0) { 195 /* No IRQ used. */ 196 return 1; 197 } 198 if (buspin > 4) { 199 printf("dec_550_intr_map: bad interrupt pin %d\n", buspin); 200 return 1; 201 } 202 203 alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function); 204 205 /* 206 * There are two main variants of Miata: Miata 1 (Intel SIO) 207 * and Miata {1.5,2} (Cypress). 208 * 209 * The Miata 1 has a CMD PCI IDE wired to compatibility mode at 210 * device 4 of bus 0. This variant apparently also has the 211 * Pyxis DMA bug. 212 * 213 * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives 214 * on device 7 of bus 0. This device has PCI IDE wired to 215 * compatibility mode on functions 1 and 2. 216 * 217 * There will be no interrupt mapping for these devices, so just 218 * bail out now. 219 */ 220 if (bus == 0) { 221 if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 222 /* Miata 1 */ 223 if (device == 7) 224 panic("dec_550_intr_map: SIO device"); 225 else if (device == 4) 226 return (1); 227 } else { 228 /* Miata 1.5 or Miata 2 */ 229 if (device == 7) { 230 if (function == 0) 231 panic("dec_550_intr_map: SIO device"); 232 if (function == 1 || function == 2) 233 return (1); 234 } 235 } 236 } 237 238 /* 239 * The console places the interrupt mapping in the "line" value. 240 * A value of (char)-1 indicates there is no mapping. 241 */ 242 if (line == 0xff) { 243 printf("dec_550_intr_map: no mapping for %d/%d/%d\n", 244 bus, device, function); 245 return (1); 246 } 247 248 #if NSIO == 0 249 if (DEC_550_LINE_IS_ISA(line)) { 250 printf("dec_550_intr_map: ISA IRQ %d for %d/%d/%d\n", 251 DEC_550_LINE_ISA_IRQ(line), bus, device, function); 252 return (1); 253 } 254 #endif 255 256 if (DEC_550_LINE_IS_ISA(line) == 0 && line >= DEC_550_MAX_IRQ) 257 panic("dec_550_intr_map: dec 550 irq too large (%d)\n", 258 line); 259 260 *ihp = line; 261 return (0); 262 } 263 264 const char * 265 dec_550_intr_string(ccv, ih) 266 void *ccv; 267 pci_intr_handle_t ih; 268 { 269 #if 0 270 struct cia_config *ccp = ccv; 271 #endif 272 static char irqstr[16]; /* 12 + 2 + NULL + sanity */ 273 274 #if NSIO 275 if (DEC_550_LINE_IS_ISA(ih)) 276 return (sio_intr_string(NULL /*XXX*/, 277 DEC_550_LINE_ISA_IRQ(ih))); 278 #endif 279 280 if (ih >= DEC_550_MAX_IRQ) 281 panic("dec_550_intr_string: bogus 550 IRQ 0x%lx\n", ih); 282 sprintf(irqstr, "dec 550 irq %ld", ih); 283 return (irqstr); 284 } 285 286 const struct evcnt * 287 dec_550_intr_evcnt(ccv, ih) 288 void *ccv; 289 pci_intr_handle_t ih; 290 { 291 #if 0 292 struct cia_config *ccp = ccv; 293 #endif 294 295 #if NSIO 296 if (DEC_550_LINE_IS_ISA(ih)) 297 return (sio_intr_evcnt(NULL /*XXX*/, 298 DEC_550_LINE_ISA_IRQ(ih))); 299 #endif 300 301 /* XXX for now, no evcnt parent reported */ 302 return (NULL); 303 } 304 305 void * 306 dec_550_intr_establish(ccv, ih, level, func, arg) 307 void *ccv, *arg; 308 pci_intr_handle_t ih; 309 int level; 310 int (*func) __P((void *)); 311 { 312 #if 0 313 struct cia_config *ccp = ccv; 314 #endif 315 void *cookie; 316 317 #if NSIO 318 if (DEC_550_LINE_IS_ISA(ih)) 319 return (sio_intr_establish(NULL /*XXX*/, 320 DEC_550_LINE_ISA_IRQ(ih), IST_LEVEL, level, func, arg)); 321 #endif 322 323 if (ih >= DEC_550_MAX_IRQ) 324 panic("dec_550_intr_establish: bogus dec 550 IRQ 0x%lx\n", ih); 325 326 cookie = alpha_shared_intr_establish(dec_550_pci_intr, ih, IST_LEVEL, 327 level, func, arg, "dec 550 irq"); 328 329 if (cookie != NULL && alpha_shared_intr_isactive(dec_550_pci_intr, ih)) 330 dec_550_intr_enable(ih); 331 return (cookie); 332 } 333 334 void 335 dec_550_intr_disestablish(ccv, cookie) 336 void *ccv, *cookie; 337 { 338 struct cia_config *ccp = ccv; 339 struct alpha_shared_intrhand *ih = cookie; 340 unsigned int irq = ih->ih_num; 341 int s; 342 343 #if NSIO 344 /* 345 * We have to determine if this is an ISA IRQ or not! We do this 346 * by checking to see if the intrhand points back to an intrhead 347 * that points to our cia_config. If not, it's an ISA IRQ. Pretty 348 * disgusting, eh? 349 */ 350 if (ih->ih_intrhead->intr_private != ccp) { 351 sio_intr_disestablish(NULL /*XXX*/, cookie); 352 return; 353 } 354 #endif 355 356 s = splhigh(); 357 358 alpha_shared_intr_disestablish(dec_550_pci_intr, cookie, 359 "dec 550 irq"); 360 if (alpha_shared_intr_isactive(dec_550_pci_intr, irq) == 0) { 361 dec_550_intr_disable(irq); 362 alpha_shared_intr_set_dfltsharetype(dec_550_pci_intr, irq, 363 IST_NONE); 364 } 365 366 splx(s); 367 } 368 369 void * 370 dec_550_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 371 void *v; 372 struct device *dev; 373 struct pci_attach_args *pa; 374 int chan; 375 int (*func) __P((void *)); 376 void *arg; 377 { 378 pci_chipset_tag_t pc = pa->pa_pc; 379 void *cookie = NULL; 380 int bus, irq; 381 382 alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 383 384 /* 385 * If this isn't PCI bus #0, all bets are off. 386 */ 387 if (bus != 0) 388 return (NULL); 389 390 irq = PCIIDE_COMPAT_IRQ(chan); 391 #if NSIO 392 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 393 func, arg); 394 #endif 395 return (cookie); 396 } 397 398 void 399 dec_550_iointr(framep, vec) 400 void *framep; 401 unsigned long vec; 402 { 403 int irq; 404 405 if (vec >= 0x900) { 406 irq = ((vec - 0x900) >> 4); 407 408 if (irq >= DEC_550_MAX_IRQ) 409 panic("550_iointr: vec 0x%lx out of range\n", vec); 410 411 #ifdef EVCNT_COUNTERS 412 dec_550_intr_evcnt.ev_count++; 413 #else 414 if (DEC_550_MAX_IRQ != INTRCNT_DEC_550_IRQ_LEN) 415 panic("dec_550 interrupt counter sizes inconsistent"); 416 intrcnt[INTRCNT_DEC_550_IRQ + irq]++; 417 #endif 418 419 if (!alpha_shared_intr_dispatch(dec_550_pci_intr, irq)) { 420 alpha_shared_intr_stray(dec_550_pci_intr, irq, 421 "dec 550 irq"); 422 if (ALPHA_SHARED_INTR_DISABLE(dec_550_pci_intr, irq)) 423 dec_550_intr_disable(irq); 424 } 425 return; 426 } 427 #if NSIO 428 if (vec >= 0x800) { 429 sio_iointr(framep, vec); 430 return; 431 } 432 #endif 433 panic("dec_550_iointr: weird vec 0x%lx\n", vec); 434 } 435 436 void 437 dec_550_intr_enable(irq) 438 int irq; 439 { 440 441 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 1); 442 } 443 444 void 445 dec_550_intr_disable(irq) 446 int irq; 447 { 448 449 cia_pyxis_intr_enable(irq + DEC_550_PCI_IRQ_BEGIN, 0); 450 } 451
Indexes created Tue Sep 30 11:09:46 GMT 2025