pci_550.c revision 1.4
1 /* $NetBSD: pci_550.c,v 1.4 1998/06/05 17:42:53 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center, and by Andrew Gallatin. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: pci_550.c,v 1.4 1998/06/05 17:42:53 thorpej Exp $"); 70 71 #include <sys/types.h> 72 #include <sys/param.h> 73 #include <sys/time.h> 74 #include <sys/systm.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/syslog.h> 79 80 #include <vm/vm.h> 81 82 #include <machine/autoconf.h> 83 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 #include <dev/pci/pciidereg.h> 87 #include <dev/pci/pciidevar.h> 88 89 #include <alpha/pci/ciareg.h> 90 #include <alpha/pci/ciavar.h> 91 92 #include <alpha/pci/pci_550.h> 93 94 #ifndef EVCNT_COUNTERS 95 #include <machine/intrcnt.h> 96 #endif 97 98 #include "sio.h" 99 #if NSIO 100 #include <alpha/pci/siovar.h> 101 #endif 102 103 int dec_550_intr_map __P((void *, pcitag_t, int, int, 104 pci_intr_handle_t *)); 105 const char *dec_550_intr_string __P((void *, pci_intr_handle_t)); 106 void *dec_550_intr_establish __P((void *, pci_intr_handle_t, 107 int, int (*func)(void *), void *)); 108 void dec_550_intr_disestablish __P((void *, void *)); 109 110 void *dec_550_pciide_compat_intr_establish __P((void *, struct device *, 111 struct pci_attach_args *, int, int (*)(void *), void *)); 112 113 #define DEC_550_PCI_IRQ_BEGIN 8 114 #define DEC_550_MAX_IRQ 48 115 #define PCI_STRAY_MAX 5 116 117 struct alpha_shared_intr *dec_550_pci_intr; 118 #ifdef EVCNT_COUNTERS 119 struct evcnt dec_550_intr_evcnt; 120 #endif 121 122 void dec_550_iointr __P((void *framep, unsigned long vec)); 123 void dec_550_intr_enable __P((int irq)); 124 void dec_550_intr_disable __P((int irq)); 125 126 u_int64_t *dec_550_int_mask_reg; 127 128 void 129 pci_550_pickintr(ccp) 130 struct cia_config *ccp; 131 { 132 bus_space_tag_t iot = &ccp->cc_iot; 133 pci_chipset_tag_t pc = &ccp->cc_pc; 134 int i; 135 136 pc->pc_intr_v = ccp; 137 pc->pc_intr_map = dec_550_intr_map; 138 pc->pc_intr_string = dec_550_intr_string; 139 pc->pc_intr_establish = dec_550_intr_establish; 140 pc->pc_intr_disestablish = dec_550_intr_disestablish; 141 142 pc->pc_pciide_compat_intr_establish = 143 dec_550_pciide_compat_intr_establish; 144 145 /* 146 * DEC 550's interrupts are enabled via the Pyxis interrupt 147 * mask register. 148 */ 149 dec_550_int_mask_reg = 150 (u_int64_t *)ALPHA_PHYS_TO_K0SEG(PYXIS_INT_MASK); 151 152 for (i = DEC_550_PCI_IRQ_BEGIN; i < DEC_550_MAX_IRQ; i++) 153 dec_550_intr_disable(i); 154 155 dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ); 156 for (i = 0; i < DEC_550_MAX_IRQ; i++) 157 alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i, 158 PCI_STRAY_MAX); 159 160 #if NSIO 161 sio_intr_setup(pc, iot); 162 #endif 163 164 set_iointr(dec_550_iointr); 165 } 166 167 int 168 dec_550_intr_map(ccv, bustag, buspin, line, ihp) 169 void *ccv; 170 pcitag_t bustag; 171 int buspin, line; 172 pci_intr_handle_t *ihp; 173 { 174 struct cia_config *ccp = ccv; 175 pci_chipset_tag_t pc = &ccp->cc_pc; 176 int bus, device, function; 177 178 if (buspin == 0) { 179 /* No IRQ used. */ 180 return 1; 181 } 182 if (buspin > 4) { 183 printf("dec_550_intr_map: bad interrupt pin %d\n", buspin); 184 return 1; 185 } 186 187 alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function); 188 189 /* 190 * The PCI-ISA bridge lives on device 7 of bus 0. On the MiataGL 191 * this is a Cypress chip with PCI IDE wired to compatibility 192 * mode on functions 1 and 2. There will be no interrupt mapping 193 * for this device, so just bail out now. 194 */ 195 if (bus == 0 && device == 7) { 196 if (function == 0) 197 panic("dec_550_intr_map: SIO device"); 198 } 199 200 /* 201 * The console places the interrupt mapping in the "line" value. 202 * A value of (char)-1 indicates there is no mapping. 203 */ 204 if (line == 0xff) { 205 printf("dec_550_intr_map: no mapping for %d/%d/%d\n", 206 bus, device, function); 207 return (1); 208 } 209 210 /* Account for the PCI interrupt offset. */ 211 line += DEC_550_PCI_IRQ_BEGIN; 212 213 if (line >= DEC_550_MAX_IRQ) 214 panic("dec_550_intr_map: dec 550 irq too large (%d)\n", 215 line); 216 217 *ihp = line; 218 return (0); 219 } 220 221 const char * 222 dec_550_intr_string(ccv, ih) 223 void *ccv; 224 pci_intr_handle_t ih; 225 { 226 #if 0 227 struct cia_config *ccp = ccv; 228 #endif 229 static char irqstr[16]; /* 12 + 2 + NULL + sanity */ 230 231 if (ih >= DEC_550_MAX_IRQ) 232 panic("dec_550_intr_string: bogus 550 IRQ 0x%x\n", ih); 233 sprintf(irqstr, "dec 550 irq %d", ih); 234 return (irqstr); 235 } 236 237 void * 238 dec_550_intr_establish(ccv, ih, level, func, arg) 239 void *ccv, *arg; 240 pci_intr_handle_t ih; 241 int level; 242 int (*func) __P((void *)); 243 { 244 #if 0 245 struct cia_config *ccp = ccv; 246 #endif 247 void *cookie; 248 249 if (ih >= DEC_550_MAX_IRQ) 250 panic("dec_550_intr_establish: bogus dec 550 IRQ 0x%x\n", ih); 251 252 cookie = alpha_shared_intr_establish(dec_550_pci_intr, ih, IST_LEVEL, 253 level, func, arg, "dec 550 irq"); 254 255 if (cookie != NULL && alpha_shared_intr_isactive(dec_550_pci_intr, ih)) 256 dec_550_intr_enable(ih); 257 return (cookie); 258 } 259 260 void 261 dec_550_intr_disestablish(ccv, cookie) 262 void *ccv, *cookie; 263 { 264 #if 0 265 struct cia_config *ccp = ccv; 266 #endif 267 268 panic("dec_550_intr_disestablish not implemented"); /* XXX */ 269 } 270 271 void * 272 dec_550_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 273 void *v; 274 struct device *dev; 275 struct pci_attach_args *pa; 276 int chan; 277 int (*func) __P((void *)); 278 void *arg; 279 { 280 pci_chipset_tag_t pc = pa->pa_pc; 281 void *cookie = NULL; 282 int bus, irq; 283 284 alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 285 286 /* 287 * If this isn't PCI bus #0, all bets are off. 288 */ 289 if (bus != 0) 290 return (NULL); 291 292 irq = PCIIDE_COMPAT_IRQ(chan); 293 #if NSIO 294 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 295 func, arg); 296 #endif 297 return (cookie); 298 } 299 300 void 301 dec_550_iointr(framep, vec) 302 void *framep; 303 unsigned long vec; 304 { 305 int irq; 306 307 if (vec >= 0x900) { 308 irq = ((vec - 0x900) >> 4) + DEC_550_PCI_IRQ_BEGIN; 309 310 if (irq >= DEC_550_MAX_IRQ) 311 panic("550_iointr: vec 0x%x out of range\n", vec); 312 313 #ifdef EVCNT_COUNTERS 314 dec_550_intr_evcnt.ev_count++; 315 #else 316 if (DEC_550_MAX_IRQ != INTRCNT_DEC_550_IRQ_LEN) 317 panic("dec_550 interrupt counter sizes inconsistent"); 318 intrcnt[INTRCNT_DEC_550_IRQ + irq]++; 319 #endif 320 321 if (!alpha_shared_intr_dispatch(dec_550_pci_intr, irq)) { 322 alpha_shared_intr_stray(dec_550_pci_intr, irq, 323 "dec 550 irq"); 324 if (dec_550_pci_intr[irq].intr_nstrays == 325 dec_550_pci_intr[irq].intr_maxstrays) 326 dec_550_intr_disable(irq); 327 } 328 return; 329 } 330 #if NSIO 331 if (vec >= 0x800) { 332 sio_iointr(framep, vec); 333 return; 334 } 335 #endif 336 panic("dec_550_iointr: weird vec 0x%x\n", vec); 337 } 338 339 void 340 dec_550_intr_enable(irq) 341 int irq; 342 { 343 u_int64_t imask; 344 int s; 345 346 #if 1 347 printf("dec_550_intr_enable: enabling %d\n", irq); 348 #endif 349 350 s = splhigh(); 351 alpha_mb(); 352 imask = *dec_550_int_mask_reg; 353 imask |= (1UL << irq); 354 *dec_550_int_mask_reg = imask; 355 alpha_mb(); 356 splx(s); 357 } 358 359 void 360 dec_550_intr_disable(irq) 361 int irq; 362 { 363 u_int64_t imask; 364 int s; 365 366 #if 1 367 printf("dec_550_intr_disable: disabling %d\n", irq); 368 #endif 369 370 s = splhigh(); 371 alpha_mb(); 372 imask = *dec_550_int_mask_reg; 373 imask &= ~(1UL << irq); 374 *dec_550_int_mask_reg = imask; 375 alpha_mb(); 376 splx(s); 377 } 378
Indexes created Mon Sep 29 15:09:53 GMT 2025