pci_550.c revision 1.6
1 /* $NetBSD: pci_550.c,v 1.6 1998/06/05 21:47:14 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center, and by Andrew Gallatin. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: pci_550.c,v 1.6 1998/06/05 21:47:14 thorpej Exp $"); 70 71 #include <sys/types.h> 72 #include <sys/param.h> 73 #include <sys/time.h> 74 #include <sys/systm.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/syslog.h> 79 80 #include <vm/vm.h> 81 82 #include <machine/autoconf.h> 83 #include <machine/rpb.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pciidereg.h> 88 #include <dev/pci/pciidevar.h> 89 90 #include <alpha/pci/ciareg.h> 91 #include <alpha/pci/ciavar.h> 92 93 #include <alpha/pci/pci_550.h> 94 95 #ifndef EVCNT_COUNTERS 96 #include <machine/intrcnt.h> 97 #endif 98 99 #include "sio.h" 100 #if NSIO 101 #include <alpha/pci/siovar.h> 102 #endif 103 104 int dec_550_intr_map __P((void *, pcitag_t, int, int, 105 pci_intr_handle_t *)); 106 const char *dec_550_intr_string __P((void *, pci_intr_handle_t)); 107 void *dec_550_intr_establish __P((void *, pci_intr_handle_t, 108 int, int (*func)(void *), void *)); 109 void dec_550_intr_disestablish __P((void *, void *)); 110 111 void *dec_550_pciide_compat_intr_establish __P((void *, struct device *, 112 struct pci_attach_args *, int, int (*)(void *), void *)); 113 114 #define DEC_550_PCI_IRQ_BEGIN 8 115 #define DEC_550_MAX_IRQ 48 116 #define PCI_STRAY_MAX 5 117 118 struct alpha_shared_intr *dec_550_pci_intr; 119 #ifdef EVCNT_COUNTERS 120 struct evcnt dec_550_intr_evcnt; 121 #endif 122 123 void dec_550_iointr __P((void *framep, unsigned long vec)); 124 void dec_550_intr_enable __P((int irq)); 125 void dec_550_intr_disable __P((int irq)); 126 127 u_int64_t *dec_550_int_mask_reg; 128 129 void 130 pci_550_pickintr(ccp) 131 struct cia_config *ccp; 132 { 133 bus_space_tag_t iot = &ccp->cc_iot; 134 pci_chipset_tag_t pc = &ccp->cc_pc; 135 int i; 136 137 pc->pc_intr_v = ccp; 138 pc->pc_intr_map = dec_550_intr_map; 139 pc->pc_intr_string = dec_550_intr_string; 140 pc->pc_intr_establish = dec_550_intr_establish; 141 pc->pc_intr_disestablish = dec_550_intr_disestablish; 142 143 pc->pc_pciide_compat_intr_establish = 144 dec_550_pciide_compat_intr_establish; 145 146 /* 147 * DEC 550's interrupts are enabled via the Pyxis interrupt 148 * mask register. 149 */ 150 dec_550_int_mask_reg = 151 (u_int64_t *)ALPHA_PHYS_TO_K0SEG(PYXIS_INT_MASK); 152 153 for (i = DEC_550_PCI_IRQ_BEGIN; i < DEC_550_MAX_IRQ; i++) 154 dec_550_intr_disable(i); 155 156 dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ); 157 for (i = 0; i < DEC_550_MAX_IRQ; i++) 158 alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i, 159 PCI_STRAY_MAX); 160 161 #if NSIO 162 sio_intr_setup(pc, iot); 163 #endif 164 165 set_iointr(dec_550_iointr); 166 } 167 168 int 169 dec_550_intr_map(ccv, bustag, buspin, line, ihp) 170 void *ccv; 171 pcitag_t bustag; 172 int buspin, line; 173 pci_intr_handle_t *ihp; 174 { 175 struct cia_config *ccp = ccv; 176 pci_chipset_tag_t pc = &ccp->cc_pc; 177 int bus, device, function; 178 179 if (buspin == 0) { 180 /* No IRQ used. */ 181 return 1; 182 } 183 if (buspin > 4) { 184 printf("dec_550_intr_map: bad interrupt pin %d\n", buspin); 185 return 1; 186 } 187 188 alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function); 189 190 /* 191 * There are two main variants of Miata: Miata 1 (Intel SIO) 192 * and Miata {1.5,2} (Cypress). 193 * 194 * The Miata 1 has a CMD PCI IDE wired to compatibility mode at 195 * device 4 of bus 0. This variant apparently also has the 196 * Pyxis DMA bug. 197 * 198 * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives 199 * on device 7 of bus 0. This device has PCI IDE wired to 200 * compatibility mode on functions 1 and 2. 201 * 202 * There will be no interrupt mapping for these devices, so just 203 * bail out now. 204 */ 205 if (bus == 0) { 206 if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 207 /* Miata 1 */ 208 if (device == 7) 209 panic("dec_550_intr_map: SIO device"); 210 else if (device == 4) 211 return (1); 212 } else { 213 /* Miata 1.5 or Miata 2 */ 214 if (device == 7) { 215 if (function == 0) 216 panic("dec_550_intr_map: SIO device"); 217 return (1); 218 } 219 } 220 } 221 222 /* 223 * The console places the interrupt mapping in the "line" value. 224 * A value of (char)-1 indicates there is no mapping. 225 */ 226 if (line == 0xff) { 227 printf("dec_550_intr_map: no mapping for %d/%d/%d\n", 228 bus, device, function); 229 return (1); 230 } 231 232 /* Account for the PCI interrupt offset. */ 233 line += DEC_550_PCI_IRQ_BEGIN; 234 235 if (line >= DEC_550_MAX_IRQ) 236 panic("dec_550_intr_map: dec 550 irq too large (%d)\n", 237 line); 238 239 *ihp = line; 240 return (0); 241 } 242 243 const char * 244 dec_550_intr_string(ccv, ih) 245 void *ccv; 246 pci_intr_handle_t ih; 247 { 248 #if 0 249 struct cia_config *ccp = ccv; 250 #endif 251 static char irqstr[16]; /* 12 + 2 + NULL + sanity */ 252 253 if (ih >= DEC_550_MAX_IRQ) 254 panic("dec_550_intr_string: bogus 550 IRQ 0x%x\n", ih); 255 sprintf(irqstr, "dec 550 irq %d", ih); 256 return (irqstr); 257 } 258 259 void * 260 dec_550_intr_establish(ccv, ih, level, func, arg) 261 void *ccv, *arg; 262 pci_intr_handle_t ih; 263 int level; 264 int (*func) __P((void *)); 265 { 266 #if 0 267 struct cia_config *ccp = ccv; 268 #endif 269 void *cookie; 270 271 if (ih >= DEC_550_MAX_IRQ) 272 panic("dec_550_intr_establish: bogus dec 550 IRQ 0x%x\n", ih); 273 274 cookie = alpha_shared_intr_establish(dec_550_pci_intr, ih, IST_LEVEL, 275 level, func, arg, "dec 550 irq"); 276 277 if (cookie != NULL && alpha_shared_intr_isactive(dec_550_pci_intr, ih)) 278 dec_550_intr_enable(ih); 279 return (cookie); 280 } 281 282 void 283 dec_550_intr_disestablish(ccv, cookie) 284 void *ccv, *cookie; 285 { 286 #if 0 287 struct cia_config *ccp = ccv; 288 #endif 289 290 panic("dec_550_intr_disestablish not implemented"); /* XXX */ 291 } 292 293 void * 294 dec_550_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 295 void *v; 296 struct device *dev; 297 struct pci_attach_args *pa; 298 int chan; 299 int (*func) __P((void *)); 300 void *arg; 301 { 302 pci_chipset_tag_t pc = pa->pa_pc; 303 void *cookie = NULL; 304 int bus, irq; 305 306 alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 307 308 /* 309 * If this isn't PCI bus #0, all bets are off. 310 */ 311 if (bus != 0) 312 return (NULL); 313 314 irq = PCIIDE_COMPAT_IRQ(chan); 315 #if NSIO 316 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 317 func, arg); 318 #endif 319 return (cookie); 320 } 321 322 void 323 dec_550_iointr(framep, vec) 324 void *framep; 325 unsigned long vec; 326 { 327 int irq; 328 329 if (vec >= 0x900) { 330 irq = ((vec - 0x900) >> 4) + DEC_550_PCI_IRQ_BEGIN; 331 332 if (irq >= DEC_550_MAX_IRQ) 333 panic("550_iointr: vec 0x%x out of range\n", vec); 334 335 #ifdef EVCNT_COUNTERS 336 dec_550_intr_evcnt.ev_count++; 337 #else 338 if (DEC_550_MAX_IRQ != INTRCNT_DEC_550_IRQ_LEN) 339 panic("dec_550 interrupt counter sizes inconsistent"); 340 intrcnt[INTRCNT_DEC_550_IRQ + irq]++; 341 #endif 342 343 if (!alpha_shared_intr_dispatch(dec_550_pci_intr, irq)) { 344 alpha_shared_intr_stray(dec_550_pci_intr, irq, 345 "dec 550 irq"); 346 if (dec_550_pci_intr[irq].intr_nstrays == 347 dec_550_pci_intr[irq].intr_maxstrays) 348 dec_550_intr_disable(irq); 349 } 350 return; 351 } 352 #if NSIO 353 if (vec >= 0x800) { 354 sio_iointr(framep, vec); 355 return; 356 } 357 #endif 358 panic("dec_550_iointr: weird vec 0x%x\n", vec); 359 } 360 361 void 362 dec_550_intr_enable(irq) 363 int irq; 364 { 365 u_int64_t imask; 366 int s; 367 368 #if 0 369 printf("dec_550_intr_enable: enabling %d\n", irq); 370 #endif 371 372 s = splhigh(); 373 alpha_mb(); 374 imask = *dec_550_int_mask_reg; 375 imask |= (1UL << irq); 376 *dec_550_int_mask_reg = imask; 377 alpha_mb(); 378 splx(s); 379 } 380 381 void 382 dec_550_intr_disable(irq) 383 int irq; 384 { 385 u_int64_t imask; 386 int s; 387 388 #if 0 389 printf("dec_550_intr_disable: disabling %d\n", irq); 390 #endif 391 392 s = splhigh(); 393 alpha_mb(); 394 imask = *dec_550_int_mask_reg; 395 imask &= ~(1UL << irq); 396 *dec_550_int_mask_reg = imask; 397 alpha_mb(); 398 splx(s); 399 } 400
Indexes created Mon Sep 29 21:09:56 GMT 2025