pci_550.c revision 1.7
1 /* $NetBSD: pci_550.c,v 1.7 1998/06/06 20:42:36 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center, and by Andrew Gallatin. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: pci_550.c,v 1.7 1998/06/06 20:42:36 thorpej Exp $"); 70 71 #include <sys/types.h> 72 #include <sys/param.h> 73 #include <sys/time.h> 74 #include <sys/systm.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/syslog.h> 79 80 #include <vm/vm.h> 81 82 #include <machine/autoconf.h> 83 #include <machine/rpb.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pciidereg.h> 88 #include <dev/pci/pciidevar.h> 89 90 #include <alpha/pci/ciareg.h> 91 #include <alpha/pci/ciavar.h> 92 93 #include <alpha/pci/pci_550.h> 94 95 #ifndef EVCNT_COUNTERS 96 #include <machine/intrcnt.h> 97 #endif 98 99 #include "sio.h" 100 #if NSIO 101 #include <alpha/pci/siovar.h> 102 #endif 103 104 int dec_550_intr_map __P((void *, pcitag_t, int, int, 105 pci_intr_handle_t *)); 106 const char *dec_550_intr_string __P((void *, pci_intr_handle_t)); 107 void *dec_550_intr_establish __P((void *, pci_intr_handle_t, 108 int, int (*func)(void *), void *)); 109 void dec_550_intr_disestablish __P((void *, void *)); 110 111 void *dec_550_pciide_compat_intr_establish __P((void *, struct device *, 112 struct pci_attach_args *, int, int (*)(void *), void *)); 113 114 #define DEC_550_PCI_IRQ_BEGIN 8 115 #define DEC_550_MAX_IRQ 48 116 #define PCI_STRAY_MAX 5 117 118 struct alpha_shared_intr *dec_550_pci_intr; 119 #ifdef EVCNT_COUNTERS 120 struct evcnt dec_550_intr_evcnt; 121 #endif 122 123 void dec_550_iointr __P((void *framep, unsigned long vec)); 124 void dec_550_intr_enable __P((int irq)); 125 void dec_550_intr_disable __P((int irq)); 126 127 void 128 pci_550_pickintr(ccp) 129 struct cia_config *ccp; 130 { 131 bus_space_tag_t iot = &ccp->cc_iot; 132 pci_chipset_tag_t pc = &ccp->cc_pc; 133 int i; 134 135 pc->pc_intr_v = ccp; 136 pc->pc_intr_map = dec_550_intr_map; 137 pc->pc_intr_string = dec_550_intr_string; 138 pc->pc_intr_establish = dec_550_intr_establish; 139 pc->pc_intr_disestablish = dec_550_intr_disestablish; 140 141 pc->pc_pciide_compat_intr_establish = 142 dec_550_pciide_compat_intr_establish; 143 144 /* 145 * DEC 550's interrupts are enabled via the Pyxis interrupt 146 * mask register. Nothing to map. 147 */ 148 149 for (i = DEC_550_PCI_IRQ_BEGIN; i < DEC_550_MAX_IRQ; i++) 150 dec_550_intr_disable(i); 151 152 dec_550_pci_intr = alpha_shared_intr_alloc(DEC_550_MAX_IRQ); 153 for (i = 0; i < DEC_550_MAX_IRQ; i++) 154 alpha_shared_intr_set_maxstrays(dec_550_pci_intr, i, 155 PCI_STRAY_MAX); 156 157 #if NSIO 158 sio_intr_setup(pc, iot); 159 #endif 160 161 set_iointr(dec_550_iointr); 162 } 163 164 int 165 dec_550_intr_map(ccv, bustag, buspin, line, ihp) 166 void *ccv; 167 pcitag_t bustag; 168 int buspin, line; 169 pci_intr_handle_t *ihp; 170 { 171 struct cia_config *ccp = ccv; 172 pci_chipset_tag_t pc = &ccp->cc_pc; 173 int bus, device, function; 174 175 if (buspin == 0) { 176 /* No IRQ used. */ 177 return 1; 178 } 179 if (buspin > 4) { 180 printf("dec_550_intr_map: bad interrupt pin %d\n", buspin); 181 return 1; 182 } 183 184 alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function); 185 186 /* 187 * There are two main variants of Miata: Miata 1 (Intel SIO) 188 * and Miata {1.5,2} (Cypress). 189 * 190 * The Miata 1 has a CMD PCI IDE wired to compatibility mode at 191 * device 4 of bus 0. This variant apparently also has the 192 * Pyxis DMA bug. 193 * 194 * On the Miata 1.5 and Miata 2, the Cypress PCI-ISA bridge lives 195 * on device 7 of bus 0. This device has PCI IDE wired to 196 * compatibility mode on functions 1 and 2. 197 * 198 * There will be no interrupt mapping for these devices, so just 199 * bail out now. 200 */ 201 if (bus == 0) { 202 if ((hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) { 203 /* Miata 1 */ 204 if (device == 7) 205 panic("dec_550_intr_map: SIO device"); 206 else if (device == 4) 207 return (1); 208 } else { 209 /* Miata 1.5 or Miata 2 */ 210 if (device == 7) { 211 if (function == 0) 212 panic("dec_550_intr_map: SIO device"); 213 return (1); 214 } 215 } 216 } 217 218 /* 219 * The console places the interrupt mapping in the "line" value. 220 * A value of (char)-1 indicates there is no mapping. 221 */ 222 if (line == 0xff) { 223 printf("dec_550_intr_map: no mapping for %d/%d/%d\n", 224 bus, device, function); 225 return (1); 226 } 227 228 /* Account for the PCI interrupt offset. */ 229 line += DEC_550_PCI_IRQ_BEGIN; 230 231 if (line >= DEC_550_MAX_IRQ) 232 panic("dec_550_intr_map: dec 550 irq too large (%d)\n", 233 line); 234 235 *ihp = line; 236 return (0); 237 } 238 239 const char * 240 dec_550_intr_string(ccv, ih) 241 void *ccv; 242 pci_intr_handle_t ih; 243 { 244 #if 0 245 struct cia_config *ccp = ccv; 246 #endif 247 static char irqstr[16]; /* 12 + 2 + NULL + sanity */ 248 249 if (ih >= DEC_550_MAX_IRQ) 250 panic("dec_550_intr_string: bogus 550 IRQ 0x%x\n", ih); 251 sprintf(irqstr, "dec 550 irq %d", ih); 252 return (irqstr); 253 } 254 255 void * 256 dec_550_intr_establish(ccv, ih, level, func, arg) 257 void *ccv, *arg; 258 pci_intr_handle_t ih; 259 int level; 260 int (*func) __P((void *)); 261 { 262 #if 0 263 struct cia_config *ccp = ccv; 264 #endif 265 void *cookie; 266 267 if (ih >= DEC_550_MAX_IRQ) 268 panic("dec_550_intr_establish: bogus dec 550 IRQ 0x%x\n", ih); 269 270 cookie = alpha_shared_intr_establish(dec_550_pci_intr, ih, IST_LEVEL, 271 level, func, arg, "dec 550 irq"); 272 273 if (cookie != NULL && alpha_shared_intr_isactive(dec_550_pci_intr, ih)) 274 dec_550_intr_enable(ih); 275 return (cookie); 276 } 277 278 void 279 dec_550_intr_disestablish(ccv, cookie) 280 void *ccv, *cookie; 281 { 282 #if 0 283 struct cia_config *ccp = ccv; 284 #endif 285 286 panic("dec_550_intr_disestablish not implemented"); /* XXX */ 287 } 288 289 void * 290 dec_550_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 291 void *v; 292 struct device *dev; 293 struct pci_attach_args *pa; 294 int chan; 295 int (*func) __P((void *)); 296 void *arg; 297 { 298 pci_chipset_tag_t pc = pa->pa_pc; 299 void *cookie = NULL; 300 int bus, irq; 301 302 alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 303 304 /* 305 * If this isn't PCI bus #0, all bets are off. 306 */ 307 if (bus != 0) 308 return (NULL); 309 310 irq = PCIIDE_COMPAT_IRQ(chan); 311 #if NSIO 312 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 313 func, arg); 314 #endif 315 return (cookie); 316 } 317 318 void 319 dec_550_iointr(framep, vec) 320 void *framep; 321 unsigned long vec; 322 { 323 int irq; 324 325 if (vec >= 0x900) { 326 irq = ((vec - 0x900) >> 4) + DEC_550_PCI_IRQ_BEGIN; 327 328 if (irq >= DEC_550_MAX_IRQ) 329 panic("550_iointr: vec 0x%x out of range\n", vec); 330 331 #ifdef EVCNT_COUNTERS 332 dec_550_intr_evcnt.ev_count++; 333 #else 334 if (DEC_550_MAX_IRQ != INTRCNT_DEC_550_IRQ_LEN) 335 panic("dec_550 interrupt counter sizes inconsistent"); 336 intrcnt[INTRCNT_DEC_550_IRQ + irq]++; 337 #endif 338 339 if (!alpha_shared_intr_dispatch(dec_550_pci_intr, irq)) { 340 alpha_shared_intr_stray(dec_550_pci_intr, irq, 341 "dec 550 irq"); 342 if (dec_550_pci_intr[irq].intr_nstrays == 343 dec_550_pci_intr[irq].intr_maxstrays) 344 dec_550_intr_disable(irq); 345 } 346 return; 347 } 348 #if NSIO 349 if (vec >= 0x800) { 350 sio_iointr(framep, vec); 351 return; 352 } 353 #endif 354 panic("dec_550_iointr: weird vec 0x%x\n", vec); 355 } 356 357 void 358 dec_550_intr_enable(irq) 359 int irq; 360 { 361 u_int64_t imask; 362 int s; 363 364 #if 0 365 printf("dec_550_intr_enable: enabling %d\n", irq); 366 #endif 367 368 s = splhigh(); 369 alpha_mb(); 370 imask = REGVAL64(PYXIS_INT_MASK); 371 imask |= (1UL << irq); 372 REGVAL64(PYXIS_INT_MASK) = imask; 373 alpha_mb(); 374 splx(s); 375 } 376 377 void 378 dec_550_intr_disable(irq) 379 int irq; 380 { 381 u_int64_t imask; 382 int s; 383 384 #if 0 385 printf("dec_550_intr_disable: disabling %d\n", irq); 386 #endif 387 388 s = splhigh(); 389 alpha_mb(); 390 imask = REGVAL64(PYXIS_INT_MASK); 391 imask &= ~(1UL << irq); 392 REGVAL64(PYXIS_INT_MASK) = imask; 393 alpha_mb(); 394 splx(s); 395 } 396
Indexes created Mon Sep 29 21:09:56 GMT 2025