1 /* $NetBSD: pci_eb164.c,v 1.50 2021/07/04 22:42:36 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 61 62 __KERNEL_RCSID(0, "$NetBSD: pci_eb164.c,v 1.50 2021/07/04 22:42:36 thorpej Exp $"); 63 64 #include <sys/types.h> 65 #include <sys/param.h> 66 #include <sys/time.h> 67 #include <sys/systm.h> 68 #include <sys/errno.h> 69 #include <sys/device.h> 70 #include <sys/syslog.h> 71 72 #include <machine/autoconf.h> 73 #include <machine/rpb.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 #include <dev/pci/pciidereg.h> 78 #include <dev/pci/pciidevar.h> 79 80 #include <alpha/pci/ciareg.h> 81 #include <alpha/pci/ciavar.h> 82 83 #include "sio.h" 84 #if NSIO 85 #include <alpha/pci/siovar.h> 86 #endif 87 88 static int dec_eb164_intr_map(const struct pci_attach_args *, 89 pci_intr_handle_t *); 90 91 #define EB164_SIO_IRQ 4 92 #define EB164_MAX_IRQ 24 93 #define PCI_STRAY_MAX 5 94 95 static bus_space_tag_t eb164_intrgate_iot; 96 static bus_space_handle_t eb164_intrgate_ioh; 97 98 /* See pci_eb164_intr.s */ 99 extern void eb164_intr_enable(pci_chipset_tag_t, int irq); 100 extern void eb164_intr_disable(pci_chipset_tag_t, int irq); 101 102 static void 103 pci_eb164_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt, 104 pci_chipset_tag_t pc) 105 { 106 struct cia_config *ccp = core; 107 int i; 108 109 pc->pc_intr_v = core; 110 pc->pc_intr_map = dec_eb164_intr_map; 111 pc->pc_intr_string = alpha_pci_generic_intr_string; 112 pc->pc_intr_evcnt = alpha_pci_generic_intr_evcnt; 113 pc->pc_intr_establish = alpha_pci_generic_intr_establish; 114 pc->pc_intr_disestablish = alpha_pci_generic_intr_disestablish; 115 116 pc->pc_pciide_compat_intr_establish = 117 sio_pciide_compat_intr_establish; 118 119 eb164_intrgate_iot = iot; 120 if (bus_space_map(eb164_intrgate_iot, 0x804, 3, 0, 121 &eb164_intrgate_ioh) != 0) 122 panic("pci_eb164_pickintr: couldn't map interrupt PLD"); 123 124 pc->pc_intr_desc = "eb164"; 125 pc->pc_vecbase = 0x900; 126 pc->pc_nirq = EB164_MAX_IRQ; 127 128 pc->pc_intr_enable = eb164_intr_enable; 129 pc->pc_intr_disable = eb164_intr_disable; 130 131 for (i = 0; i < EB164_MAX_IRQ; i++) { 132 eb164_intr_disable(pc, i); 133 } 134 135 /* 136 * Systems with a Pyxis seem to have problems with 137 * stray interrupts, so just ignore them. 138 */ 139 alpha_pci_intr_alloc(pc, 140 (ccp->cc_flags & CCF_ISPYXIS) ? 0 : PCI_STRAY_MAX); 141 142 #if NSIO 143 sio_intr_setup(pc, iot); 144 eb164_intr_enable(pc, EB164_SIO_IRQ); 145 #endif 146 } 147 ALPHA_PCI_INTR_INIT(ST_EB164, pci_eb164_pickintr) 148 149 static int 150 dec_eb164_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 151 { 152 pcitag_t bustag = pa->pa_intrtag; 153 int buspin = pa->pa_intrpin; 154 pci_chipset_tag_t pc = pa->pa_pc; 155 int bus, device, function; 156 uint64_t variation; 157 158 if (buspin == 0) { 159 /* No IRQ used. */ 160 return 1; 161 } 162 if (buspin < 0 || buspin > 4) { 163 printf("dec_eb164_intr_map: bad interrupt pin %d\n", buspin); 164 return 1; 165 } 166 167 pci_decompose_tag(pc, bustag, &bus, &device, &function); 168 169 variation = hwrpb->rpb_variation & SV_ST_MASK; 170 171 /* 172 * 173 * The AlphaPC 164 and AlphaPC 164LX have a CMD PCI IDE controller 174 * at bus 0 device 11. These are wired to compatibility mode, 175 * so do not map their interrupts. 176 * 177 * The AlphaPC 164SX has PCI IDE on functions 1 and 2 of the 178 * Cypress PCI-ISA bridge at bus 0 device 8. These, too, are 179 * wired to compatibility mode. 180 * 181 * Real EB164s have ISA IDE on the Super I/O chip. 182 */ 183 if (bus == 0) { 184 if (variation >= SV_ST_ALPHAPC164_366 && 185 variation <= SV_ST_ALPHAPC164LX_600) { 186 if (device == 8) 187 panic("dec_eb164_intr_map: SIO device"); 188 if (device == 11) 189 return (1); 190 } else if (variation >= SV_ST_ALPHAPC164SX_400 && 191 variation <= SV_ST_ALPHAPC164SX_600) { 192 if (device == 8) { 193 if (function == 0) 194 panic("dec_eb164_intr_map: SIO device"); 195 return (1); 196 } 197 } else { 198 if (device == 8) 199 panic("dec_eb164_intr_map: SIO device"); 200 } 201 } 202 203 return alpha_pci_generic_intr_map(pa, ihp); 204 } 205 206 #if 0 /* THIS DOES NOT WORK! see pci_eb164_intr.S. */ 207 uint8_t eb164_intr_mask[3] = { 0xff, 0xff, 0xff }; 208 209 void 210 eb164_intr_enable(pci_chipset_tag_t pc __unused, int irq) 211 { 212 int byte = (irq / 8), bit = (irq % 8); 213 214 #if 1 215 printf("eb164_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 216 #endif 217 eb164_intr_mask[byte] &= ~(1 << bit); 218 219 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 220 eb164_intr_mask[byte]); 221 } 222 223 void 224 eb164_intr_disable(pci_chipset_tag_t pc __unused, int irq) 225 { 226 int byte = (irq / 8), bit = (irq % 8); 227 228 #if 1 229 printf("eb164_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 230 #endif 231 eb164_intr_mask[byte] |= (1 << bit); 232 233 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 234 eb164_intr_mask[byte]); 235 } 236 #endif 237
Indexes created Mon Sep 22 05:09:51 GMT 2025