pci_eb164.c revision 1.25
1 /* $NetBSD: pci_eb164.c,v 1.25 2000/06/04 19:14:23 cgd Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: pci_eb164.c,v 1.25 2000/06/04 19:14:23 cgd Exp $"); 70 71 #include <sys/types.h> 72 #include <sys/param.h> 73 #include <sys/time.h> 74 #include <sys/systm.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/syslog.h> 79 80 #include <vm/vm.h> 81 82 #include <machine/autoconf.h> 83 #include <machine/rpb.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pciidereg.h> 88 #include <dev/pci/pciidevar.h> 89 90 #include <alpha/pci/ciareg.h> 91 #include <alpha/pci/ciavar.h> 92 93 #include <alpha/pci/pci_eb164.h> 94 95 #ifndef EVCNT_COUNTERS 96 #include <machine/intrcnt.h> 97 #endif 98 99 #include "sio.h" 100 #if NSIO 101 #include <alpha/pci/siovar.h> 102 #endif 103 104 int dec_eb164_intr_map __P((void *, pcitag_t, int, int, 105 pci_intr_handle_t *)); 106 const char *dec_eb164_intr_string __P((void *, pci_intr_handle_t)); 107 const struct evcnt *dec_eb164_intr_evcnt __P((void *, pci_intr_handle_t)); 108 void *dec_eb164_intr_establish __P((void *, pci_intr_handle_t, 109 int, int (*func)(void *), void *)); 110 void dec_eb164_intr_disestablish __P((void *, void *)); 111 112 void *dec_eb164_pciide_compat_intr_establish __P((void *, struct device *, 113 struct pci_attach_args *, int, int (*)(void *), void *)); 114 115 #define EB164_SIO_IRQ 4 116 #define EB164_MAX_IRQ 24 117 #define PCI_STRAY_MAX 5 118 119 struct alpha_shared_intr *eb164_pci_intr; 120 #ifdef EVCNT_COUNTERS 121 struct evcnt eb164_intr_evcnt; 122 #endif 123 124 bus_space_tag_t eb164_intrgate_iot; 125 bus_space_handle_t eb164_intrgate_ioh; 126 127 void eb164_iointr __P((void *framep, unsigned long vec)); 128 extern void eb164_intr_enable __P((int irq)); /* pci_eb164_intr.S */ 129 extern void eb164_intr_disable __P((int irq)); /* pci_eb164_intr.S */ 130 131 void 132 pci_eb164_pickintr(ccp) 133 struct cia_config *ccp; 134 { 135 bus_space_tag_t iot = &ccp->cc_iot; 136 pci_chipset_tag_t pc = &ccp->cc_pc; 137 int i; 138 139 pc->pc_intr_v = ccp; 140 pc->pc_intr_map = dec_eb164_intr_map; 141 pc->pc_intr_string = dec_eb164_intr_string; 142 pc->pc_intr_evcnt = dec_eb164_intr_evcnt; 143 pc->pc_intr_establish = dec_eb164_intr_establish; 144 pc->pc_intr_disestablish = dec_eb164_intr_disestablish; 145 146 pc->pc_pciide_compat_intr_establish = 147 dec_eb164_pciide_compat_intr_establish; 148 149 eb164_intrgate_iot = iot; 150 if (bus_space_map(eb164_intrgate_iot, 0x804, 3, 0, 151 &eb164_intrgate_ioh) != 0) 152 panic("pci_eb164_pickintr: couldn't map interrupt PLD"); 153 for (i = 0; i < EB164_MAX_IRQ; i++) 154 eb164_intr_disable(i); 155 156 eb164_pci_intr = alpha_shared_intr_alloc(EB164_MAX_IRQ); 157 for (i = 0; i < EB164_MAX_IRQ; i++) { 158 /* 159 * Systems with a Pyxis seem to have problems with 160 * stray interrupts, so just ignore them. Sigh, 161 * I hate buggy hardware. 162 */ 163 alpha_shared_intr_set_maxstrays(eb164_pci_intr, i, 164 (ccp->cc_flags & CCF_ISPYXIS) ? 0 : PCI_STRAY_MAX); 165 } 166 167 #if NSIO 168 sio_intr_setup(pc, iot); 169 eb164_intr_enable(EB164_SIO_IRQ); 170 #endif 171 172 set_iointr(eb164_iointr); 173 } 174 175 int 176 dec_eb164_intr_map(ccv, bustag, buspin, line, ihp) 177 void *ccv; 178 pcitag_t bustag; 179 int buspin, line; 180 pci_intr_handle_t *ihp; 181 { 182 struct cia_config *ccp = ccv; 183 pci_chipset_tag_t pc = &ccp->cc_pc; 184 int bus, device, function; 185 u_int64_t variation; 186 187 if (buspin == 0) { 188 /* No IRQ used. */ 189 return 1; 190 } 191 if (buspin > 4) { 192 printf("dec_eb164_intr_map: bad interrupt pin %d\n", buspin); 193 return 1; 194 } 195 196 alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function); 197 198 variation = hwrpb->rpb_variation & SV_ST_MASK; 199 200 /* 201 * 202 * The AlphaPC 164 and AlphaPC 164LX have a CMD PCI IDE controller 203 * at bus 0 device 11. These are wired to compatibility mode, 204 * so do not map their interrupts. 205 * 206 * The AlphaPC 164SX has PCI IDE on functions 1 and 2 of the 207 * Cypress PCI-ISA bridge at bus 0 device 8. These, too, are 208 * wired to compatibility mode. 209 * 210 * Real EB164s have ISA IDE on the Super I/O chip. 211 */ 212 if (bus == 0) { 213 if (variation >= SV_ST_ALPHAPC164_366 && 214 variation <= SV_ST_ALPHAPC164LX_600) { 215 if (device == 8) 216 panic("dec_eb164_intr_map: SIO device"); 217 if (device == 11) 218 return (1); 219 } else if (variation >= SV_ST_ALPHAPC164SX_400 && 220 variation <= SV_ST_ALPHAPC164SX_600) { 221 if (device == 8) { 222 if (function == 0) 223 panic("dec_eb164_intr_map: SIO device"); 224 return (1); 225 } 226 } else { 227 if (device == 8) 228 panic("dec_eb164_intr_map: SIO device"); 229 } 230 } 231 232 /* 233 * The console places the interrupt mapping in the "line" value. 234 * A value of (char)-1 indicates there is no mapping. 235 */ 236 if (line == 0xff) { 237 printf("dec_eb164_intr_map: no mapping for %d/%d/%d\n", 238 bus, device, function); 239 return (1); 240 } 241 242 if (line > EB164_MAX_IRQ) 243 panic("dec_eb164_intr_map: eb164 irq too large (%d)\n", 244 line); 245 246 *ihp = line; 247 return (0); 248 } 249 250 const char * 251 dec_eb164_intr_string(ccv, ih) 252 void *ccv; 253 pci_intr_handle_t ih; 254 { 255 #if 0 256 struct cia_config *ccp = ccv; 257 #endif 258 static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 259 260 if (ih > EB164_MAX_IRQ) 261 panic("dec_eb164_intr_string: bogus eb164 IRQ 0x%lx\n", ih); 262 sprintf(irqstr, "eb164 irq %ld", ih); 263 return (irqstr); 264 } 265 266 const struct evcnt * 267 dec_eb164_intr_evcnt(ccv, ih) 268 void *ccv; 269 pci_intr_handle_t ih; 270 { 271 #if 0 272 struct cia_config *ccp = ccv; 273 #endif 274 275 /* XXX for now, no evcnt parent reported */ 276 return (NULL); 277 } 278 279 void * 280 dec_eb164_intr_establish(ccv, ih, level, func, arg) 281 void *ccv, *arg; 282 pci_intr_handle_t ih; 283 int level; 284 int (*func) __P((void *)); 285 { 286 #if 0 287 struct cia_config *ccp = ccv; 288 #endif 289 void *cookie; 290 291 if (ih > EB164_MAX_IRQ) 292 panic("dec_eb164_intr_establish: bogus eb164 IRQ 0x%lx\n", ih); 293 294 cookie = alpha_shared_intr_establish(eb164_pci_intr, ih, IST_LEVEL, 295 level, func, arg, "eb164 irq"); 296 297 if (cookie != NULL && alpha_shared_intr_isactive(eb164_pci_intr, ih)) 298 eb164_intr_enable(ih); 299 return (cookie); 300 } 301 302 void 303 dec_eb164_intr_disestablish(ccv, cookie) 304 void *ccv, *cookie; 305 { 306 #if 0 307 struct cia_config *ccp = ccv; 308 #endif 309 struct alpha_shared_intrhand *ih = cookie; 310 unsigned int irq = ih->ih_num; 311 int s; 312 313 s = splhigh(); 314 315 alpha_shared_intr_disestablish(eb164_pci_intr, cookie, 316 "eb164 irq"); 317 if (alpha_shared_intr_isactive(eb164_pci_intr, irq) == 0) { 318 eb164_intr_disable(irq); 319 alpha_shared_intr_set_dfltsharetype(eb164_pci_intr, irq, 320 IST_NONE); 321 } 322 323 splx(s); 324 } 325 326 void * 327 dec_eb164_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 328 void *v; 329 struct device *dev; 330 struct pci_attach_args *pa; 331 int chan; 332 int (*func) __P((void *)); 333 void *arg; 334 { 335 pci_chipset_tag_t pc = pa->pa_pc; 336 void *cookie = NULL; 337 int bus, irq; 338 339 alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 340 341 /* 342 * If this isn't PCI bus #0, all bets are off. 343 */ 344 if (bus != 0) 345 return (NULL); 346 347 irq = PCIIDE_COMPAT_IRQ(chan); 348 #if NSIO 349 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 350 func, arg); 351 #endif 352 return (cookie); 353 } 354 355 void 356 eb164_iointr(framep, vec) 357 void *framep; 358 unsigned long vec; 359 { 360 int irq; 361 362 if (vec >= 0x900) { 363 if (vec >= 0x900 + (EB164_MAX_IRQ << 4)) 364 panic("eb164_iointr: vec 0x%lx out of range\n", vec); 365 irq = (vec - 0x900) >> 4; 366 367 #ifdef EVCNT_COUNTERS 368 eb164_intr_evcnt.ev_count++; 369 #else 370 if (EB164_MAX_IRQ != INTRCNT_EB164_IRQ_LEN) 371 panic("eb164 interrupt counter sizes inconsistent"); 372 intrcnt[INTRCNT_EB164_IRQ + irq]++; 373 #endif 374 375 if (!alpha_shared_intr_dispatch(eb164_pci_intr, irq)) { 376 alpha_shared_intr_stray(eb164_pci_intr, irq, 377 "eb164 irq"); 378 if (ALPHA_SHARED_INTR_DISABLE(eb164_pci_intr, irq)) 379 eb164_intr_disable(irq); 380 } 381 return; 382 } 383 #if NSIO 384 if (vec >= 0x800) { 385 sio_iointr(framep, vec); 386 return; 387 } 388 #endif 389 panic("eb164_iointr: weird vec 0x%lx\n", vec); 390 } 391 392 #if 0 /* THIS DOES NOT WORK! see pci_eb164_intr.S. */ 393 u_int8_t eb164_intr_mask[3] = { 0xff, 0xff, 0xff }; 394 395 void 396 eb164_intr_enable(irq) 397 int irq; 398 { 399 int byte = (irq / 8), bit = (irq % 8); 400 401 #if 1 402 printf("eb164_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 403 #endif 404 eb164_intr_mask[byte] &= ~(1 << bit); 405 406 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 407 eb164_intr_mask[byte]); 408 } 409 410 void 411 eb164_intr_disable(irq) 412 int irq; 413 { 414 int byte = (irq / 8), bit = (irq % 8); 415 416 #if 1 417 printf("eb164_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 418 #endif 419 eb164_intr_mask[byte] |= (1 << bit); 420 421 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 422 eb164_intr_mask[byte]); 423 } 424 #endif 425
Indexes created Tue Sep 30 17:09:57 GMT 2025