pci_eb164.c revision 1.28
1 /* $NetBSD: pci_eb164.c,v 1.28 2000/06/29 08:58:48 mrg Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: pci_eb164.c,v 1.28 2000/06/29 08:58:48 mrg Exp $"); 70 71 #include <sys/types.h> 72 #include <sys/param.h> 73 #include <sys/time.h> 74 #include <sys/systm.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/syslog.h> 79 80 #include <uvm/uvm_extern.h> 81 82 #include <machine/autoconf.h> 83 #include <machine/rpb.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pciidereg.h> 88 #include <dev/pci/pciidevar.h> 89 90 #include <alpha/pci/ciareg.h> 91 #include <alpha/pci/ciavar.h> 92 93 #include <alpha/pci/pci_eb164.h> 94 95 #include "sio.h" 96 #if NSIO 97 #include <alpha/pci/siovar.h> 98 #endif 99 100 int dec_eb164_intr_map __P((void *, pcitag_t, int, int, 101 pci_intr_handle_t *)); 102 const char *dec_eb164_intr_string __P((void *, pci_intr_handle_t)); 103 const struct evcnt *dec_eb164_intr_evcnt __P((void *, pci_intr_handle_t)); 104 void *dec_eb164_intr_establish __P((void *, pci_intr_handle_t, 105 int, int (*func)(void *), void *)); 106 void dec_eb164_intr_disestablish __P((void *, void *)); 107 108 void *dec_eb164_pciide_compat_intr_establish __P((void *, struct device *, 109 struct pci_attach_args *, int, int (*)(void *), void *)); 110 111 #define EB164_SIO_IRQ 4 112 #define EB164_MAX_IRQ 24 113 #define PCI_STRAY_MAX 5 114 115 struct alpha_shared_intr *eb164_pci_intr; 116 117 bus_space_tag_t eb164_intrgate_iot; 118 bus_space_handle_t eb164_intrgate_ioh; 119 120 void eb164_iointr __P((void *framep, unsigned long vec)); 121 extern void eb164_intr_enable __P((int irq)); /* pci_eb164_intr.S */ 122 extern void eb164_intr_disable __P((int irq)); /* pci_eb164_intr.S */ 123 124 void 125 pci_eb164_pickintr(ccp) 126 struct cia_config *ccp; 127 { 128 bus_space_tag_t iot = &ccp->cc_iot; 129 pci_chipset_tag_t pc = &ccp->cc_pc; 130 char *cp; 131 int i; 132 133 pc->pc_intr_v = ccp; 134 pc->pc_intr_map = dec_eb164_intr_map; 135 pc->pc_intr_string = dec_eb164_intr_string; 136 pc->pc_intr_evcnt = dec_eb164_intr_evcnt; 137 pc->pc_intr_establish = dec_eb164_intr_establish; 138 pc->pc_intr_disestablish = dec_eb164_intr_disestablish; 139 140 pc->pc_pciide_compat_intr_establish = 141 dec_eb164_pciide_compat_intr_establish; 142 143 eb164_intrgate_iot = iot; 144 if (bus_space_map(eb164_intrgate_iot, 0x804, 3, 0, 145 &eb164_intrgate_ioh) != 0) 146 panic("pci_eb164_pickintr: couldn't map interrupt PLD"); 147 for (i = 0; i < EB164_MAX_IRQ; i++) 148 eb164_intr_disable(i); 149 150 eb164_pci_intr = alpha_shared_intr_alloc(EB164_MAX_IRQ, 8); 151 for (i = 0; i < EB164_MAX_IRQ; i++) { 152 /* 153 * Systems with a Pyxis seem to have problems with 154 * stray interrupts, so just ignore them. Sigh, 155 * I hate buggy hardware. 156 */ 157 alpha_shared_intr_set_maxstrays(eb164_pci_intr, i, 158 (ccp->cc_flags & CCF_ISPYXIS) ? 0 : PCI_STRAY_MAX); 159 160 cp = alpha_shared_intr_string(eb164_pci_intr, i); 161 sprintf(cp, "irq %d", i); 162 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 163 eb164_pci_intr, i), EVCNT_TYPE_INTR, NULL, 164 "eb164", cp); 165 } 166 167 #if NSIO 168 sio_intr_setup(pc, iot); 169 eb164_intr_enable(EB164_SIO_IRQ); 170 #endif 171 172 set_iointr(eb164_iointr); 173 } 174 175 int 176 dec_eb164_intr_map(ccv, bustag, buspin, line, ihp) 177 void *ccv; 178 pcitag_t bustag; 179 int buspin, line; 180 pci_intr_handle_t *ihp; 181 { 182 struct cia_config *ccp = ccv; 183 pci_chipset_tag_t pc = &ccp->cc_pc; 184 int bus, device, function; 185 u_int64_t variation; 186 187 if (buspin == 0) { 188 /* No IRQ used. */ 189 return 1; 190 } 191 if (buspin > 4) { 192 printf("dec_eb164_intr_map: bad interrupt pin %d\n", buspin); 193 return 1; 194 } 195 196 alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function); 197 198 variation = hwrpb->rpb_variation & SV_ST_MASK; 199 200 /* 201 * 202 * The AlphaPC 164 and AlphaPC 164LX have a CMD PCI IDE controller 203 * at bus 0 device 11. These are wired to compatibility mode, 204 * so do not map their interrupts. 205 * 206 * The AlphaPC 164SX has PCI IDE on functions 1 and 2 of the 207 * Cypress PCI-ISA bridge at bus 0 device 8. These, too, are 208 * wired to compatibility mode. 209 * 210 * Real EB164s have ISA IDE on the Super I/O chip. 211 */ 212 if (bus == 0) { 213 if (variation >= SV_ST_ALPHAPC164_366 && 214 variation <= SV_ST_ALPHAPC164LX_600) { 215 if (device == 8) 216 panic("dec_eb164_intr_map: SIO device"); 217 if (device == 11) 218 return (1); 219 } else if (variation >= SV_ST_ALPHAPC164SX_400 && 220 variation <= SV_ST_ALPHAPC164SX_600) { 221 if (device == 8) { 222 if (function == 0) 223 panic("dec_eb164_intr_map: SIO device"); 224 return (1); 225 } 226 } else { 227 if (device == 8) 228 panic("dec_eb164_intr_map: SIO device"); 229 } 230 } 231 232 /* 233 * The console places the interrupt mapping in the "line" value. 234 * A value of (char)-1 indicates there is no mapping. 235 */ 236 if (line == 0xff) { 237 printf("dec_eb164_intr_map: no mapping for %d/%d/%d\n", 238 bus, device, function); 239 return (1); 240 } 241 242 if (line > EB164_MAX_IRQ) 243 panic("dec_eb164_intr_map: eb164 irq too large (%d)\n", 244 line); 245 246 *ihp = line; 247 return (0); 248 } 249 250 const char * 251 dec_eb164_intr_string(ccv, ih) 252 void *ccv; 253 pci_intr_handle_t ih; 254 { 255 #if 0 256 struct cia_config *ccp = ccv; 257 #endif 258 static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 259 260 if (ih > EB164_MAX_IRQ) 261 panic("dec_eb164_intr_string: bogus eb164 IRQ 0x%lx\n", ih); 262 sprintf(irqstr, "eb164 irq %ld", ih); 263 return (irqstr); 264 } 265 266 const struct evcnt * 267 dec_eb164_intr_evcnt(ccv, ih) 268 void *ccv; 269 pci_intr_handle_t ih; 270 { 271 #if 0 272 struct cia_config *ccp = ccv; 273 #endif 274 275 if (ih > EB164_MAX_IRQ) 276 panic("dec_eb164_intr_string: bogus eb164 IRQ 0x%lx\n", ih); 277 return (alpha_shared_intr_evcnt(eb164_pci_intr, ih)); 278 } 279 280 void * 281 dec_eb164_intr_establish(ccv, ih, level, func, arg) 282 void *ccv, *arg; 283 pci_intr_handle_t ih; 284 int level; 285 int (*func) __P((void *)); 286 { 287 #if 0 288 struct cia_config *ccp = ccv; 289 #endif 290 void *cookie; 291 292 if (ih > EB164_MAX_IRQ) 293 panic("dec_eb164_intr_establish: bogus eb164 IRQ 0x%lx\n", ih); 294 295 cookie = alpha_shared_intr_establish(eb164_pci_intr, ih, IST_LEVEL, 296 level, func, arg, "eb164 irq"); 297 298 if (cookie != NULL && alpha_shared_intr_isactive(eb164_pci_intr, ih)) 299 eb164_intr_enable(ih); 300 return (cookie); 301 } 302 303 void 304 dec_eb164_intr_disestablish(ccv, cookie) 305 void *ccv, *cookie; 306 { 307 #if 0 308 struct cia_config *ccp = ccv; 309 #endif 310 struct alpha_shared_intrhand *ih = cookie; 311 unsigned int irq = ih->ih_num; 312 int s; 313 314 s = splhigh(); 315 316 alpha_shared_intr_disestablish(eb164_pci_intr, cookie, 317 "eb164 irq"); 318 if (alpha_shared_intr_isactive(eb164_pci_intr, irq) == 0) { 319 eb164_intr_disable(irq); 320 alpha_shared_intr_set_dfltsharetype(eb164_pci_intr, irq, 321 IST_NONE); 322 } 323 324 splx(s); 325 } 326 327 void * 328 dec_eb164_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 329 void *v; 330 struct device *dev; 331 struct pci_attach_args *pa; 332 int chan; 333 int (*func) __P((void *)); 334 void *arg; 335 { 336 pci_chipset_tag_t pc = pa->pa_pc; 337 void *cookie = NULL; 338 int bus, irq; 339 340 alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 341 342 /* 343 * If this isn't PCI bus #0, all bets are off. 344 */ 345 if (bus != 0) 346 return (NULL); 347 348 irq = PCIIDE_COMPAT_IRQ(chan); 349 #if NSIO 350 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 351 func, arg); 352 if (cookie == NULL) 353 return (NULL); 354 printf("%s: %s channel interrupting at %s\n", dev->dv_xname, 355 PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq)); 356 #endif 357 return (cookie); 358 } 359 360 void 361 eb164_iointr(framep, vec) 362 void *framep; 363 unsigned long vec; 364 { 365 int irq; 366 367 if (vec >= 0x900) { 368 if (vec >= 0x900 + (EB164_MAX_IRQ << 4)) 369 panic("eb164_iointr: vec 0x%lx out of range\n", vec); 370 irq = (vec - 0x900) >> 4; 371 372 if (!alpha_shared_intr_dispatch(eb164_pci_intr, irq)) { 373 alpha_shared_intr_stray(eb164_pci_intr, irq, 374 "eb164 irq"); 375 if (ALPHA_SHARED_INTR_DISABLE(eb164_pci_intr, irq)) 376 eb164_intr_disable(irq); 377 } 378 return; 379 } 380 #if NSIO 381 if (vec >= 0x800) { 382 sio_iointr(framep, vec); 383 return; 384 } 385 #endif 386 panic("eb164_iointr: weird vec 0x%lx\n", vec); 387 } 388 389 #if 0 /* THIS DOES NOT WORK! see pci_eb164_intr.S. */ 390 u_int8_t eb164_intr_mask[3] = { 0xff, 0xff, 0xff }; 391 392 void 393 eb164_intr_enable(irq) 394 int irq; 395 { 396 int byte = (irq / 8), bit = (irq % 8); 397 398 #if 1 399 printf("eb164_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 400 #endif 401 eb164_intr_mask[byte] &= ~(1 << bit); 402 403 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 404 eb164_intr_mask[byte]); 405 } 406 407 void 408 eb164_intr_disable(irq) 409 int irq; 410 { 411 int byte = (irq / 8), bit = (irq % 8); 412 413 #if 1 414 printf("eb164_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 415 #endif 416 eb164_intr_mask[byte] |= (1 << bit); 417 418 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 419 eb164_intr_mask[byte]); 420 } 421 #endif 422
Indexes created Tue Sep 30 11:09:46 GMT 2025