pci_eb164.c revision 1.29
1 /* $NetBSD: pci_eb164.c,v 1.29 2000/12/28 22:59:07 sommerfeld Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: pci_eb164.c,v 1.29 2000/12/28 22:59:07 sommerfeld Exp $"); 70 71 #include <sys/types.h> 72 #include <sys/param.h> 73 #include <sys/time.h> 74 #include <sys/systm.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/syslog.h> 79 80 #include <uvm/uvm_extern.h> 81 82 #include <machine/autoconf.h> 83 #include <machine/rpb.h> 84 85 #include <dev/pci/pcireg.h> 86 #include <dev/pci/pcivar.h> 87 #include <dev/pci/pciidereg.h> 88 #include <dev/pci/pciidevar.h> 89 90 #include <alpha/pci/ciareg.h> 91 #include <alpha/pci/ciavar.h> 92 93 #include <alpha/pci/pci_eb164.h> 94 95 #include "sio.h" 96 #if NSIO 97 #include <alpha/pci/siovar.h> 98 #endif 99 100 int dec_eb164_intr_map __P((struct pci_attach_args *, pci_intr_handle_t *)); 101 const char *dec_eb164_intr_string __P((void *, pci_intr_handle_t)); 102 const struct evcnt *dec_eb164_intr_evcnt __P((void *, pci_intr_handle_t)); 103 void *dec_eb164_intr_establish __P((void *, pci_intr_handle_t, 104 int, int (*func)(void *), void *)); 105 void dec_eb164_intr_disestablish __P((void *, void *)); 106 107 void *dec_eb164_pciide_compat_intr_establish __P((void *, struct device *, 108 struct pci_attach_args *, int, int (*)(void *), void *)); 109 110 #define EB164_SIO_IRQ 4 111 #define EB164_MAX_IRQ 24 112 #define PCI_STRAY_MAX 5 113 114 struct alpha_shared_intr *eb164_pci_intr; 115 116 bus_space_tag_t eb164_intrgate_iot; 117 bus_space_handle_t eb164_intrgate_ioh; 118 119 void eb164_iointr __P((void *framep, unsigned long vec)); 120 extern void eb164_intr_enable __P((int irq)); /* pci_eb164_intr.S */ 121 extern void eb164_intr_disable __P((int irq)); /* pci_eb164_intr.S */ 122 123 void 124 pci_eb164_pickintr(ccp) 125 struct cia_config *ccp; 126 { 127 bus_space_tag_t iot = &ccp->cc_iot; 128 pci_chipset_tag_t pc = &ccp->cc_pc; 129 char *cp; 130 int i; 131 132 pc->pc_intr_v = ccp; 133 pc->pc_intr_map = dec_eb164_intr_map; 134 pc->pc_intr_string = dec_eb164_intr_string; 135 pc->pc_intr_evcnt = dec_eb164_intr_evcnt; 136 pc->pc_intr_establish = dec_eb164_intr_establish; 137 pc->pc_intr_disestablish = dec_eb164_intr_disestablish; 138 139 pc->pc_pciide_compat_intr_establish = 140 dec_eb164_pciide_compat_intr_establish; 141 142 eb164_intrgate_iot = iot; 143 if (bus_space_map(eb164_intrgate_iot, 0x804, 3, 0, 144 &eb164_intrgate_ioh) != 0) 145 panic("pci_eb164_pickintr: couldn't map interrupt PLD"); 146 for (i = 0; i < EB164_MAX_IRQ; i++) 147 eb164_intr_disable(i); 148 149 eb164_pci_intr = alpha_shared_intr_alloc(EB164_MAX_IRQ, 8); 150 for (i = 0; i < EB164_MAX_IRQ; i++) { 151 /* 152 * Systems with a Pyxis seem to have problems with 153 * stray interrupts, so just ignore them. Sigh, 154 * I hate buggy hardware. 155 */ 156 alpha_shared_intr_set_maxstrays(eb164_pci_intr, i, 157 (ccp->cc_flags & CCF_ISPYXIS) ? 0 : PCI_STRAY_MAX); 158 159 cp = alpha_shared_intr_string(eb164_pci_intr, i); 160 sprintf(cp, "irq %d", i); 161 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 162 eb164_pci_intr, i), EVCNT_TYPE_INTR, NULL, 163 "eb164", cp); 164 } 165 166 #if NSIO 167 sio_intr_setup(pc, iot); 168 eb164_intr_enable(EB164_SIO_IRQ); 169 #endif 170 171 set_iointr(eb164_iointr); 172 } 173 174 int 175 dec_eb164_intr_map(pa, ihp) 176 struct pci_attach_args *pa; 177 pci_intr_handle_t *ihp; 178 { 179 pcitag_t bustag = pa->pa_intrtag; 180 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 181 pci_chipset_tag_t pc = pa->pa_pc; 182 int bus, device, function; 183 u_int64_t variation; 184 185 if (buspin == 0) { 186 /* No IRQ used. */ 187 return 1; 188 } 189 if (buspin > 4) { 190 printf("dec_eb164_intr_map: bad interrupt pin %d\n", buspin); 191 return 1; 192 } 193 194 alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function); 195 196 variation = hwrpb->rpb_variation & SV_ST_MASK; 197 198 /* 199 * 200 * The AlphaPC 164 and AlphaPC 164LX have a CMD PCI IDE controller 201 * at bus 0 device 11. These are wired to compatibility mode, 202 * so do not map their interrupts. 203 * 204 * The AlphaPC 164SX has PCI IDE on functions 1 and 2 of the 205 * Cypress PCI-ISA bridge at bus 0 device 8. These, too, are 206 * wired to compatibility mode. 207 * 208 * Real EB164s have ISA IDE on the Super I/O chip. 209 */ 210 if (bus == 0) { 211 if (variation >= SV_ST_ALPHAPC164_366 && 212 variation <= SV_ST_ALPHAPC164LX_600) { 213 if (device == 8) 214 panic("dec_eb164_intr_map: SIO device"); 215 if (device == 11) 216 return (1); 217 } else if (variation >= SV_ST_ALPHAPC164SX_400 && 218 variation <= SV_ST_ALPHAPC164SX_600) { 219 if (device == 8) { 220 if (function == 0) 221 panic("dec_eb164_intr_map: SIO device"); 222 return (1); 223 } 224 } else { 225 if (device == 8) 226 panic("dec_eb164_intr_map: SIO device"); 227 } 228 } 229 230 /* 231 * The console places the interrupt mapping in the "line" value. 232 * A value of (char)-1 indicates there is no mapping. 233 */ 234 if (line == 0xff) { 235 printf("dec_eb164_intr_map: no mapping for %d/%d/%d\n", 236 bus, device, function); 237 return (1); 238 } 239 240 if (line > EB164_MAX_IRQ) 241 panic("dec_eb164_intr_map: eb164 irq too large (%d)\n", 242 line); 243 244 *ihp = line; 245 return (0); 246 } 247 248 const char * 249 dec_eb164_intr_string(ccv, ih) 250 void *ccv; 251 pci_intr_handle_t ih; 252 { 253 #if 0 254 struct cia_config *ccp = ccv; 255 #endif 256 static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 257 258 if (ih > EB164_MAX_IRQ) 259 panic("dec_eb164_intr_string: bogus eb164 IRQ 0x%lx\n", ih); 260 sprintf(irqstr, "eb164 irq %ld", ih); 261 return (irqstr); 262 } 263 264 const struct evcnt * 265 dec_eb164_intr_evcnt(ccv, ih) 266 void *ccv; 267 pci_intr_handle_t ih; 268 { 269 #if 0 270 struct cia_config *ccp = ccv; 271 #endif 272 273 if (ih > EB164_MAX_IRQ) 274 panic("dec_eb164_intr_string: bogus eb164 IRQ 0x%lx\n", ih); 275 return (alpha_shared_intr_evcnt(eb164_pci_intr, ih)); 276 } 277 278 void * 279 dec_eb164_intr_establish(ccv, ih, level, func, arg) 280 void *ccv, *arg; 281 pci_intr_handle_t ih; 282 int level; 283 int (*func) __P((void *)); 284 { 285 #if 0 286 struct cia_config *ccp = ccv; 287 #endif 288 void *cookie; 289 290 if (ih > EB164_MAX_IRQ) 291 panic("dec_eb164_intr_establish: bogus eb164 IRQ 0x%lx\n", ih); 292 293 cookie = alpha_shared_intr_establish(eb164_pci_intr, ih, IST_LEVEL, 294 level, func, arg, "eb164 irq"); 295 296 if (cookie != NULL && alpha_shared_intr_isactive(eb164_pci_intr, ih)) 297 eb164_intr_enable(ih); 298 return (cookie); 299 } 300 301 void 302 dec_eb164_intr_disestablish(ccv, cookie) 303 void *ccv, *cookie; 304 { 305 #if 0 306 struct cia_config *ccp = ccv; 307 #endif 308 struct alpha_shared_intrhand *ih = cookie; 309 unsigned int irq = ih->ih_num; 310 int s; 311 312 s = splhigh(); 313 314 alpha_shared_intr_disestablish(eb164_pci_intr, cookie, 315 "eb164 irq"); 316 if (alpha_shared_intr_isactive(eb164_pci_intr, irq) == 0) { 317 eb164_intr_disable(irq); 318 alpha_shared_intr_set_dfltsharetype(eb164_pci_intr, irq, 319 IST_NONE); 320 } 321 322 splx(s); 323 } 324 325 void * 326 dec_eb164_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 327 void *v; 328 struct device *dev; 329 struct pci_attach_args *pa; 330 int chan; 331 int (*func) __P((void *)); 332 void *arg; 333 { 334 pci_chipset_tag_t pc = pa->pa_pc; 335 void *cookie = NULL; 336 int bus, irq; 337 338 alpha_pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 339 340 /* 341 * If this isn't PCI bus #0, all bets are off. 342 */ 343 if (bus != 0) 344 return (NULL); 345 346 irq = PCIIDE_COMPAT_IRQ(chan); 347 #if NSIO 348 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 349 func, arg); 350 if (cookie == NULL) 351 return (NULL); 352 printf("%s: %s channel interrupting at %s\n", dev->dv_xname, 353 PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq)); 354 #endif 355 return (cookie); 356 } 357 358 void 359 eb164_iointr(framep, vec) 360 void *framep; 361 unsigned long vec; 362 { 363 int irq; 364 365 if (vec >= 0x900) { 366 if (vec >= 0x900 + (EB164_MAX_IRQ << 4)) 367 panic("eb164_iointr: vec 0x%lx out of range\n", vec); 368 irq = (vec - 0x900) >> 4; 369 370 if (!alpha_shared_intr_dispatch(eb164_pci_intr, irq)) { 371 alpha_shared_intr_stray(eb164_pci_intr, irq, 372 "eb164 irq"); 373 if (ALPHA_SHARED_INTR_DISABLE(eb164_pci_intr, irq)) 374 eb164_intr_disable(irq); 375 } 376 return; 377 } 378 #if NSIO 379 if (vec >= 0x800) { 380 sio_iointr(framep, vec); 381 return; 382 } 383 #endif 384 panic("eb164_iointr: weird vec 0x%lx\n", vec); 385 } 386 387 #if 0 /* THIS DOES NOT WORK! see pci_eb164_intr.S. */ 388 u_int8_t eb164_intr_mask[3] = { 0xff, 0xff, 0xff }; 389 390 void 391 eb164_intr_enable(irq) 392 int irq; 393 { 394 int byte = (irq / 8), bit = (irq % 8); 395 396 #if 1 397 printf("eb164_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 398 #endif 399 eb164_intr_mask[byte] &= ~(1 << bit); 400 401 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 402 eb164_intr_mask[byte]); 403 } 404 405 void 406 eb164_intr_disable(irq) 407 int irq; 408 { 409 int byte = (irq / 8), bit = (irq % 8); 410 411 #if 1 412 printf("eb164_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 413 #endif 414 eb164_intr_mask[byte] |= (1 << bit); 415 416 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 417 eb164_intr_mask[byte]); 418 } 419 #endif 420
Indexes created Mon Sep 29 21:09:56 GMT 2025