pci_eb164.c revision 1.37
1 /* $NetBSD: pci_eb164.c,v 1.37 2009/03/14 14:45:53 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 61 62 __KERNEL_RCSID(0, "$NetBSD: pci_eb164.c,v 1.37 2009/03/14 14:45:53 dsl Exp $"); 63 64 #include <sys/types.h> 65 #include <sys/param.h> 66 #include <sys/time.h> 67 #include <sys/systm.h> 68 #include <sys/errno.h> 69 #include <sys/malloc.h> 70 #include <sys/device.h> 71 #include <sys/syslog.h> 72 73 #include <uvm/uvm_extern.h> 74 75 #include <machine/autoconf.h> 76 #include <machine/rpb.h> 77 78 #include <dev/pci/pcireg.h> 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pciidereg.h> 81 #include <dev/pci/pciidevar.h> 82 83 #include <alpha/pci/ciareg.h> 84 #include <alpha/pci/ciavar.h> 85 86 #include <alpha/pci/pci_eb164.h> 87 88 #include "sio.h" 89 #if NSIO 90 #include <alpha/pci/siovar.h> 91 #endif 92 93 int dec_eb164_intr_map(struct pci_attach_args *, pci_intr_handle_t *); 94 const char *dec_eb164_intr_string(void *, pci_intr_handle_t); 95 const struct evcnt *dec_eb164_intr_evcnt(void *, pci_intr_handle_t); 96 void *dec_eb164_intr_establish(void *, pci_intr_handle_t, 97 int, int (*func)(void *), void *); 98 void dec_eb164_intr_disestablish(void *, void *); 99 100 void *dec_eb164_pciide_compat_intr_establish(void *, struct device *, 101 struct pci_attach_args *, int, int (*)(void *), void *); 102 103 #define EB164_SIO_IRQ 4 104 #define EB164_MAX_IRQ 24 105 #define PCI_STRAY_MAX 5 106 107 struct alpha_shared_intr *eb164_pci_intr; 108 109 bus_space_tag_t eb164_intrgate_iot; 110 bus_space_handle_t eb164_intrgate_ioh; 111 112 void eb164_iointr(void *arg, unsigned long vec); 113 extern void eb164_intr_enable(int irq); /* pci_eb164_intr.S */ 114 extern void eb164_intr_disable(int irq); /* pci_eb164_intr.S */ 115 116 void 117 pci_eb164_pickintr(ccp) 118 struct cia_config *ccp; 119 { 120 bus_space_tag_t iot = &ccp->cc_iot; 121 pci_chipset_tag_t pc = &ccp->cc_pc; 122 char *cp; 123 int i; 124 125 pc->pc_intr_v = ccp; 126 pc->pc_intr_map = dec_eb164_intr_map; 127 pc->pc_intr_string = dec_eb164_intr_string; 128 pc->pc_intr_evcnt = dec_eb164_intr_evcnt; 129 pc->pc_intr_establish = dec_eb164_intr_establish; 130 pc->pc_intr_disestablish = dec_eb164_intr_disestablish; 131 132 pc->pc_pciide_compat_intr_establish = 133 dec_eb164_pciide_compat_intr_establish; 134 135 eb164_intrgate_iot = iot; 136 if (bus_space_map(eb164_intrgate_iot, 0x804, 3, 0, 137 &eb164_intrgate_ioh) != 0) 138 panic("pci_eb164_pickintr: couldn't map interrupt PLD"); 139 for (i = 0; i < EB164_MAX_IRQ; i++) 140 eb164_intr_disable(i); 141 142 eb164_pci_intr = alpha_shared_intr_alloc(EB164_MAX_IRQ, 8); 143 for (i = 0; i < EB164_MAX_IRQ; i++) { 144 /* 145 * Systems with a Pyxis seem to have problems with 146 * stray interrupts, so just ignore them. Sigh, 147 * I hate buggy hardware. 148 */ 149 alpha_shared_intr_set_maxstrays(eb164_pci_intr, i, 150 (ccp->cc_flags & CCF_ISPYXIS) ? 0 : PCI_STRAY_MAX); 151 152 cp = alpha_shared_intr_string(eb164_pci_intr, i); 153 sprintf(cp, "irq %d", i); 154 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 155 eb164_pci_intr, i), EVCNT_TYPE_INTR, NULL, 156 "eb164", cp); 157 } 158 159 #if NSIO 160 sio_intr_setup(pc, iot); 161 eb164_intr_enable(EB164_SIO_IRQ); 162 #endif 163 } 164 165 int 166 dec_eb164_intr_map(pa, ihp) 167 struct pci_attach_args *pa; 168 pci_intr_handle_t *ihp; 169 { 170 pcitag_t bustag = pa->pa_intrtag; 171 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 172 pci_chipset_tag_t pc = pa->pa_pc; 173 int bus, device, function; 174 u_int64_t variation; 175 176 if (buspin == 0) { 177 /* No IRQ used. */ 178 return 1; 179 } 180 if (buspin > 4) { 181 printf("dec_eb164_intr_map: bad interrupt pin %d\n", buspin); 182 return 1; 183 } 184 185 pci_decompose_tag(pc, bustag, &bus, &device, &function); 186 187 variation = hwrpb->rpb_variation & SV_ST_MASK; 188 189 /* 190 * 191 * The AlphaPC 164 and AlphaPC 164LX have a CMD PCI IDE controller 192 * at bus 0 device 11. These are wired to compatibility mode, 193 * so do not map their interrupts. 194 * 195 * The AlphaPC 164SX has PCI IDE on functions 1 and 2 of the 196 * Cypress PCI-ISA bridge at bus 0 device 8. These, too, are 197 * wired to compatibility mode. 198 * 199 * Real EB164s have ISA IDE on the Super I/O chip. 200 */ 201 if (bus == 0) { 202 if (variation >= SV_ST_ALPHAPC164_366 && 203 variation <= SV_ST_ALPHAPC164LX_600) { 204 if (device == 8) 205 panic("dec_eb164_intr_map: SIO device"); 206 if (device == 11) 207 return (1); 208 } else if (variation >= SV_ST_ALPHAPC164SX_400 && 209 variation <= SV_ST_ALPHAPC164SX_600) { 210 if (device == 8) { 211 if (function == 0) 212 panic("dec_eb164_intr_map: SIO device"); 213 return (1); 214 } 215 } else { 216 if (device == 8) 217 panic("dec_eb164_intr_map: SIO device"); 218 } 219 } 220 221 /* 222 * The console places the interrupt mapping in the "line" value. 223 * A value of (char)-1 indicates there is no mapping. 224 */ 225 if (line == 0xff) { 226 printf("dec_eb164_intr_map: no mapping for %d/%d/%d\n", 227 bus, device, function); 228 return (1); 229 } 230 231 if (line > EB164_MAX_IRQ) 232 panic("dec_eb164_intr_map: eb164 irq too large (%d)", 233 line); 234 235 *ihp = line; 236 return (0); 237 } 238 239 const char * 240 dec_eb164_intr_string(ccv, ih) 241 void *ccv; 242 pci_intr_handle_t ih; 243 { 244 #if 0 245 struct cia_config *ccp = ccv; 246 #endif 247 static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 248 249 if (ih > EB164_MAX_IRQ) 250 panic("dec_eb164_intr_string: bogus eb164 IRQ 0x%lx", ih); 251 sprintf(irqstr, "eb164 irq %ld", ih); 252 return (irqstr); 253 } 254 255 const struct evcnt * 256 dec_eb164_intr_evcnt(ccv, ih) 257 void *ccv; 258 pci_intr_handle_t ih; 259 { 260 #if 0 261 struct cia_config *ccp = ccv; 262 #endif 263 264 if (ih > EB164_MAX_IRQ) 265 panic("dec_eb164_intr_string: bogus eb164 IRQ 0x%lx", ih); 266 return (alpha_shared_intr_evcnt(eb164_pci_intr, ih)); 267 } 268 269 void * 270 dec_eb164_intr_establish(ccv, ih, level, func, arg) 271 void *ccv, *arg; 272 pci_intr_handle_t ih; 273 int level; 274 int (*func)(void *); 275 { 276 #if 0 277 struct cia_config *ccp = ccv; 278 #endif 279 void *cookie; 280 281 if (ih > EB164_MAX_IRQ) 282 panic("dec_eb164_intr_establish: bogus eb164 IRQ 0x%lx", ih); 283 284 cookie = alpha_shared_intr_establish(eb164_pci_intr, ih, IST_LEVEL, 285 level, func, arg, "eb164 irq"); 286 287 if (cookie != NULL && 288 alpha_shared_intr_firstactive(eb164_pci_intr, ih)) { 289 scb_set(0x900 + SCB_IDXTOVEC(ih), eb164_iointr, NULL, 290 level); 291 eb164_intr_enable(ih); 292 } 293 return (cookie); 294 } 295 296 void 297 dec_eb164_intr_disestablish(ccv, cookie) 298 void *ccv, *cookie; 299 { 300 #if 0 301 struct cia_config *ccp = ccv; 302 #endif 303 struct alpha_shared_intrhand *ih = cookie; 304 unsigned int irq = ih->ih_num; 305 int s; 306 307 s = splhigh(); 308 309 alpha_shared_intr_disestablish(eb164_pci_intr, cookie, 310 "eb164 irq"); 311 if (alpha_shared_intr_isactive(eb164_pci_intr, irq) == 0) { 312 eb164_intr_disable(irq); 313 alpha_shared_intr_set_dfltsharetype(eb164_pci_intr, irq, 314 IST_NONE); 315 scb_free(0x900 + SCB_IDXTOVEC(irq)); 316 } 317 318 splx(s); 319 } 320 321 void * 322 dec_eb164_pciide_compat_intr_establish(v, dev, pa, chan, func, arg) 323 void *v; 324 struct device *dev; 325 struct pci_attach_args *pa; 326 int chan; 327 int (*func)(void *); 328 void *arg; 329 { 330 pci_chipset_tag_t pc = pa->pa_pc; 331 void *cookie = NULL; 332 int bus, irq; 333 334 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 335 336 /* 337 * If this isn't PCI bus #0, all bets are off. 338 */ 339 if (bus != 0) 340 return (NULL); 341 342 irq = PCIIDE_COMPAT_IRQ(chan); 343 #if NSIO 344 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 345 func, arg); 346 if (cookie == NULL) 347 return (NULL); 348 printf("%s: %s channel interrupting at %s\n", dev->dv_xname, 349 PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq)); 350 #endif 351 return (cookie); 352 } 353 354 void 355 eb164_iointr(arg, vec) 356 void *arg; 357 unsigned long vec; 358 { 359 int irq; 360 361 irq = SCB_VECTOIDX(vec - 0x900); 362 363 if (!alpha_shared_intr_dispatch(eb164_pci_intr, irq)) { 364 alpha_shared_intr_stray(eb164_pci_intr, irq, 365 "eb164 irq"); 366 if (ALPHA_SHARED_INTR_DISABLE(eb164_pci_intr, irq)) 367 eb164_intr_disable(irq); 368 } else 369 alpha_shared_intr_reset_strays(eb164_pci_intr, irq); 370 } 371 372 #if 0 /* THIS DOES NOT WORK! see pci_eb164_intr.S. */ 373 u_int8_t eb164_intr_mask[3] = { 0xff, 0xff, 0xff }; 374 375 void 376 eb164_intr_enable(irq) 377 int irq; 378 { 379 int byte = (irq / 8), bit = (irq % 8); 380 381 #if 1 382 printf("eb164_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 383 #endif 384 eb164_intr_mask[byte] &= ~(1 << bit); 385 386 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 387 eb164_intr_mask[byte]); 388 } 389 390 void 391 eb164_intr_disable(irq) 392 int irq; 393 { 394 int byte = (irq / 8), bit = (irq % 8); 395 396 #if 1 397 printf("eb164_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 398 #endif 399 eb164_intr_mask[byte] |= (1 << bit); 400 401 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 402 eb164_intr_mask[byte]); 403 } 404 #endif 405
Indexes created Tue Sep 30 11:09:46 GMT 2025