pci_eb164.c revision 1.45
1 /* $NetBSD: pci_eb164.c,v 1.45 2014/03/21 16:39:29 christos Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 61 62 __KERNEL_RCSID(0, "$NetBSD: pci_eb164.c,v 1.45 2014/03/21 16:39:29 christos Exp $"); 63 64 #include <sys/types.h> 65 #include <sys/param.h> 66 #include <sys/time.h> 67 #include <sys/systm.h> 68 #include <sys/errno.h> 69 #include <sys/malloc.h> 70 #include <sys/device.h> 71 #include <sys/syslog.h> 72 73 #include <machine/autoconf.h> 74 #include <machine/rpb.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pciidereg.h> 79 #include <dev/pci/pciidevar.h> 80 81 #include <alpha/pci/ciareg.h> 82 #include <alpha/pci/ciavar.h> 83 84 #include <alpha/pci/pci_eb164.h> 85 86 #include "sio.h" 87 #if NSIO 88 #include <alpha/pci/siovar.h> 89 #endif 90 91 int dec_eb164_intr_map(const struct pci_attach_args *, pci_intr_handle_t *); 92 const char *dec_eb164_intr_string(void *, pci_intr_handle_t, char *, size_t); 93 const struct evcnt *dec_eb164_intr_evcnt(void *, pci_intr_handle_t); 94 void *dec_eb164_intr_establish(void *, pci_intr_handle_t, 95 int, int (*func)(void *), void *); 96 void dec_eb164_intr_disestablish(void *, void *); 97 98 void *dec_eb164_pciide_compat_intr_establish(void *, device_t, 99 const struct pci_attach_args *, int, int (*)(void *), void *); 100 101 #define EB164_SIO_IRQ 4 102 #define EB164_MAX_IRQ 24 103 #define PCI_STRAY_MAX 5 104 105 struct alpha_shared_intr *eb164_pci_intr; 106 107 bus_space_tag_t eb164_intrgate_iot; 108 bus_space_handle_t eb164_intrgate_ioh; 109 110 void eb164_iointr(void *arg, unsigned long vec); 111 extern void eb164_intr_enable(int irq); /* pci_eb164_intr.S */ 112 extern void eb164_intr_disable(int irq); /* pci_eb164_intr.S */ 113 114 void 115 pci_eb164_pickintr(struct cia_config *ccp) 116 { 117 bus_space_tag_t iot = &ccp->cc_iot; 118 pci_chipset_tag_t pc = &ccp->cc_pc; 119 char *cp; 120 int i; 121 122 pc->pc_intr_v = ccp; 123 pc->pc_intr_map = dec_eb164_intr_map; 124 pc->pc_intr_string = dec_eb164_intr_string; 125 pc->pc_intr_evcnt = dec_eb164_intr_evcnt; 126 pc->pc_intr_establish = dec_eb164_intr_establish; 127 pc->pc_intr_disestablish = dec_eb164_intr_disestablish; 128 129 pc->pc_pciide_compat_intr_establish = 130 dec_eb164_pciide_compat_intr_establish; 131 132 eb164_intrgate_iot = iot; 133 if (bus_space_map(eb164_intrgate_iot, 0x804, 3, 0, 134 &eb164_intrgate_ioh) != 0) 135 panic("pci_eb164_pickintr: couldn't map interrupt PLD"); 136 for (i = 0; i < EB164_MAX_IRQ; i++) 137 eb164_intr_disable(i); 138 139 #define PCI_EB164_IRQ_STR 8 140 eb164_pci_intr = alpha_shared_intr_alloc(EB164_MAX_IRQ, 141 PCI_EB164_IRQ_STR); 142 for (i = 0; i < EB164_MAX_IRQ; i++) { 143 /* 144 * Systems with a Pyxis seem to have problems with 145 * stray interrupts, so just ignore them. Sigh, 146 * I hate buggy hardware. 147 */ 148 alpha_shared_intr_set_maxstrays(eb164_pci_intr, i, 149 (ccp->cc_flags & CCF_ISPYXIS) ? 0 : PCI_STRAY_MAX); 150 151 cp = alpha_shared_intr_string(eb164_pci_intr, i); 152 snprintf(cp, PCI_EB164_IRQ_STR, "irq %d", i); 153 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 154 eb164_pci_intr, i), EVCNT_TYPE_INTR, NULL, 155 "eb164", cp); 156 } 157 158 #if NSIO 159 sio_intr_setup(pc, iot); 160 eb164_intr_enable(EB164_SIO_IRQ); 161 #endif 162 } 163 164 int 165 dec_eb164_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 166 { 167 pcitag_t bustag = pa->pa_intrtag; 168 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 169 pci_chipset_tag_t pc = pa->pa_pc; 170 int bus, device, function; 171 uint64_t variation; 172 173 if (buspin == 0) { 174 /* No IRQ used. */ 175 return 1; 176 } 177 if (buspin > 4) { 178 printf("dec_eb164_intr_map: bad interrupt pin %d\n", buspin); 179 return 1; 180 } 181 182 pci_decompose_tag(pc, bustag, &bus, &device, &function); 183 184 variation = hwrpb->rpb_variation & SV_ST_MASK; 185 186 /* 187 * 188 * The AlphaPC 164 and AlphaPC 164LX have a CMD PCI IDE controller 189 * at bus 0 device 11. These are wired to compatibility mode, 190 * so do not map their interrupts. 191 * 192 * The AlphaPC 164SX has PCI IDE on functions 1 and 2 of the 193 * Cypress PCI-ISA bridge at bus 0 device 8. These, too, are 194 * wired to compatibility mode. 195 * 196 * Real EB164s have ISA IDE on the Super I/O chip. 197 */ 198 if (bus == 0) { 199 if (variation >= SV_ST_ALPHAPC164_366 && 200 variation <= SV_ST_ALPHAPC164LX_600) { 201 if (device == 8) 202 panic("dec_eb164_intr_map: SIO device"); 203 if (device == 11) 204 return (1); 205 } else if (variation >= SV_ST_ALPHAPC164SX_400 && 206 variation <= SV_ST_ALPHAPC164SX_600) { 207 if (device == 8) { 208 if (function == 0) 209 panic("dec_eb164_intr_map: SIO device"); 210 return (1); 211 } 212 } else { 213 if (device == 8) 214 panic("dec_eb164_intr_map: SIO device"); 215 } 216 } 217 218 /* 219 * The console places the interrupt mapping in the "line" value. 220 * A value of (char)-1 indicates there is no mapping. 221 */ 222 if (line == 0xff) { 223 printf("dec_eb164_intr_map: no mapping for %d/%d/%d\n", 224 bus, device, function); 225 return (1); 226 } 227 228 if (line > EB164_MAX_IRQ) 229 panic("dec_eb164_intr_map: eb164 irq too large (%d)", 230 line); 231 232 *ihp = line; 233 return (0); 234 } 235 236 const char * 237 dec_eb164_intr_string(void *ccv, pci_intr_handle_t ih, char *buf, size_t len) 238 { 239 #if 0 240 struct cia_config *ccp = ccv; 241 #endif 242 243 if (ih > EB164_MAX_IRQ) 244 panic("%s: bogus eb164 IRQ 0x%lx", __func__, ih); 245 snprintf(buf, len, "eb164 irq %ld", ih); 246 return buf; 247 } 248 249 const struct evcnt * 250 dec_eb164_intr_evcnt(void *ccv, pci_intr_handle_t ih) 251 { 252 #if 0 253 struct cia_config *ccp = ccv; 254 #endif 255 256 if (ih > EB164_MAX_IRQ) 257 panic("%s: bogus eb164 IRQ 0x%lx", __func__, ih); 258 return (alpha_shared_intr_evcnt(eb164_pci_intr, ih)); 259 } 260 261 void * 262 dec_eb164_intr_establish(void *ccv, pci_intr_handle_t ih, int level, int (*func)(void *), void *arg) 263 { 264 #if 0 265 struct cia_config *ccp = ccv; 266 #endif 267 void *cookie; 268 269 if (ih > EB164_MAX_IRQ) 270 panic("dec_eb164_intr_establish: bogus eb164 IRQ 0x%lx", ih); 271 272 cookie = alpha_shared_intr_establish(eb164_pci_intr, ih, IST_LEVEL, 273 level, func, arg, "eb164 irq"); 274 275 if (cookie != NULL && 276 alpha_shared_intr_firstactive(eb164_pci_intr, ih)) { 277 scb_set(0x900 + SCB_IDXTOVEC(ih), eb164_iointr, NULL, 278 level); 279 eb164_intr_enable(ih); 280 } 281 return (cookie); 282 } 283 284 void 285 dec_eb164_intr_disestablish(void *ccv, void *cookie) 286 { 287 #if 0 288 struct cia_config *ccp = ccv; 289 #endif 290 struct alpha_shared_intrhand *ih = cookie; 291 unsigned int irq = ih->ih_num; 292 int s; 293 294 s = splhigh(); 295 296 alpha_shared_intr_disestablish(eb164_pci_intr, cookie, 297 "eb164 irq"); 298 if (alpha_shared_intr_isactive(eb164_pci_intr, irq) == 0) { 299 eb164_intr_disable(irq); 300 alpha_shared_intr_set_dfltsharetype(eb164_pci_intr, irq, 301 IST_NONE); 302 scb_free(0x900 + SCB_IDXTOVEC(irq)); 303 } 304 305 splx(s); 306 } 307 308 void * 309 dec_eb164_pciide_compat_intr_establish(void *v, device_t dev, 310 const struct pci_attach_args *pa, int chan, int (*func)(void *), void *arg) 311 { 312 pci_chipset_tag_t pc = pa->pa_pc; 313 void *cookie = NULL; 314 int bus, irq; 315 char buf[64]; 316 317 pci_decompose_tag(pc, pa->pa_tag, &bus, NULL, NULL); 318 319 /* 320 * If this isn't PCI bus #0, all bets are off. 321 */ 322 if (bus != 0) 323 return (NULL); 324 325 irq = PCIIDE_COMPAT_IRQ(chan); 326 #if NSIO 327 cookie = sio_intr_establish(NULL /*XXX*/, irq, IST_EDGE, IPL_BIO, 328 func, arg); 329 if (cookie == NULL) 330 return (NULL); 331 aprint_normal_dev(dev, "%s channel interrupting at %s\n", 332 PCIIDE_CHANNEL_NAME(chan), sio_intr_string(NULL /*XXX*/, irq, 333 buf, sizeof(buf))); 334 #endif 335 return (cookie); 336 } 337 338 void 339 eb164_iointr(void *arg, unsigned long vec) 340 { 341 int irq; 342 343 irq = SCB_VECTOIDX(vec - 0x900); 344 345 if (!alpha_shared_intr_dispatch(eb164_pci_intr, irq)) { 346 alpha_shared_intr_stray(eb164_pci_intr, irq, 347 "eb164 irq"); 348 if (ALPHA_SHARED_INTR_DISABLE(eb164_pci_intr, irq)) 349 eb164_intr_disable(irq); 350 } else 351 alpha_shared_intr_reset_strays(eb164_pci_intr, irq); 352 } 353 354 #if 0 /* THIS DOES NOT WORK! see pci_eb164_intr.S. */ 355 uint8_t eb164_intr_mask[3] = { 0xff, 0xff, 0xff }; 356 357 void 358 eb164_intr_enable(int irq) 359 { 360 int byte = (irq / 8), bit = (irq % 8); 361 362 #if 1 363 printf("eb164_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 364 #endif 365 eb164_intr_mask[byte] &= ~(1 << bit); 366 367 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 368 eb164_intr_mask[byte]); 369 } 370 371 void 372 eb164_intr_disable(int irq) 373 { 374 int byte = (irq / 8), bit = (irq % 8); 375 376 #if 1 377 printf("eb164_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 378 #endif 379 eb164_intr_mask[byte] |= (1 << bit); 380 381 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 382 eb164_intr_mask[byte]); 383 } 384 #endif 385
Indexes created Mon Sep 29 21:09:56 GMT 2025