pci_eb164.c revision 1.49
1 /* $NetBSD: pci_eb164.c,v 1.49 2021/07/04 22:36:43 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 61 62 __KERNEL_RCSID(0, "$NetBSD: pci_eb164.c,v 1.49 2021/07/04 22:36:43 thorpej Exp $"); 63 64 #include <sys/types.h> 65 #include <sys/param.h> 66 #include <sys/time.h> 67 #include <sys/systm.h> 68 #include <sys/errno.h> 69 #include <sys/malloc.h> 70 #include <sys/device.h> 71 #include <sys/syslog.h> 72 73 #include <machine/autoconf.h> 74 #include <machine/rpb.h> 75 76 #include <dev/pci/pcireg.h> 77 #include <dev/pci/pcivar.h> 78 #include <dev/pci/pciidereg.h> 79 #include <dev/pci/pciidevar.h> 80 81 #include <alpha/pci/ciareg.h> 82 #include <alpha/pci/ciavar.h> 83 84 #include "sio.h" 85 #if NSIO 86 #include <alpha/pci/siovar.h> 87 #endif 88 89 static int dec_eb164_intr_map(const struct pci_attach_args *, 90 pci_intr_handle_t *); 91 92 #define EB164_SIO_IRQ 4 93 #define EB164_MAX_IRQ 24 94 #define PCI_STRAY_MAX 5 95 96 static bus_space_tag_t eb164_intrgate_iot; 97 static bus_space_handle_t eb164_intrgate_ioh; 98 99 /* See pci_eb164_intr.s */ 100 extern void eb164_intr_enable(pci_chipset_tag_t, int irq); 101 extern void eb164_intr_disable(pci_chipset_tag_t, int irq); 102 103 static void 104 pci_eb164_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt, 105 pci_chipset_tag_t pc) 106 { 107 struct cia_config *ccp = core; 108 int i; 109 110 pc->pc_intr_v = core; 111 pc->pc_intr_map = dec_eb164_intr_map; 112 pc->pc_intr_string = alpha_pci_generic_intr_string; 113 pc->pc_intr_evcnt = alpha_pci_generic_intr_evcnt; 114 pc->pc_intr_establish = alpha_pci_generic_intr_establish; 115 pc->pc_intr_disestablish = alpha_pci_generic_intr_disestablish; 116 117 pc->pc_pciide_compat_intr_establish = 118 sio_pciide_compat_intr_establish; 119 120 eb164_intrgate_iot = iot; 121 if (bus_space_map(eb164_intrgate_iot, 0x804, 3, 0, 122 &eb164_intrgate_ioh) != 0) 123 panic("pci_eb164_pickintr: couldn't map interrupt PLD"); 124 125 pc->pc_intr_desc = "eb164"; 126 pc->pc_vecbase = 0x900; 127 pc->pc_nirq = EB164_MAX_IRQ; 128 129 pc->pc_intr_enable = eb164_intr_enable; 130 pc->pc_intr_disable = eb164_intr_disable; 131 132 for (i = 0; i < EB164_MAX_IRQ; i++) { 133 eb164_intr_disable(pc, i); 134 } 135 136 /* 137 * Systems with a Pyxis seem to have problems with 138 * stray interrupts, so just ignore them. 139 */ 140 alpha_pci_intr_alloc(pc, 141 (ccp->cc_flags & CCF_ISPYXIS) ? 0 : PCI_STRAY_MAX); 142 143 #if NSIO 144 sio_intr_setup(pc, iot); 145 eb164_intr_enable(pc, EB164_SIO_IRQ); 146 #endif 147 } 148 ALPHA_PCI_INTR_INIT(ST_EB164, pci_eb164_pickintr) 149 150 static int 151 dec_eb164_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 152 { 153 pcitag_t bustag = pa->pa_intrtag; 154 int buspin = pa->pa_intrpin; 155 pci_chipset_tag_t pc = pa->pa_pc; 156 int bus, device, function; 157 uint64_t variation; 158 159 if (buspin == 0) { 160 /* No IRQ used. */ 161 return 1; 162 } 163 if (buspin < 0 || buspin > 4) { 164 printf("dec_eb164_intr_map: bad interrupt pin %d\n", buspin); 165 return 1; 166 } 167 168 pci_decompose_tag(pc, bustag, &bus, &device, &function); 169 170 variation = hwrpb->rpb_variation & SV_ST_MASK; 171 172 /* 173 * 174 * The AlphaPC 164 and AlphaPC 164LX have a CMD PCI IDE controller 175 * at bus 0 device 11. These are wired to compatibility mode, 176 * so do not map their interrupts. 177 * 178 * The AlphaPC 164SX has PCI IDE on functions 1 and 2 of the 179 * Cypress PCI-ISA bridge at bus 0 device 8. These, too, are 180 * wired to compatibility mode. 181 * 182 * Real EB164s have ISA IDE on the Super I/O chip. 183 */ 184 if (bus == 0) { 185 if (variation >= SV_ST_ALPHAPC164_366 && 186 variation <= SV_ST_ALPHAPC164LX_600) { 187 if (device == 8) 188 panic("dec_eb164_intr_map: SIO device"); 189 if (device == 11) 190 return (1); 191 } else if (variation >= SV_ST_ALPHAPC164SX_400 && 192 variation <= SV_ST_ALPHAPC164SX_600) { 193 if (device == 8) { 194 if (function == 0) 195 panic("dec_eb164_intr_map: SIO device"); 196 return (1); 197 } 198 } else { 199 if (device == 8) 200 panic("dec_eb164_intr_map: SIO device"); 201 } 202 } 203 204 return alpha_pci_generic_intr_map(pa, ihp); 205 } 206 207 #if 0 /* THIS DOES NOT WORK! see pci_eb164_intr.S. */ 208 uint8_t eb164_intr_mask[3] = { 0xff, 0xff, 0xff }; 209 210 void 211 eb164_intr_enable(pci_chipset_tag_t pc __unused, int irq) 212 { 213 int byte = (irq / 8), bit = (irq % 8); 214 215 #if 1 216 printf("eb164_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 217 #endif 218 eb164_intr_mask[byte] &= ~(1 << bit); 219 220 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 221 eb164_intr_mask[byte]); 222 } 223 224 void 225 eb164_intr_disable(pci_chipset_tag_t pc __unused, int irq) 226 { 227 int byte = (irq / 8), bit = (irq % 8); 228 229 #if 1 230 printf("eb164_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 231 #endif 232 eb164_intr_mask[byte] |= (1 << bit); 233 234 bus_space_write_1(eb164_intrgate_iot, eb164_intrgate_ioh, byte, 235 eb164_intr_mask[byte]); 236 } 237 #endif 238
Indexes created Mon Sep 29 15:09:53 GMT 2025