1 /* $NetBSD: pci_eb64plus.c,v 1.29 2021/07/04 22:42:36 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 61 62 __KERNEL_RCSID(0, "$NetBSD: pci_eb64plus.c,v 1.29 2021/07/04 22:42:36 thorpej Exp $"); 63 64 #include <sys/types.h> 65 #include <sys/param.h> 66 #include <sys/time.h> 67 #include <sys/systm.h> 68 #include <sys/errno.h> 69 #include <sys/device.h> 70 #include <sys/syslog.h> 71 72 #include <machine/autoconf.h> 73 #include <machine/rpb.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 78 #include <alpha/pci/apecsreg.h> 79 #include <alpha/pci/apecsvar.h> 80 81 #include "sio.h" 82 #if NSIO 83 #include <alpha/pci/siovar.h> 84 #endif 85 86 #define EB64PLUS_MAX_IRQ 32 87 #define PCI_STRAY_MAX 5 88 89 static bus_space_tag_t eb64plus_intrgate_iot; 90 static bus_space_handle_t eb64plus_intrgate_ioh; 91 92 /* See pci_eb64plus_intr.s */ 93 extern void eb64plus_intr_enable(pci_chipset_tag_t, int irq); 94 extern void eb64plus_intr_disable(pci_chipset_tag_t, int irq); 95 96 static void 97 pci_eb64plus_pickintr(void *core, bus_space_tag_t iot, bus_space_tag_t memt, 98 pci_chipset_tag_t pc) 99 { 100 int i; 101 102 pc->pc_intr_v = core; 103 pc->pc_intr_map = alpha_pci_generic_intr_map; 104 pc->pc_intr_string = alpha_pci_generic_intr_string; 105 pc->pc_intr_evcnt = alpha_pci_generic_intr_evcnt; 106 pc->pc_intr_establish = alpha_pci_generic_intr_establish; 107 pc->pc_intr_disestablish = alpha_pci_generic_intr_disestablish; 108 109 /* Not supported on the EB64+. */ 110 pc->pc_pciide_compat_intr_establish = NULL; 111 112 eb64plus_intrgate_iot = iot; 113 if (bus_space_map(eb64plus_intrgate_iot, 0x804, 3, 0, 114 &eb64plus_intrgate_ioh) != 0) 115 panic("pci_eb64plus_pickintr: couldn't map interrupt PLD"); 116 117 pc->pc_intr_desc = "eb64+"; 118 pc->pc_vecbase = 0x900; 119 pc->pc_nirq = EB64PLUS_MAX_IRQ; 120 121 pc->pc_intr_enable = eb64plus_intr_enable; 122 pc->pc_intr_disable = eb64plus_intr_disable; 123 124 for (i = 0; i < EB64PLUS_MAX_IRQ; i++) { 125 eb64plus_intr_disable(pc, i); 126 } 127 128 alpha_pci_intr_alloc(pc, PCI_STRAY_MAX); 129 130 #if NSIO 131 sio_intr_setup(pc, iot); 132 #endif 133 } 134 ALPHA_PCI_INTR_INIT(ST_EB64P, pci_eb64plus_pickintr) 135 136 #if 0 /* THIS DOES NOT WORK! see pci_eb64plus_intr.S. */ 137 uint8_t eb64plus_intr_mask[3] = { 0xff, 0xff, 0xff }; 138 139 void 140 eb64plus_intr_enable(pci_chipset_tag_t pc __unused, int irq) 141 { 142 int byte = (irq / 8), bit = (irq % 8); 143 144 #if 1 145 printf("eb64plus_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 146 #endif 147 eb64plus_intr_mask[byte] &= ~(1 << bit); 148 149 bus_space_write_1(eb64plus_intrgate_iot, eb64plus_intrgate_ioh, byte, 150 eb64plus_intr_mask[byte]); 151 } 152 153 void 154 eb64plus_intr_disable(pci_chipset_tag_t pc __unused, int irq) 155 { 156 int byte = (irq / 8), bit = (irq % 8); 157 158 #if 1 159 printf("eb64plus_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 160 #endif 161 eb64plus_intr_mask[byte] |= (1 << bit); 162 163 bus_space_write_1(eb64plus_intrgate_iot, eb64plus_intrgate_ioh, byte, 164 eb64plus_intr_mask[byte]); 165 } 166 #endif 167
Indexes created Sat Sep 20 22:09:52 GMT 2025