pci_eb64plus.c revision 1.10.2.3
1 1.10.2.3 nathanw /* $NetBSD: pci_eb64plus.c,v 1.10.2.3 2002/10/18 02:34:23 nathanw Exp $ */ 2 1.10.2.2 nathanw 3 1.10.2.2 nathanw /*- 4 1.10.2.2 nathanw * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 1.10.2.2 nathanw * All rights reserved. 6 1.10.2.2 nathanw * 7 1.10.2.2 nathanw * This code is derived from software contributed to The NetBSD Foundation 8 1.10.2.2 nathanw * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 1.10.2.2 nathanw * NASA Ames Research Center. 10 1.10.2.2 nathanw * 11 1.10.2.2 nathanw * Redistribution and use in source and binary forms, with or without 12 1.10.2.2 nathanw * modification, are permitted provided that the following conditions 13 1.10.2.2 nathanw * are met: 14 1.10.2.2 nathanw * 1. Redistributions of source code must retain the above copyright 15 1.10.2.2 nathanw * notice, this list of conditions and the following disclaimer. 16 1.10.2.2 nathanw * 2. Redistributions in binary form must reproduce the above copyright 17 1.10.2.2 nathanw * notice, this list of conditions and the following disclaimer in the 18 1.10.2.2 nathanw * documentation and/or other materials provided with the distribution. 19 1.10.2.2 nathanw * 3. All advertising materials mentioning features or use of this software 20 1.10.2.2 nathanw * must display the following acknowledgement: 21 1.10.2.2 nathanw * This product includes software developed by the NetBSD 22 1.10.2.2 nathanw * Foundation, Inc. and its contributors. 23 1.10.2.2 nathanw * 4. Neither the name of The NetBSD Foundation nor the names of its 24 1.10.2.2 nathanw * contributors may be used to endorse or promote products derived 25 1.10.2.2 nathanw * from this software without specific prior written permission. 26 1.10.2.2 nathanw * 27 1.10.2.2 nathanw * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 1.10.2.2 nathanw * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 1.10.2.2 nathanw * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 1.10.2.2 nathanw * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 1.10.2.2 nathanw * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 1.10.2.2 nathanw * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 1.10.2.2 nathanw * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 1.10.2.2 nathanw * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 1.10.2.2 nathanw * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 1.10.2.2 nathanw * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 1.10.2.2 nathanw * POSSIBILITY OF SUCH DAMAGE. 38 1.10.2.2 nathanw */ 39 1.10.2.2 nathanw 40 1.10.2.2 nathanw /* 41 1.10.2.2 nathanw * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 1.10.2.2 nathanw * All rights reserved. 43 1.10.2.2 nathanw * 44 1.10.2.2 nathanw * Author: Chris G. Demetriou 45 1.10.2.2 nathanw * 46 1.10.2.2 nathanw * Permission to use, copy, modify and distribute this software and 47 1.10.2.2 nathanw * its documentation is hereby granted, provided that both the copyright 48 1.10.2.2 nathanw * notice and this permission notice appear in all copies of the 49 1.10.2.2 nathanw * software, derivative works or modified versions, and any portions 50 1.10.2.2 nathanw * thereof, and that both notices appear in supporting documentation. 51 1.10.2.2 nathanw * 52 1.10.2.2 nathanw * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 1.10.2.2 nathanw * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 1.10.2.2 nathanw * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 1.10.2.2 nathanw * 56 1.10.2.2 nathanw * Carnegie Mellon requests users of this software to return to 57 1.10.2.2 nathanw * 58 1.10.2.2 nathanw * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 1.10.2.2 nathanw * School of Computer Science 60 1.10.2.2 nathanw * Carnegie Mellon University 61 1.10.2.2 nathanw * Pittsburgh PA 15213-3890 62 1.10.2.2 nathanw * 63 1.10.2.2 nathanw * any improvements or extensions that they make and grant Carnegie the 64 1.10.2.2 nathanw * rights to redistribute these changes. 65 1.10.2.2 nathanw */ 66 1.10.2.2 nathanw 67 1.10.2.2 nathanw #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 1.10.2.2 nathanw 69 1.10.2.3 nathanw __KERNEL_RCSID(0, "$NetBSD: pci_eb64plus.c,v 1.10.2.3 2002/10/18 02:34:23 nathanw Exp $"); 70 1.10.2.2 nathanw 71 1.10.2.2 nathanw #include <sys/types.h> 72 1.10.2.2 nathanw #include <sys/param.h> 73 1.10.2.2 nathanw #include <sys/time.h> 74 1.10.2.2 nathanw #include <sys/systm.h> 75 1.10.2.2 nathanw #include <sys/errno.h> 76 1.10.2.2 nathanw #include <sys/malloc.h> 77 1.10.2.2 nathanw #include <sys/device.h> 78 1.10.2.2 nathanw #include <sys/syslog.h> 79 1.10.2.2 nathanw 80 1.10.2.2 nathanw #include <uvm/uvm_extern.h> 81 1.10.2.2 nathanw 82 1.10.2.2 nathanw #include <machine/autoconf.h> 83 1.10.2.2 nathanw 84 1.10.2.2 nathanw #include <dev/pci/pcireg.h> 85 1.10.2.2 nathanw #include <dev/pci/pcivar.h> 86 1.10.2.2 nathanw 87 1.10.2.2 nathanw #include <alpha/pci/apecsreg.h> 88 1.10.2.2 nathanw #include <alpha/pci/apecsvar.h> 89 1.10.2.2 nathanw 90 1.10.2.2 nathanw #include <alpha/pci/pci_eb64plus.h> 91 1.10.2.2 nathanw 92 1.10.2.2 nathanw #include "sio.h" 93 1.10.2.2 nathanw #if NSIO 94 1.10.2.2 nathanw #include <alpha/pci/siovar.h> 95 1.10.2.2 nathanw #endif 96 1.10.2.2 nathanw 97 1.10.2.2 nathanw int dec_eb64plus_intr_map __P((struct pci_attach_args *, 98 1.10.2.2 nathanw pci_intr_handle_t *)); 99 1.10.2.2 nathanw const char *dec_eb64plus_intr_string __P((void *, pci_intr_handle_t)); 100 1.10.2.2 nathanw const struct evcnt *dec_eb64plus_intr_evcnt __P((void *, pci_intr_handle_t)); 101 1.10.2.2 nathanw void *dec_eb64plus_intr_establish __P((void *, pci_intr_handle_t, 102 1.10.2.2 nathanw int, int (*func)(void *), void *)); 103 1.10.2.2 nathanw void dec_eb64plus_intr_disestablish __P((void *, void *)); 104 1.10.2.2 nathanw 105 1.10.2.2 nathanw #define EB64PLUS_MAX_IRQ 32 106 1.10.2.2 nathanw #define PCI_STRAY_MAX 5 107 1.10.2.2 nathanw 108 1.10.2.2 nathanw struct alpha_shared_intr *eb64plus_pci_intr; 109 1.10.2.2 nathanw 110 1.10.2.2 nathanw bus_space_tag_t eb64plus_intrgate_iot; 111 1.10.2.2 nathanw bus_space_handle_t eb64plus_intrgate_ioh; 112 1.10.2.2 nathanw 113 1.10.2.2 nathanw void eb64plus_iointr __P((void *arg, unsigned long vec)); 114 1.10.2.2 nathanw extern void eb64plus_intr_enable __P((int irq)); /* pci_eb64plus_intr.S */ 115 1.10.2.2 nathanw extern void eb64plus_intr_disable __P((int irq)); /* pci_eb64plus_intr.S */ 116 1.10.2.2 nathanw 117 1.10.2.2 nathanw void 118 1.10.2.2 nathanw pci_eb64plus_pickintr(acp) 119 1.10.2.2 nathanw struct apecs_config *acp; 120 1.10.2.2 nathanw { 121 1.10.2.2 nathanw bus_space_tag_t iot = &acp->ac_iot; 122 1.10.2.2 nathanw pci_chipset_tag_t pc = &acp->ac_pc; 123 1.10.2.2 nathanw char *cp; 124 1.10.2.2 nathanw int i; 125 1.10.2.2 nathanw 126 1.10.2.2 nathanw pc->pc_intr_v = acp; 127 1.10.2.2 nathanw pc->pc_intr_map = dec_eb64plus_intr_map; 128 1.10.2.2 nathanw pc->pc_intr_string = dec_eb64plus_intr_string; 129 1.10.2.2 nathanw pc->pc_intr_evcnt = dec_eb64plus_intr_evcnt; 130 1.10.2.2 nathanw pc->pc_intr_establish = dec_eb64plus_intr_establish; 131 1.10.2.2 nathanw pc->pc_intr_disestablish = dec_eb64plus_intr_disestablish; 132 1.10.2.2 nathanw 133 1.10.2.2 nathanw /* Not supported on the EB64+. */ 134 1.10.2.2 nathanw pc->pc_pciide_compat_intr_establish = NULL; 135 1.10.2.2 nathanw 136 1.10.2.2 nathanw eb64plus_intrgate_iot = iot; 137 1.10.2.2 nathanw if (bus_space_map(eb64plus_intrgate_iot, 0x804, 3, 0, 138 1.10.2.2 nathanw &eb64plus_intrgate_ioh) != 0) 139 1.10.2.2 nathanw panic("pci_eb64plus_pickintr: couldn't map interrupt PLD"); 140 1.10.2.2 nathanw for (i = 0; i < EB64PLUS_MAX_IRQ; i++) 141 1.10.2.2 nathanw eb64plus_intr_disable(i); 142 1.10.2.2 nathanw 143 1.10.2.2 nathanw eb64plus_pci_intr = alpha_shared_intr_alloc(EB64PLUS_MAX_IRQ, 8); 144 1.10.2.2 nathanw for (i = 0; i < EB64PLUS_MAX_IRQ; i++) { 145 1.10.2.2 nathanw alpha_shared_intr_set_maxstrays(eb64plus_pci_intr, i, 146 1.10.2.2 nathanw PCI_STRAY_MAX); 147 1.10.2.2 nathanw 148 1.10.2.2 nathanw cp = alpha_shared_intr_string(eb64plus_pci_intr, i); 149 1.10.2.2 nathanw sprintf(cp, "irq %d", i); 150 1.10.2.2 nathanw evcnt_attach_dynamic(alpha_shared_intr_evcnt( 151 1.10.2.2 nathanw eb64plus_pci_intr, i), EVCNT_TYPE_INTR, NULL, 152 1.10.2.2 nathanw "eb64+", cp); 153 1.10.2.2 nathanw } 154 1.10.2.2 nathanw 155 1.10.2.2 nathanw #if NSIO 156 1.10.2.2 nathanw sio_intr_setup(pc, iot); 157 1.10.2.2 nathanw #endif 158 1.10.2.2 nathanw } 159 1.10.2.2 nathanw 160 1.10.2.2 nathanw int 161 1.10.2.2 nathanw dec_eb64plus_intr_map(pa, ihp) 162 1.10.2.2 nathanw struct pci_attach_args *pa; 163 1.10.2.2 nathanw pci_intr_handle_t *ihp; 164 1.10.2.2 nathanw { 165 1.10.2.2 nathanw pcitag_t bustag = pa->pa_intrtag; 166 1.10.2.2 nathanw int buspin = pa->pa_intrpin, line = pa->pa_intrline; 167 1.10.2.2 nathanw pci_chipset_tag_t pc = pa->pa_pc; 168 1.10.2.2 nathanw int bus, device, function; 169 1.10.2.2 nathanw 170 1.10.2.2 nathanw if (buspin == 0) { 171 1.10.2.2 nathanw /* No IRQ used. */ 172 1.10.2.2 nathanw return 1; 173 1.10.2.2 nathanw } 174 1.10.2.2 nathanw if (buspin > 4) { 175 1.10.2.2 nathanw printf("dec_eb64plus_intr_map: bad interrupt pin %d\n", buspin); 176 1.10.2.2 nathanw return 1; 177 1.10.2.2 nathanw } 178 1.10.2.2 nathanw 179 1.10.2.2 nathanw pci_decompose_tag(pc, bustag, &bus, &device, &function); 180 1.10.2.2 nathanw 181 1.10.2.2 nathanw /* 182 1.10.2.2 nathanw * The console places the interrupt mapping in the "line" value. 183 1.10.2.2 nathanw * A value of (char)-1 indicates there is no mapping. 184 1.10.2.2 nathanw */ 185 1.10.2.2 nathanw if (line == 0xff) { 186 1.10.2.2 nathanw printf("dec_eb64plus_intr_map: no mapping for %d/%d/%d\n", 187 1.10.2.2 nathanw bus, device, function); 188 1.10.2.2 nathanw return (1); 189 1.10.2.2 nathanw } 190 1.10.2.2 nathanw 191 1.10.2.2 nathanw if (line >= EB64PLUS_MAX_IRQ) 192 1.10.2.3 nathanw panic("dec_eb64plus_intr_map: eb64+ irq too large (%d)", 193 1.10.2.2 nathanw line); 194 1.10.2.2 nathanw 195 1.10.2.2 nathanw *ihp = line; 196 1.10.2.2 nathanw return (0); 197 1.10.2.2 nathanw } 198 1.10.2.2 nathanw 199 1.10.2.2 nathanw const char * 200 1.10.2.2 nathanw dec_eb64plus_intr_string(acv, ih) 201 1.10.2.2 nathanw void *acv; 202 1.10.2.2 nathanw pci_intr_handle_t ih; 203 1.10.2.2 nathanw { 204 1.10.2.2 nathanw static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 205 1.10.2.2 nathanw 206 1.10.2.2 nathanw if (ih > EB64PLUS_MAX_IRQ) 207 1.10.2.3 nathanw panic("dec_eb64plus_intr_string: bogus eb64+ IRQ 0x%lx", ih); 208 1.10.2.2 nathanw sprintf(irqstr, "eb64+ irq %ld", ih); 209 1.10.2.2 nathanw return (irqstr); 210 1.10.2.2 nathanw } 211 1.10.2.2 nathanw 212 1.10.2.2 nathanw const struct evcnt * 213 1.10.2.2 nathanw dec_eb64plus_intr_evcnt(acv, ih) 214 1.10.2.2 nathanw void *acv; 215 1.10.2.2 nathanw pci_intr_handle_t ih; 216 1.10.2.2 nathanw { 217 1.10.2.2 nathanw 218 1.10.2.2 nathanw if (ih > EB64PLUS_MAX_IRQ) 219 1.10.2.3 nathanw panic("dec_eb64plus_intr_string: bogus eb64+ IRQ 0x%lx", ih); 220 1.10.2.2 nathanw return (alpha_shared_intr_evcnt(eb64plus_pci_intr, ih)); 221 1.10.2.2 nathanw } 222 1.10.2.2 nathanw 223 1.10.2.2 nathanw void * 224 1.10.2.2 nathanw dec_eb64plus_intr_establish(acv, ih, level, func, arg) 225 1.10.2.2 nathanw void *acv, *arg; 226 1.10.2.2 nathanw pci_intr_handle_t ih; 227 1.10.2.2 nathanw int level; 228 1.10.2.2 nathanw int (*func) __P((void *)); 229 1.10.2.2 nathanw { 230 1.10.2.2 nathanw void *cookie; 231 1.10.2.2 nathanw 232 1.10.2.2 nathanw if (ih > EB64PLUS_MAX_IRQ) 233 1.10.2.3 nathanw panic("dec_eb64plus_intr_establish: bogus eb64+ IRQ 0x%lx", 234 1.10.2.2 nathanw ih); 235 1.10.2.2 nathanw 236 1.10.2.2 nathanw cookie = alpha_shared_intr_establish(eb64plus_pci_intr, ih, IST_LEVEL, 237 1.10.2.2 nathanw level, func, arg, "eb64+ irq"); 238 1.10.2.2 nathanw 239 1.10.2.2 nathanw if (cookie != NULL && 240 1.10.2.2 nathanw alpha_shared_intr_firstactive(eb64plus_pci_intr, ih)) { 241 1.10.2.2 nathanw scb_set(0x900 + SCB_IDXTOVEC(ih), eb64plus_iointr, NULL); 242 1.10.2.2 nathanw eb64plus_intr_enable(ih); 243 1.10.2.2 nathanw } 244 1.10.2.2 nathanw return (cookie); 245 1.10.2.2 nathanw } 246 1.10.2.2 nathanw 247 1.10.2.2 nathanw void 248 1.10.2.2 nathanw dec_eb64plus_intr_disestablish(acv, cookie) 249 1.10.2.2 nathanw void *acv, *cookie; 250 1.10.2.2 nathanw { 251 1.10.2.2 nathanw struct alpha_shared_intrhand *ih = cookie; 252 1.10.2.2 nathanw unsigned int irq = ih->ih_num; 253 1.10.2.2 nathanw int s; 254 1.10.2.2 nathanw 255 1.10.2.2 nathanw s = splhigh(); 256 1.10.2.2 nathanw 257 1.10.2.2 nathanw alpha_shared_intr_disestablish(eb64plus_pci_intr, cookie, 258 1.10.2.2 nathanw "eb64+ irq"); 259 1.10.2.2 nathanw if (alpha_shared_intr_isactive(eb64plus_pci_intr, irq) == 0) { 260 1.10.2.2 nathanw eb64plus_intr_disable(irq); 261 1.10.2.2 nathanw alpha_shared_intr_set_dfltsharetype(eb64plus_pci_intr, irq, 262 1.10.2.2 nathanw IST_NONE); 263 1.10.2.2 nathanw scb_free(0x900 + SCB_IDXTOVEC(irq)); 264 1.10.2.2 nathanw } 265 1.10.2.2 nathanw 266 1.10.2.2 nathanw splx(s); 267 1.10.2.2 nathanw } 268 1.10.2.2 nathanw 269 1.10.2.2 nathanw void 270 1.10.2.2 nathanw eb64plus_iointr(arg, vec) 271 1.10.2.2 nathanw void *arg; 272 1.10.2.2 nathanw unsigned long vec; 273 1.10.2.2 nathanw { 274 1.10.2.2 nathanw int irq; 275 1.10.2.2 nathanw 276 1.10.2.2 nathanw irq = SCB_VECTOIDX(vec - 0x900); 277 1.10.2.2 nathanw 278 1.10.2.2 nathanw if (!alpha_shared_intr_dispatch(eb64plus_pci_intr, irq)) { 279 1.10.2.2 nathanw alpha_shared_intr_stray(eb64plus_pci_intr, irq, 280 1.10.2.2 nathanw "eb64+ irq"); 281 1.10.2.2 nathanw if (ALPHA_SHARED_INTR_DISABLE(eb64plus_pci_intr, irq)) 282 1.10.2.2 nathanw eb64plus_intr_disable(irq); 283 1.10.2.2 nathanw } 284 1.10.2.2 nathanw } 285 1.10.2.2 nathanw 286 1.10.2.2 nathanw #if 0 /* THIS DOES NOT WORK! see pci_eb64plus_intr.S. */ 287 1.10.2.2 nathanw u_int8_t eb64plus_intr_mask[3] = { 0xff, 0xff, 0xff }; 288 1.10.2.2 nathanw 289 1.10.2.2 nathanw void 290 1.10.2.2 nathanw eb64plus_intr_enable(irq) 291 1.10.2.2 nathanw int irq; 292 1.10.2.2 nathanw { 293 1.10.2.2 nathanw int byte = (irq / 8), bit = (irq % 8); 294 1.10.2.2 nathanw 295 1.10.2.2 nathanw #if 1 296 1.10.2.2 nathanw printf("eb64plus_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 297 1.10.2.2 nathanw #endif 298 1.10.2.2 nathanw eb64plus_intr_mask[byte] &= ~(1 << bit); 299 1.10.2.2 nathanw 300 1.10.2.2 nathanw bus_space_write_1(eb64plus_intrgate_iot, eb64plus_intrgate_ioh, byte, 301 1.10.2.2 nathanw eb64plus_intr_mask[byte]); 302 1.10.2.2 nathanw } 303 1.10.2.2 nathanw 304 1.10.2.2 nathanw void 305 1.10.2.2 nathanw eb64plus_intr_disable(irq) 306 1.10.2.2 nathanw int irq; 307 1.10.2.2 nathanw { 308 1.10.2.2 nathanw int byte = (irq / 8), bit = (irq % 8); 309 1.10.2.2 nathanw 310 1.10.2.2 nathanw #if 1 311 1.10.2.2 nathanw printf("eb64plus_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 312 1.10.2.2 nathanw #endif 313 1.10.2.2 nathanw eb64plus_intr_mask[byte] |= (1 << bit); 314 1.10.2.2 nathanw 315 1.10.2.2 nathanw bus_space_write_1(eb64plus_intrgate_iot, eb64plus_intrgate_ioh, byte, 316 1.10.2.2 nathanw eb64plus_intr_mask[byte]); 317 1.10.2.2 nathanw } 318 1.10.2.2 nathanw #endif 319
Indexes created Wed Oct 29 09:09:48 GMT 2025