pci_eb64plus.c revision 1.17
1 /* $NetBSD: pci_eb64plus.c,v 1.17 2009/03/14 14:45:53 dsl Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 35 * All rights reserved. 36 * 37 * Author: Chris G. Demetriou 38 * 39 * Permission to use, copy, modify and distribute this software and 40 * its documentation is hereby granted, provided that both the copyright 41 * notice and this permission notice appear in all copies of the 42 * software, derivative works or modified versions, and any portions 43 * thereof, and that both notices appear in supporting documentation. 44 * 45 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 46 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 47 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 48 * 49 * Carnegie Mellon requests users of this software to return to 50 * 51 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 52 * School of Computer Science 53 * Carnegie Mellon University 54 * Pittsburgh PA 15213-3890 55 * 56 * any improvements or extensions that they make and grant Carnegie the 57 * rights to redistribute these changes. 58 */ 59 60 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 61 62 __KERNEL_RCSID(0, "$NetBSD: pci_eb64plus.c,v 1.17 2009/03/14 14:45:53 dsl Exp $"); 63 64 #include <sys/types.h> 65 #include <sys/param.h> 66 #include <sys/time.h> 67 #include <sys/systm.h> 68 #include <sys/errno.h> 69 #include <sys/malloc.h> 70 #include <sys/device.h> 71 #include <sys/syslog.h> 72 73 #include <uvm/uvm_extern.h> 74 75 #include <machine/autoconf.h> 76 77 #include <dev/pci/pcireg.h> 78 #include <dev/pci/pcivar.h> 79 80 #include <alpha/pci/apecsreg.h> 81 #include <alpha/pci/apecsvar.h> 82 83 #include <alpha/pci/pci_eb64plus.h> 84 85 #include "sio.h" 86 #if NSIO 87 #include <alpha/pci/siovar.h> 88 #endif 89 90 int dec_eb64plus_intr_map(struct pci_attach_args *, 91 pci_intr_handle_t *); 92 const char *dec_eb64plus_intr_string(void *, pci_intr_handle_t); 93 const struct evcnt *dec_eb64plus_intr_evcnt(void *, pci_intr_handle_t); 94 void *dec_eb64plus_intr_establish(void *, pci_intr_handle_t, 95 int, int (*func)(void *), void *); 96 void dec_eb64plus_intr_disestablish(void *, void *); 97 98 #define EB64PLUS_MAX_IRQ 32 99 #define PCI_STRAY_MAX 5 100 101 struct alpha_shared_intr *eb64plus_pci_intr; 102 103 bus_space_tag_t eb64plus_intrgate_iot; 104 bus_space_handle_t eb64plus_intrgate_ioh; 105 106 void eb64plus_iointr(void *arg, unsigned long vec); 107 extern void eb64plus_intr_enable(int irq); /* pci_eb64plus_intr.S */ 108 extern void eb64plus_intr_disable(int irq); /* pci_eb64plus_intr.S */ 109 110 void 111 pci_eb64plus_pickintr(acp) 112 struct apecs_config *acp; 113 { 114 bus_space_tag_t iot = &acp->ac_iot; 115 pci_chipset_tag_t pc = &acp->ac_pc; 116 char *cp; 117 int i; 118 119 pc->pc_intr_v = acp; 120 pc->pc_intr_map = dec_eb64plus_intr_map; 121 pc->pc_intr_string = dec_eb64plus_intr_string; 122 pc->pc_intr_evcnt = dec_eb64plus_intr_evcnt; 123 pc->pc_intr_establish = dec_eb64plus_intr_establish; 124 pc->pc_intr_disestablish = dec_eb64plus_intr_disestablish; 125 126 /* Not supported on the EB64+. */ 127 pc->pc_pciide_compat_intr_establish = NULL; 128 129 eb64plus_intrgate_iot = iot; 130 if (bus_space_map(eb64plus_intrgate_iot, 0x804, 3, 0, 131 &eb64plus_intrgate_ioh) != 0) 132 panic("pci_eb64plus_pickintr: couldn't map interrupt PLD"); 133 for (i = 0; i < EB64PLUS_MAX_IRQ; i++) 134 eb64plus_intr_disable(i); 135 136 eb64plus_pci_intr = alpha_shared_intr_alloc(EB64PLUS_MAX_IRQ, 8); 137 for (i = 0; i < EB64PLUS_MAX_IRQ; i++) { 138 alpha_shared_intr_set_maxstrays(eb64plus_pci_intr, i, 139 PCI_STRAY_MAX); 140 141 cp = alpha_shared_intr_string(eb64plus_pci_intr, i); 142 sprintf(cp, "irq %d", i); 143 evcnt_attach_dynamic(alpha_shared_intr_evcnt( 144 eb64plus_pci_intr, i), EVCNT_TYPE_INTR, NULL, 145 "eb64+", cp); 146 } 147 148 #if NSIO 149 sio_intr_setup(pc, iot); 150 #endif 151 } 152 153 int 154 dec_eb64plus_intr_map(pa, ihp) 155 struct pci_attach_args *pa; 156 pci_intr_handle_t *ihp; 157 { 158 pcitag_t bustag = pa->pa_intrtag; 159 int buspin = pa->pa_intrpin, line = pa->pa_intrline; 160 pci_chipset_tag_t pc = pa->pa_pc; 161 int bus, device, function; 162 163 if (buspin == 0) { 164 /* No IRQ used. */ 165 return 1; 166 } 167 if (buspin > 4) { 168 printf("dec_eb64plus_intr_map: bad interrupt pin %d\n", buspin); 169 return 1; 170 } 171 172 pci_decompose_tag(pc, bustag, &bus, &device, &function); 173 174 /* 175 * The console places the interrupt mapping in the "line" value. 176 * A value of (char)-1 indicates there is no mapping. 177 */ 178 if (line == 0xff) { 179 printf("dec_eb64plus_intr_map: no mapping for %d/%d/%d\n", 180 bus, device, function); 181 return (1); 182 } 183 184 if (line >= EB64PLUS_MAX_IRQ) 185 panic("dec_eb64plus_intr_map: eb64+ irq too large (%d)", 186 line); 187 188 *ihp = line; 189 return (0); 190 } 191 192 const char * 193 dec_eb64plus_intr_string(acv, ih) 194 void *acv; 195 pci_intr_handle_t ih; 196 { 197 static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 198 199 if (ih > EB64PLUS_MAX_IRQ) 200 panic("dec_eb64plus_intr_string: bogus eb64+ IRQ 0x%lx", ih); 201 sprintf(irqstr, "eb64+ irq %ld", ih); 202 return (irqstr); 203 } 204 205 const struct evcnt * 206 dec_eb64plus_intr_evcnt(acv, ih) 207 void *acv; 208 pci_intr_handle_t ih; 209 { 210 211 if (ih > EB64PLUS_MAX_IRQ) 212 panic("dec_eb64plus_intr_string: bogus eb64+ IRQ 0x%lx", ih); 213 return (alpha_shared_intr_evcnt(eb64plus_pci_intr, ih)); 214 } 215 216 void * 217 dec_eb64plus_intr_establish(acv, ih, level, func, arg) 218 void *acv, *arg; 219 pci_intr_handle_t ih; 220 int level; 221 int (*func)(void *); 222 { 223 void *cookie; 224 225 if (ih > EB64PLUS_MAX_IRQ) 226 panic("dec_eb64plus_intr_establish: bogus eb64+ IRQ 0x%lx", 227 ih); 228 229 cookie = alpha_shared_intr_establish(eb64plus_pci_intr, ih, IST_LEVEL, 230 level, func, arg, "eb64+ irq"); 231 232 if (cookie != NULL && 233 alpha_shared_intr_firstactive(eb64plus_pci_intr, ih)) { 234 scb_set(0x900 + SCB_IDXTOVEC(ih), eb64plus_iointr, NULL, 235 level); 236 eb64plus_intr_enable(ih); 237 } 238 return (cookie); 239 } 240 241 void 242 dec_eb64plus_intr_disestablish(acv, cookie) 243 void *acv, *cookie; 244 { 245 struct alpha_shared_intrhand *ih = cookie; 246 unsigned int irq = ih->ih_num; 247 int s; 248 249 s = splhigh(); 250 251 alpha_shared_intr_disestablish(eb64plus_pci_intr, cookie, 252 "eb64+ irq"); 253 if (alpha_shared_intr_isactive(eb64plus_pci_intr, irq) == 0) { 254 eb64plus_intr_disable(irq); 255 alpha_shared_intr_set_dfltsharetype(eb64plus_pci_intr, irq, 256 IST_NONE); 257 scb_free(0x900 + SCB_IDXTOVEC(irq)); 258 } 259 260 splx(s); 261 } 262 263 void 264 eb64plus_iointr(arg, vec) 265 void *arg; 266 unsigned long vec; 267 { 268 int irq; 269 270 irq = SCB_VECTOIDX(vec - 0x900); 271 272 if (!alpha_shared_intr_dispatch(eb64plus_pci_intr, irq)) { 273 alpha_shared_intr_stray(eb64plus_pci_intr, irq, 274 "eb64+ irq"); 275 if (ALPHA_SHARED_INTR_DISABLE(eb64plus_pci_intr, irq)) 276 eb64plus_intr_disable(irq); 277 } else 278 alpha_shared_intr_reset_strays(eb64plus_pci_intr, irq); 279 } 280 281 #if 0 /* THIS DOES NOT WORK! see pci_eb64plus_intr.S. */ 282 u_int8_t eb64plus_intr_mask[3] = { 0xff, 0xff, 0xff }; 283 284 void 285 eb64plus_intr_enable(irq) 286 int irq; 287 { 288 int byte = (irq / 8), bit = (irq % 8); 289 290 #if 1 291 printf("eb64plus_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 292 #endif 293 eb64plus_intr_mask[byte] &= ~(1 << bit); 294 295 bus_space_write_1(eb64plus_intrgate_iot, eb64plus_intrgate_ioh, byte, 296 eb64plus_intr_mask[byte]); 297 } 298 299 void 300 eb64plus_intr_disable(irq) 301 int irq; 302 { 303 int byte = (irq / 8), bit = (irq % 8); 304 305 #if 1 306 printf("eb64plus_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 307 #endif 308 eb64plus_intr_mask[byte] |= (1 << bit); 309 310 bus_space_write_1(eb64plus_intrgate_iot, eb64plus_intrgate_ioh, byte, 311 eb64plus_intr_mask[byte]); 312 } 313 #endif 314
Indexes created Mon Sep 29 18:09:42 GMT 2025