pci_eb64plus.c revision 1.5
1 /* $NetBSD: pci_eb64plus.c,v 1.5 1999/02/12 06:25:13 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 42 * All rights reserved. 43 * 44 * Author: Chris G. Demetriou 45 * 46 * Permission to use, copy, modify and distribute this software and 47 * its documentation is hereby granted, provided that both the copyright 48 * notice and this permission notice appear in all copies of the 49 * software, derivative works or modified versions, and any portions 50 * thereof, and that both notices appear in supporting documentation. 51 * 52 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 53 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 54 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 55 * 56 * Carnegie Mellon requests users of this software to return to 57 * 58 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 59 * School of Computer Science 60 * Carnegie Mellon University 61 * Pittsburgh PA 15213-3890 62 * 63 * any improvements or extensions that they make and grant Carnegie the 64 * rights to redistribute these changes. 65 */ 66 67 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 68 69 __KERNEL_RCSID(0, "$NetBSD: pci_eb64plus.c,v 1.5 1999/02/12 06:25:13 thorpej Exp $"); 70 71 #include <sys/types.h> 72 #include <sys/param.h> 73 #include <sys/time.h> 74 #include <sys/systm.h> 75 #include <sys/errno.h> 76 #include <sys/malloc.h> 77 #include <sys/device.h> 78 #include <sys/syslog.h> 79 80 #include <vm/vm.h> 81 82 #include <machine/autoconf.h> 83 84 #include <dev/pci/pcireg.h> 85 #include <dev/pci/pcivar.h> 86 87 #include <alpha/pci/apecsreg.h> 88 #include <alpha/pci/apecsvar.h> 89 90 #include <alpha/pci/pci_eb64plus.h> 91 92 #ifndef EVCNT_COUNTERS 93 #include <machine/intrcnt.h> 94 #endif 95 96 #include "sio.h" 97 #if NSIO 98 #include <alpha/pci/siovar.h> 99 #endif 100 101 int dec_eb64plus_intr_map __P((void *, pcitag_t, int, int, 102 pci_intr_handle_t *)); 103 const char *dec_eb64plus_intr_string __P((void *, pci_intr_handle_t)); 104 void *dec_eb64plus_intr_establish __P((void *, pci_intr_handle_t, 105 int, int (*func)(void *), void *)); 106 void dec_eb64plus_intr_disestablish __P((void *, void *)); 107 108 #define EB64PLUS_MAX_IRQ 32 109 #define PCI_STRAY_MAX 5 110 111 struct alpha_shared_intr *eb64plus_pci_intr; 112 #ifdef EVCNT_COUNTERS 113 struct evcnt eb64plus_intr_evcnt; 114 #endif 115 116 bus_space_tag_t eb64plus_intrgate_iot; 117 bus_space_handle_t eb64plus_intrgate_ioh; 118 119 void eb64plus_iointr __P((void *framep, unsigned long vec)); 120 extern void eb64plus_intr_enable __P((int irq)); /* pci_eb64plus_intr.S */ 121 extern void eb64plus_intr_disable __P((int irq)); /* pci_eb64plus_intr.S */ 122 123 void 124 pci_eb64plus_pickintr(acp) 125 struct apecs_config *acp; 126 { 127 bus_space_tag_t iot = &acp->ac_iot; 128 pci_chipset_tag_t pc = &acp->ac_pc; 129 int i; 130 131 pc->pc_intr_v = acp; 132 pc->pc_intr_map = dec_eb64plus_intr_map; 133 pc->pc_intr_string = dec_eb64plus_intr_string; 134 pc->pc_intr_establish = dec_eb64plus_intr_establish; 135 pc->pc_intr_disestablish = dec_eb64plus_intr_disestablish; 136 137 /* Not supported on the EB64+. */ 138 pc->pc_pciide_compat_intr_establish = NULL; 139 140 eb64plus_intrgate_iot = iot; 141 if (bus_space_map(eb64plus_intrgate_iot, 0x804, 3, 0, 142 &eb64plus_intrgate_ioh) != 0) 143 panic("pci_eb64plus_pickintr: couldn't map interrupt PLD"); 144 for (i = 0; i < EB64PLUS_MAX_IRQ; i++) 145 eb64plus_intr_disable(i); 146 147 eb64plus_pci_intr = alpha_shared_intr_alloc(EB64PLUS_MAX_IRQ); 148 for (i = 0; i < EB64PLUS_MAX_IRQ; i++) 149 alpha_shared_intr_set_maxstrays(eb64plus_pci_intr, i, 150 PCI_STRAY_MAX); 151 152 #if NSIO 153 sio_intr_setup(pc, iot); 154 #endif 155 156 set_iointr(eb64plus_iointr); 157 } 158 159 int 160 dec_eb64plus_intr_map(acv, bustag, buspin, line, ihp) 161 void *acv; 162 pcitag_t bustag; 163 int buspin, line; 164 pci_intr_handle_t *ihp; 165 { 166 struct apecs_config *acp = acv; 167 pci_chipset_tag_t pc = &acp->ac_pc; 168 int bus, device, function; 169 170 if (buspin == 0) { 171 /* No IRQ used. */ 172 return 1; 173 } 174 if (buspin > 4) { 175 printf("dec_eb64plus_intr_map: bad interrupt pin %d\n", buspin); 176 return 1; 177 } 178 179 alpha_pci_decompose_tag(pc, bustag, &bus, &device, &function); 180 181 /* 182 * The console places the interrupt mapping in the "line" value. 183 * A value of (char)-1 indicates there is no mapping. 184 */ 185 if (line == 0xff) { 186 printf("dec_eb64plus_intr_map: no mapping for %d/%d/%d\n", 187 bus, device, function); 188 return (1); 189 } 190 191 if (line >= EB64PLUS_MAX_IRQ) 192 panic("dec_eb64plus_intr_map: eb64+ irq too large (%d)\n", 193 line); 194 195 *ihp = line; 196 return (0); 197 } 198 199 const char * 200 dec_eb64plus_intr_string(acv, ih) 201 void *acv; 202 pci_intr_handle_t ih; 203 { 204 static char irqstr[15]; /* 11 + 2 + NULL + sanity */ 205 206 if (ih > EB64PLUS_MAX_IRQ) 207 panic("dec_eb64plus_intr_string: bogus eb64+ IRQ 0x%lx\n", ih); 208 sprintf(irqstr, "eb64+ irq %ld", ih); 209 return (irqstr); 210 } 211 212 void * 213 dec_eb64plus_intr_establish(acv, ih, level, func, arg) 214 void *acv, *arg; 215 pci_intr_handle_t ih; 216 int level; 217 int (*func) __P((void *)); 218 { 219 void *cookie; 220 221 if (ih > EB64PLUS_MAX_IRQ) 222 panic("dec_eb64plus_intr_establish: bogus eb64+ IRQ 0x%lx\n", 223 ih); 224 225 cookie = alpha_shared_intr_establish(eb64plus_pci_intr, ih, IST_LEVEL, 226 level, func, arg, "eb64+ irq"); 227 228 if (cookie != NULL && alpha_shared_intr_isactive(eb64plus_pci_intr, ih)) 229 eb64plus_intr_enable(ih); 230 return (cookie); 231 } 232 233 void 234 dec_eb64plus_intr_disestablish(acv, cookie) 235 void *acv, *cookie; 236 { 237 struct alpha_shared_intrhand *ih = cookie; 238 unsigned int irq = ih->ih_num; 239 int s; 240 241 s = splhigh(); 242 243 alpha_shared_intr_disestablish(eb64plus_pci_intr, cookie, 244 "eb64+ irq"); 245 if (alpha_shared_intr_isactive(eb64plus_pci_intr, irq) == 0) { 246 eb64plus_intr_disable(irq); 247 alpha_shared_intr_set_dfltsharetype(eb64plus_pci_intr, irq, 248 IST_NONE); 249 } 250 251 splx(s); 252 } 253 254 void 255 eb64plus_iointr(framep, vec) 256 void *framep; 257 unsigned long vec; 258 { 259 int irq; 260 261 if (vec >= 0x900) { 262 if (vec >= 0x900 + (EB64PLUS_MAX_IRQ << 4)) 263 panic("eb64plus_iointr: vec 0x%lx out of range\n", vec); 264 irq = (vec - 0x900) >> 4; 265 266 #ifdef EVCNT_COUNTERS 267 eb64plus_intr_evcnt.ev_count++; 268 #else 269 if (EB64PLUS_MAX_IRQ != INTRCNT_EB64PLUS_IRQ_LEN) 270 panic("eb64plus interrupt counter sizes inconsistent"); 271 intrcnt[INTRCNT_EB64PLUS_IRQ + irq]++; 272 #endif 273 274 if (!alpha_shared_intr_dispatch(eb64plus_pci_intr, irq)) { 275 alpha_shared_intr_stray(eb64plus_pci_intr, irq, 276 "eb64+ irq"); 277 if (ALPHA_SHARED_INTR_DISABLE(eb64plus_pci_intr, irq)) 278 eb64plus_intr_disable(irq); 279 } 280 return; 281 } 282 #if NSIO 283 if (vec >= 0x800) { 284 sio_iointr(framep, vec); 285 return; 286 } 287 #endif 288 panic("eb64plus_iointr: weird vec 0x%lx\n", vec); 289 } 290 291 #if 0 /* THIS DOES NOT WORK! see pci_eb64plus_intr.S. */ 292 u_int8_t eb64plus_intr_mask[3] = { 0xff, 0xff, 0xff }; 293 294 void 295 eb64plus_intr_enable(irq) 296 int irq; 297 { 298 int byte = (irq / 8), bit = (irq % 8); 299 300 #if 1 301 printf("eb64plus_intr_enable: enabling %d (%d:%d)\n", irq, byte, bit); 302 #endif 303 eb64plus_intr_mask[byte] &= ~(1 << bit); 304 305 bus_space_write_1(eb64plus_intrgate_iot, eb64plus_intrgate_ioh, byte, 306 eb64plus_intr_mask[byte]); 307 } 308 309 void 310 eb64plus_intr_disable(irq) 311 int irq; 312 { 313 int byte = (irq / 8), bit = (irq % 8); 314 315 #if 1 316 printf("eb64plus_intr_disable: disabling %d (%d:%d)\n", irq, byte, bit); 317 #endif 318 eb64plus_intr_mask[byte] |= (1 << bit); 319 320 bus_space_write_1(eb64plus_intrgate_iot, eb64plus_intrgate_ioh, byte, 321 eb64plus_intr_mask[byte]); 322 } 323 #endif 324
Indexes created Mon Sep 29 21:09:56 GMT 2025