1 /* $NetBSD: ttwoga_pci.c,v 1.10 2021/06/25 03:49:47 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> /* RCS ID & Copyright macro defns */ 33 34 __KERNEL_RCSID(0, "$NetBSD: ttwoga_pci.c,v 1.10 2021/06/25 03:49:47 thorpej Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/kernel.h> 39 #include <sys/device.h> 40 41 #include <dev/pci/pcireg.h> 42 #include <dev/pci/pcivar.h> 43 44 #include <alpha/pci/ttwogareg.h> 45 #include <alpha/pci/ttwogavar.h> 46 47 static int ttwoga_bus_maxdevs(void *, int); 48 static pcireg_t ttwoga_conf_read(void *, pcitag_t, int); 49 static void ttwoga_conf_write(void *, pcitag_t, int, pcireg_t); 50 51 static paddr_t ttwoga_make_type0addr(int, int); 52 53 /* 54 * The T2 has an annoying bug that can manifest itself while 55 * probing for devices. If a non-existent CBUS address is 56 * accessed with a read, "a few" subsequent write cycles 57 * will generate spurious memory errors. We work around this 58 * by tracking which CPU has the PCI configuration mutex and 59 * "expect" machine checks on that CPU for the duraction of 60 * the PCI configuration access routine. 61 */ 62 63 static kmutex_t ttwoga_conf_lock; 64 cpuid_t ttwoga_conf_cpu; /* XXX core logic bug */ 65 66 #define TTWOGA_CONF_LOCK() \ 67 do { \ 68 mutex_enter(&ttwoga_conf_lock); \ 69 ttwoga_conf_cpu = cpu_number(); \ 70 } while (0) 71 72 #define TTWOGA_CONF_UNLOCK() \ 73 do { \ 74 ttwoga_conf_cpu = (cpuid_t)-1; \ 75 mutex_exit(&ttwoga_conf_lock); \ 76 } while (0) 77 78 void 79 ttwoga_pci_init(pci_chipset_tag_t pc, void *v) 80 { 81 82 mutex_init(&ttwoga_conf_lock, MUTEX_DEFAULT, IPL_HIGH); 83 84 pc->pc_conf_v = v; 85 pc->pc_bus_maxdevs = ttwoga_bus_maxdevs; 86 pc->pc_conf_read = ttwoga_conf_read; 87 pc->pc_conf_write = ttwoga_conf_write; 88 } 89 90 static int 91 ttwoga_bus_maxdevs(void *cpv, int busno) 92 { 93 /* 94 * We have to drive the IDSEL directly on bus 0, so we are 95 * limited to 9 devices there. 96 */ 97 return busno == 0 ? 9 : 32; 98 } 99 100 static paddr_t 101 ttwoga_make_type0addr(int d, int f) 102 { 103 KASSERT(d < 9); 104 return PCI_CONF_TYPE0_IDSEL(d) | __SHIFTIN(f, PCI_CONF_TYPE1_FUNCTION); 105 } 106 107 static pcireg_t 108 ttwoga_conf_read(void *cpv, pcitag_t tag, int offset) 109 { 110 struct ttwoga_config *tcp = cpv; 111 pcireg_t *datap, data; 112 int b, d, f, ba; 113 paddr_t addr; 114 uint64_t old_hae3; 115 116 if ((unsigned int)offset >= PCI_CONF_SIZE) 117 return (pcireg_t) -1; 118 119 pci_decompose_tag(&tcp->tc_pc, tag, &b, &d, &f); 120 121 addr = b ? tag : ttwoga_make_type0addr(d, f); 122 123 TTWOGA_CONF_LOCK(); 124 125 alpha_mb(); 126 old_hae3 = T2GA(tcp, T2_HAE0_3) & ~HAE0_3_PCA; 127 T2GA(tcp, T2_HAE0_3) = 128 old_hae3 | ((b ? 1UL : 0UL) << HAE0_3_PCA_SHIFT); 129 alpha_mb(); 130 alpha_mb(); 131 132 datap = 133 (pcireg_t *)ALPHA_PHYS_TO_K0SEG(tcp->tc_sysmap->tsmap_conf_base | 134 addr << 5UL | /* address shift */ 135 (offset & ~0x03) << 5UL | /* address shift */ 136 0x3 << 3UL); /* 4-byte, size shift */ 137 data = (pcireg_t)-1; 138 if (!(ba = badaddr(datap, sizeof *datap))) 139 data = *datap; 140 141 alpha_mb(); 142 T2GA(tcp, T2_HAE0_3) = old_hae3; 143 alpha_mb(); 144 alpha_mb(); 145 146 alpha_pal_draina(); 147 alpha_mb(); 148 alpha_mb(); 149 150 TTWOGA_CONF_UNLOCK(); 151 152 #if 0 153 printf("ttwoga_conf_read: tag 0x%lx, reg 0x%x -> 0x%x @ %p%s\n", 154 tag, offset, data, datap, ba ? " (badaddr)" : ""); 155 #endif 156 157 return (data); 158 } 159 160 static void 161 ttwoga_conf_write(void *cpv, pcitag_t tag, int offset, pcireg_t data) 162 { 163 struct ttwoga_config *tcp = cpv; 164 pcireg_t *datap; 165 int b, d, f; 166 paddr_t addr; 167 uint64_t old_hae3; 168 169 if ((unsigned int)offset >= PCI_CONF_SIZE) 170 return; 171 172 pci_decompose_tag(&tcp->tc_pc, tag, &b, &d, &f); 173 174 addr = b ? tag : ttwoga_make_type0addr(d, f); 175 176 TTWOGA_CONF_LOCK(); 177 178 alpha_mb(); 179 old_hae3 = T2GA(tcp, T2_HAE0_3) & ~HAE0_3_PCA; 180 T2GA(tcp, T2_HAE0_3) = 181 old_hae3 | ((b ? 1UL : 0UL) << HAE0_3_PCA_SHIFT); 182 alpha_mb(); 183 alpha_mb(); 184 185 datap = 186 (pcireg_t *)ALPHA_PHYS_TO_K0SEG(tcp->tc_sysmap->tsmap_conf_base | 187 addr << 5UL | /* address shift */ 188 (offset & ~0x03) << 5UL | /* address shift */ 189 0x3 << 3UL); /* 4-byte, size shift */ 190 191 alpha_mb(); 192 *datap = data; 193 alpha_mb(); 194 alpha_mb(); 195 196 alpha_mb(); 197 T2GA(tcp, T2_HAE0_3) = old_hae3; 198 alpha_mb(); 199 alpha_mb(); 200 201 TTWOGA_CONF_UNLOCK(); 202 203 #if 0 204 printf("ttwoga_conf_write: tag 0x%lx, reg 0x%x -> 0x%x @ %p\n", 205 tag, offset, data, datap); 206 #endif 207 } 208
Indexes created Thu Sep 25 16:09:42 GMT 2025