pmap.h revision 1.36 
1/*	$NetBSD: pmap.h,v 1.36 2016/05/14 12:48:31 maxv Exp $	*/
2
3/*
4 * Copyright (c) 1997 Charles D. Cranor and Washington University.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28/*
29 * Copyright (c) 2001 Wasabi Systems, Inc.
30 * All rights reserved.
31 *
32 * Written by Frank van der Linden for Wasabi Systems, Inc.
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 *    notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 *    notice, this list of conditions and the following disclaimer in the
41 *    documentation and/or other materials provided with the distribution.
42 * 3. All advertising materials mentioning features or use of this software
43 *    must display the following acknowledgement:
44 *      This product includes software developed for the NetBSD Project by
45 *      Wasabi Systems, Inc.
46 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
47 *    or promote products derived from this software without specific prior
48 *    written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
53 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
60 * POSSIBILITY OF SUCH DAMAGE.
61 */
62
63#ifndef	_AMD64_PMAP_H_
64#define	_AMD64_PMAP_H_
65
66#ifdef __x86_64__
67
68#if defined(_KERNEL_OPT)
69#include "opt_xen.h"
70#endif
71
72#include <sys/atomic.h>
73
74#include <machine/pte.h>
75#include <machine/segments.h>
76#ifdef _KERNEL
77#include <machine/cpufunc.h>
78#endif
79
80#include <uvm/uvm_object.h>
81#ifdef XEN
82#include <xen/xenfunc.h>
83#include <xen/xenpmap.h>
84#endif /* XEN */
85
86/*
87 * The x86_64 pmap module closely resembles the i386 one and it
88 * uses the same recursive entry scheme. See the i386 pmap.h
89 * for a description. The obvious difference is that 3 extra
90 * levels of page table need to be dealt with. The level 1 page
91 * table pages are at:
92 *
93 * l1: 0x00007f8000000000 - 0x00007fffffffffff     (39 bits, needs PML4 entry)
94 *
95 * The rest is kept as physical pages in 3 UVM objects, and is
96 * temporarily mapped for virtual access when needed.
97 *
98 * Note that address space is signed, so the layout for 48 bits is:
99 *
100 *  +---------------------------------+ 0xffffffffffffffff
101 *  |                                 |
102 *  |         Unused                  |
103 *  |                                 |
104 *  +---------------------------------+ 0xffffff8000000000
105 *  ~                                 ~
106 *  |                                 |
107 *  |         Kernel Space            |
108 *  |                                 |
109 *  |                                 |
110 *  +---------------------------------+ 0xffff800000000000 = 0x0000800000000000
111 *  |                                 |
112 *  |    alt.L1 table (PTE pages)     |
113 *  |                                 |
114 *  +---------------------------------+ 0x00007f8000000000
115 *  ~                                 ~
116 *  |                                 |
117 *  |         User Space              |
118 *  |                                 |
119 *  |                                 |
120 *  +---------------------------------+ 0x0000000000000000
121 *
122 * In other words, there is a 'VA hole' at 0x0000800000000000 -
123 * 0xffff800000000000 which will trap, just as on, for example,
124 * sparcv9.
125 *
126 * The unused space can be used if needed, but it adds a little more
127 * complexity to the calculations.
128 */
129
130/*
131 * The first generation of Hammer processors can use 48 bits of
132 * virtual memory, and 40 bits of physical memory. This will be
133 * more for later generations. These defines can be changed to
134 * variable names containing the # of bits, extracted from an
135 * extended cpuid instruction (variables are harder to use during
136 * bootstrap, though)
137 */
138#define VIRT_BITS	48
139#define PHYS_BITS	40
140
141/*
142 * Mask to get rid of the sign-extended part of addresses.
143 */
144#define VA_SIGN_MASK		0xffff000000000000
145#define VA_SIGN_NEG(va)		((va) | VA_SIGN_MASK)
146/*
147 * XXXfvdl this one's not right.
148 */
149#define VA_SIGN_POS(va)		((va) & ~VA_SIGN_MASK)
150
151#define L4_SLOT_PTE		255
152#ifndef XEN
153#define L4_SLOT_KERN		256
154#else
155/* Xen use slots 256-272, let's move farther */
156#define L4_SLOT_KERN		320
157#endif
158#define L4_SLOT_KERNBASE	511
159
160#define PDIR_SLOT_KERN	L4_SLOT_KERN
161#define PDIR_SLOT_PTE	L4_SLOT_PTE
162
163/*
164 * The following defines give the virtual addresses of various MMU
165 * data structures:
166 * PTE_BASE: the base VA of the linear PTE mappings
167 * PDP_BASE: the base VA of the recursive mapping of the PTD
168 * PDP_PDE: the VA of the PDE that points back to the PDP
169 */
170
171#define PTE_BASE	((pt_entry_t *)(L4_SLOT_PTE * NBPD_L4))
172#define KERN_BASE	((pt_entry_t *)(L4_SLOT_KERN * NBPD_L4))
173
174#define L1_BASE	PTE_BASE
175#define L2_BASE	((pd_entry_t *)((char *)L1_BASE + L4_SLOT_PTE * NBPD_L3))
176#define L3_BASE	((pd_entry_t *)((char *)L2_BASE + L4_SLOT_PTE * NBPD_L2))
177#define L4_BASE	((pd_entry_t *)((char *)L3_BASE + L4_SLOT_PTE * NBPD_L1))
178
179#define PDP_PDE		(L4_BASE + PDIR_SLOT_PTE)
180
181#define PDP_BASE	L4_BASE
182
183#define NKL4_MAX_ENTRIES	(unsigned long)1
184#define NKL3_MAX_ENTRIES	(unsigned long)(NKL4_MAX_ENTRIES * 512)
185#define NKL2_MAX_ENTRIES	(unsigned long)(NKL3_MAX_ENTRIES * 512)
186#define NKL1_MAX_ENTRIES	(unsigned long)(NKL2_MAX_ENTRIES * 512)
187
188#define NKL4_KIMG_ENTRIES	1
189#define NKL3_KIMG_ENTRIES	1
190#define NKL2_KIMG_ENTRIES	32
191
192/*
193 * Since kva space is below the kernel in its entirety, we start off
194 * with zero entries on each level.
195 */
196#define NKL4_START_ENTRIES	0
197#define NKL3_START_ENTRIES	0
198#define NKL2_START_ENTRIES	0
199#define NKL1_START_ENTRIES	0	/* XXX */
200
201#define NTOPLEVEL_PDES		(PAGE_SIZE / (sizeof (pd_entry_t)))
202
203#define NPDPG			(PAGE_SIZE / sizeof (pd_entry_t))
204
205#define PTP_MASK_INITIALIZER	{ L1_FRAME, L2_FRAME, L3_FRAME, L4_FRAME }
206#define PTP_SHIFT_INITIALIZER	{ L1_SHIFT, L2_SHIFT, L3_SHIFT, L4_SHIFT }
207#define NKPTP_INITIALIZER	{ NKL1_START_ENTRIES, NKL2_START_ENTRIES, \
208				  NKL3_START_ENTRIES, NKL4_START_ENTRIES }
209#define NKPTPMAX_INITIALIZER	{ NKL1_MAX_ENTRIES, NKL2_MAX_ENTRIES, \
210				  NKL3_MAX_ENTRIES, NKL4_MAX_ENTRIES }
211#define NBPD_INITIALIZER	{ NBPD_L1, NBPD_L2, NBPD_L3, NBPD_L4 }
212#define PDES_INITIALIZER	{ L2_BASE, L3_BASE, L4_BASE }
213
214#define PTP_LEVELS	4
215
216/*
217 * PG_AVAIL usage: we make use of the ignored bits of the PTE
218 */
219
220#define PG_W		PG_AVAIL1	/* "wired" mapping */
221#define PG_PVLIST	PG_AVAIL2	/* mapping has entry on pvlist */
222/* PG_AVAIL3 not used */
223
224#define	PG_X		0		/* XXX dummy */
225
226/*
227 * Number of PTE's per cache line.  8 byte pte, 64-byte cache line
228 * Used to avoid false sharing of cache lines.
229 */
230#define NPTECL		8
231
232#include <x86/pmap.h>
233
234#ifndef XEN
235#define pmap_pa2pte(a)			(a)
236#define pmap_pte2pa(a)			((a) & PG_FRAME)
237#define pmap_pte_set(p, n)		do { *(p) = (n); } while (0)
238#define pmap_pte_cas(p, o, n)		atomic_cas_64((p), (o), (n))
239#define pmap_pte_testset(p, n)		\
240    atomic_swap_ulong((volatile unsigned long *)p, n)
241#define pmap_pte_setbits(p, b)		\
242    atomic_or_ulong((volatile unsigned long *)p, b)
243#define pmap_pte_clearbits(p, b)	\
244    atomic_and_ulong((volatile unsigned long *)p, ~(b))
245#define pmap_pte_flush()		/* nothing */
246#else
247extern kmutex_t pte_lock;
248
249static __inline pt_entry_t
250pmap_pa2pte(paddr_t pa)
251{
252	return (pt_entry_t)xpmap_ptom_masked(pa);
253}
254
255static __inline paddr_t
256pmap_pte2pa(pt_entry_t pte)
257{
258	return xpmap_mtop_masked(pte & PG_FRAME);
259}
260
261static __inline void
262pmap_pte_set(pt_entry_t *pte, pt_entry_t npte)
263{
264	int s = splvm();
265	xpq_queue_pte_update(xpmap_ptetomach(pte), npte);
266	splx(s);
267}
268
269static __inline pt_entry_t
270pmap_pte_cas(volatile pt_entry_t *ptep, pt_entry_t o, pt_entry_t n)
271{
272	pt_entry_t opte;
273
274	mutex_enter(&pte_lock);
275	opte = *ptep;
276	if (opte == o) {
277		xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(ptep)), n);
278		xpq_flush_queue();
279	}
280
281	mutex_exit(&pte_lock);
282	return opte;
283}
284
285static __inline pt_entry_t
286pmap_pte_testset(volatile pt_entry_t *pte, pt_entry_t npte)
287{
288	pt_entry_t opte;
289
290	mutex_enter(&pte_lock);
291	opte = *pte;
292	xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)), npte);
293	xpq_flush_queue();
294	mutex_exit(&pte_lock);
295	return opte;
296}
297
298static __inline void
299pmap_pte_setbits(volatile pt_entry_t *pte, pt_entry_t bits)
300{
301	mutex_enter(&pte_lock);
302	xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)), (*pte) | bits);
303	xpq_flush_queue();
304	mutex_exit(&pte_lock);
305}
306
307static __inline void
308pmap_pte_clearbits(volatile pt_entry_t *pte, pt_entry_t bits)
309{
310	mutex_enter(&pte_lock);
311	xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)),
312	    (*pte) & ~bits);
313	xpq_flush_queue();
314	mutex_exit(&pte_lock);
315}
316
317static __inline void
318pmap_pte_flush(void)
319{
320	int s = splvm();
321	xpq_flush_queue();
322	splx(s);
323}
324#endif
325
326void pmap_prealloc_lowmem_ptps(void);
327void pmap_changeprot_local(vaddr_t, vm_prot_t);
328
329#include <x86/pmap_pv.h>
330
331#define	__HAVE_VM_PAGE_MD
332#define	VM_MDPAGE_INIT(pg) \
333	memset(&(pg)->mdpage, 0, sizeof((pg)->mdpage)); \
334	PMAP_PAGE_INIT(&(pg)->mdpage.mp_pp)
335
336struct vm_page_md {
337	struct pmap_page mp_pp;
338};
339
340#else	/*	!__x86_64__	*/
341
342#include <i386/pmap.h>
343
344#endif	/*	__x86_64__	*/
345
346#endif	/* _AMD64_PMAP_H_ */
347