pmap.h revision 1.52 
1/*	$NetBSD: pmap.h,v 1.52 2018/08/12 12:42:53 maxv Exp $	*/
2
3/*
4 * Copyright (c) 1997 Charles D. Cranor and Washington University.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28/*
29 * Copyright (c) 2001 Wasabi Systems, Inc.
30 * All rights reserved.
31 *
32 * Written by Frank van der Linden for Wasabi Systems, Inc.
33 *
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
36 * are met:
37 * 1. Redistributions of source code must retain the above copyright
38 *    notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 *    notice, this list of conditions and the following disclaimer in the
41 *    documentation and/or other materials provided with the distribution.
42 * 3. All advertising materials mentioning features or use of this software
43 *    must display the following acknowledgement:
44 *      This product includes software developed for the NetBSD Project by
45 *      Wasabi Systems, Inc.
46 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
47 *    or promote products derived from this software without specific prior
48 *    written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
51 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
52 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
53 * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
54 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
60 * POSSIBILITY OF SUCH DAMAGE.
61 */
62
63#ifndef	_AMD64_PMAP_H_
64#define	_AMD64_PMAP_H_
65
66#ifdef __x86_64__
67
68#if defined(_KERNEL_OPT)
69#include "opt_xen.h"
70#endif
71
72#include <sys/atomic.h>
73
74#include <machine/pte.h>
75#include <machine/segments.h>
76#ifdef _KERNEL
77#include <machine/cpufunc.h>
78#endif
79
80#include <uvm/uvm_object.h>
81#ifdef XEN
82#include <xen/xenfunc.h>
83#include <xen/xenpmap.h>
84#endif /* XEN */
85
86/*
87 * The x86_64 pmap module closely resembles the i386 one and it
88 * uses the same recursive entry scheme. See the i386 pmap.h
89 * for a description. The obvious difference is that 3 extra
90 * levels of page table need to be dealt with. The level 1 page
91 * table pages are at:
92 *
93 * l1: 0x00007f8000000000 - 0x00007fffffffffff     (39 bits, needs PML4 entry)
94 *
95 * The rest is kept as physical pages in 3 UVM objects, and is
96 * temporarily mapped for virtual access when needed.
97 *
98 * Note that address space is signed, so the layout for 48 bits is:
99 *
100 *  +---------------------------------+ 0xffffffffffffffff
101 *  |                                 |
102 *  |         Unused                  |
103 *  |                                 |
104 *  +---------------------------------+ 0xffffff8000000000
105 *  ~                                 ~
106 *  |                                 |
107 *  |         Kernel Space            |
108 *  |                                 |
109 *  |                                 |
110 *  +---------------------------------+ 0xffff800000000000 = 0x0000800000000000
111 *  |                                 |
112 *  |    alt.L1 table (PTE pages)     |
113 *  |                                 |
114 *  +---------------------------------+ 0x00007f8000000000
115 *  ~                                 ~
116 *  |                                 |
117 *  |         User Space              |
118 *  |                                 |
119 *  |                                 |
120 *  +---------------------------------+ 0x0000000000000000
121 *
122 * In other words, there is a 'VA hole' at 0x0000800000000000 -
123 * 0xffff800000000000 which will trap, just as on, for example,
124 * sparcv9.
125 *
126 * The unused space can be used if needed, but it adds a little more
127 * complexity to the calculations.
128 */
129
130/*
131 * Mask to get rid of the sign-extended part of addresses.
132 */
133#define VA_SIGN_MASK		0xffff000000000000
134#define VA_SIGN_NEG(va)		((va) | VA_SIGN_MASK)
135/*
136 * XXXfvdl this one's not right.
137 */
138#define VA_SIGN_POS(va)		((va) & ~VA_SIGN_MASK)
139
140#define L4_SLOT_PTE		509
141#define L4_SLOT_KERN		slotspace.area[SLAREA_MAIN].sslot
142#define L4_SLOT_KERNBASE	511 /* pl4_i(KERNBASE) */
143
144#define PDIR_SLOT_USERLIM	255
145#define PDIR_SLOT_KERN	L4_SLOT_KERN
146#define PDIR_SLOT_PTE	L4_SLOT_PTE
147
148/*
149 * The following defines give the virtual addresses of various MMU
150 * data structures:
151 * PTE_BASE: the base VA of the linear PTE mappings
152 * PDP_BASE: the base VA of the recursive mapping of the PTD
153 * PDP_PDE: the VA of the PDE that points back to the PDP
154 */
155
156#define PTE_BASE	((pt_entry_t *)VA_SIGN_NEG((L4_SLOT_PTE * NBPD_L4)))
157
158#define L1_BASE	PTE_BASE
159#define L2_BASE	((pd_entry_t *)((char *)L1_BASE + L4_SLOT_PTE * NBPD_L3))
160#define L3_BASE	((pd_entry_t *)((char *)L2_BASE + L4_SLOT_PTE * NBPD_L2))
161#define L4_BASE	((pd_entry_t *)((char *)L3_BASE + L4_SLOT_PTE * NBPD_L1))
162
163#define PDP_PDE		(L4_BASE + PDIR_SLOT_PTE)
164
165#define PDP_BASE	L4_BASE
166
167#define NKL4_MAX_ENTRIES	(unsigned long)64
168#define NKL3_MAX_ENTRIES	(unsigned long)(NKL4_MAX_ENTRIES * 512)
169#define NKL2_MAX_ENTRIES	(unsigned long)(NKL3_MAX_ENTRIES * 512)
170#define NKL1_MAX_ENTRIES	(unsigned long)(NKL2_MAX_ENTRIES * 512)
171
172#define NKL4_KIMG_ENTRIES	1
173#define NKL3_KIMG_ENTRIES	1
174#define NKL2_KIMG_ENTRIES	48
175
176/*
177 * Since kva space is below the kernel in its entirety, we start off
178 * with zero entries on each level.
179 */
180#define NKL4_START_ENTRIES	0
181#define NKL3_START_ENTRIES	0
182#define NKL2_START_ENTRIES	0
183#define NKL1_START_ENTRIES	0	/* XXX */
184
185#define NTOPLEVEL_PDES		(PAGE_SIZE / (sizeof (pd_entry_t)))
186
187#define NPDPG			(PAGE_SIZE / sizeof (pd_entry_t))
188
189#define PTP_MASK_INITIALIZER	{ L1_FRAME, L2_FRAME, L3_FRAME, L4_FRAME }
190#define PTP_SHIFT_INITIALIZER	{ L1_SHIFT, L2_SHIFT, L3_SHIFT, L4_SHIFT }
191#define NKPTP_INITIALIZER	{ NKL1_START_ENTRIES, NKL2_START_ENTRIES, \
192				  NKL3_START_ENTRIES, NKL4_START_ENTRIES }
193#define NKPTPMAX_INITIALIZER	{ NKL1_MAX_ENTRIES, NKL2_MAX_ENTRIES, \
194				  NKL3_MAX_ENTRIES, NKL4_MAX_ENTRIES }
195#define NBPD_INITIALIZER	{ NBPD_L1, NBPD_L2, NBPD_L3, NBPD_L4 }
196#define PDES_INITIALIZER	{ L2_BASE, L3_BASE, L4_BASE }
197
198#define PTP_LEVELS	4
199
200/*
201 * PG_AVAIL usage: we make use of the ignored bits of the PTE
202 */
203
204#define PG_W		PG_AVAIL1	/* "wired" mapping */
205#define PG_PVLIST	PG_AVAIL2	/* mapping has entry on pvlist */
206/* PG_AVAIL3 not used */
207
208#define	PG_X		0		/* XXX dummy */
209
210void svs_pmap_sync(struct pmap *, int);
211void svs_lwp_switch(struct lwp *, struct lwp *);
212void svs_pdir_switch(struct pmap *);
213void svs_init(void);
214extern bool svs_enabled;
215
216#include <x86/pmap.h>
217
218#ifndef XEN
219#define pmap_pa2pte(a)			(a)
220#define pmap_pte2pa(a)			((a) & PG_FRAME)
221#define pmap_pte_set(p, n)		do { *(p) = (n); } while (0)
222#define pmap_pte_cas(p, o, n)		atomic_cas_64((p), (o), (n))
223#define pmap_pte_testset(p, n)		\
224    atomic_swap_ulong((volatile unsigned long *)p, n)
225#define pmap_pte_setbits(p, b)		\
226    atomic_or_ulong((volatile unsigned long *)p, b)
227#define pmap_pte_clearbits(p, b)	\
228    atomic_and_ulong((volatile unsigned long *)p, ~(b))
229#define pmap_pte_flush()		/* nothing */
230#else
231extern kmutex_t pte_lock;
232
233static __inline pt_entry_t
234pmap_pa2pte(paddr_t pa)
235{
236	return (pt_entry_t)xpmap_ptom_masked(pa);
237}
238
239static __inline paddr_t
240pmap_pte2pa(pt_entry_t pte)
241{
242	return xpmap_mtop_masked(pte & PG_FRAME);
243}
244
245static __inline void
246pmap_pte_set(pt_entry_t *pte, pt_entry_t npte)
247{
248	int s = splvm();
249	xpq_queue_pte_update(xpmap_ptetomach(pte), npte);
250	splx(s);
251}
252
253static __inline pt_entry_t
254pmap_pte_cas(volatile pt_entry_t *ptep, pt_entry_t o, pt_entry_t n)
255{
256	pt_entry_t opte;
257
258	mutex_enter(&pte_lock);
259	opte = *ptep;
260	if (opte == o) {
261		xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(ptep)), n);
262		xpq_flush_queue();
263	}
264
265	mutex_exit(&pte_lock);
266	return opte;
267}
268
269static __inline pt_entry_t
270pmap_pte_testset(volatile pt_entry_t *pte, pt_entry_t npte)
271{
272	pt_entry_t opte;
273
274	mutex_enter(&pte_lock);
275	opte = *pte;
276	xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)), npte);
277	xpq_flush_queue();
278	mutex_exit(&pte_lock);
279	return opte;
280}
281
282static __inline void
283pmap_pte_setbits(volatile pt_entry_t *pte, pt_entry_t bits)
284{
285	mutex_enter(&pte_lock);
286	xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)), (*pte) | bits);
287	xpq_flush_queue();
288	mutex_exit(&pte_lock);
289}
290
291static __inline void
292pmap_pte_clearbits(volatile pt_entry_t *pte, pt_entry_t bits)
293{
294	mutex_enter(&pte_lock);
295	xpq_queue_pte_update(xpmap_ptetomach(__UNVOLATILE(pte)),
296	    (*pte) & ~bits);
297	xpq_flush_queue();
298	mutex_exit(&pte_lock);
299}
300
301static __inline void
302pmap_pte_flush(void)
303{
304	int s = splvm();
305	xpq_flush_queue();
306	splx(s);
307}
308#endif
309
310#ifdef __HAVE_DIRECT_MAP
311#define PMAP_DIRECT
312
313static __inline int
314pmap_direct_process(paddr_t pa, voff_t pgoff, size_t len,
315    int (*process)(void *, size_t, void *), void *arg)
316{
317	vaddr_t va = PMAP_DIRECT_MAP(pa);
318
319	return process((void *)(va + pgoff), len, arg);
320}
321
322#endif /* __HAVE_DIRECT_MAP */
323
324void pmap_changeprot_local(vaddr_t, vm_prot_t);
325
326#include <x86/pmap_pv.h>
327
328#define	__HAVE_VM_PAGE_MD
329#define	VM_MDPAGE_INIT(pg) \
330	memset(&(pg)->mdpage, 0, sizeof((pg)->mdpage)); \
331	PMAP_PAGE_INIT(&(pg)->mdpage.mp_pp)
332
333struct vm_page_md {
334	struct pmap_page mp_pp;
335};
336
337#else	/*	!__x86_64__	*/
338
339#include <i386/pmap.h>
340
341#endif	/*	__x86_64__	*/
342
343#endif	/* _AMD64_PMAP_H_ */
344