1 1.7 snj /* $NetBSD: flscvar.h,v 1.7 2009/10/21 23:53:38 snj Exp $ */ 2 1.2 veego 3 1.1 chopps /* 4 1.3 mhitch * Copyright (c) 1997 Michael L. Hitch. 5 1.3 mhitch * All rights reserved. 6 1.1 chopps * 7 1.1 chopps * Redistribution and use in source and binary forms, with or without 8 1.1 chopps * modification, are permitted provided that the following conditions 9 1.1 chopps * are met: 10 1.1 chopps * 1. Redistributions of source code must retain the above copyright 11 1.1 chopps * notice, this list of conditions and the following disclaimer. 12 1.1 chopps * 2. Redistributions in binary form must reproduce the above copyright 13 1.1 chopps * notice, this list of conditions and the following disclaimer in the 14 1.1 chopps * documentation and/or other materials provided with the distribution. 15 1.1 chopps * 16 1.1 chopps * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 1.1 chopps * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 1.1 chopps * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 1.1 chopps * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 1.1 chopps * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 1.1 chopps * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 1.1 chopps * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 1.1 chopps * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 1.1 chopps * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 1.1 chopps * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 1.1 chopps */ 27 1.1 chopps 28 1.3 mhitch struct flsc_softc { 29 1.3 mhitch struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 30 1.3 mhitch 31 1.6 tsutsui struct isr sc_isr; /* Interrupt chain struct */ 32 1.3 mhitch 33 1.6 tsutsui volatile uint8_t *sc_reg; /* the registers */ 34 1.6 tsutsui volatile uint8_t *sc_dmabase; 35 1.3 mhitch 36 1.3 mhitch int sc_active; /* Pseudo-DMA state vars */ 37 1.3 mhitch int sc_piomode; 38 1.3 mhitch int sc_datain; 39 1.3 mhitch int sc_tc; 40 1.3 mhitch size_t sc_dmasize; 41 1.3 mhitch size_t sc_dmatrans; 42 1.6 tsutsui uint8_t **sc_dmaaddr; 43 1.3 mhitch size_t *sc_pdmalen; 44 1.5 is paddr_t sc_pa; 45 1.3 mhitch 46 1.6 tsutsui uint8_t *sc_alignbuf; 47 1.6 tsutsui uint8_t sc_pad1[2]; /* XXX */ 48 1.6 tsutsui uint8_t sc_unalignbuf[256]; 49 1.6 tsutsui uint8_t sc_pad2[16]; 50 1.6 tsutsui uint8_t sc_hardbits; 51 1.6 tsutsui uint8_t sc_portbits; 52 1.6 tsutsui uint8_t sc_csr; 53 1.6 tsutsui uint8_t sc_xfr_align; 54 1.1 chopps }; 55 1.1 chopps 56 1.3 mhitch #define FLSC_HB_DISABLED 0x01 57 1.3 mhitch #define FLSC_HB_BUSID6 0x02 58 1.3 mhitch #define FLSC_HB_SEAGATE 0x04 59 1.3 mhitch #define FLSC_HB_SLOW 0x08 60 1.3 mhitch #define FLSC_HB_SYNCHRON 0x10 61 1.3 mhitch #define FLSC_HB_CREQ 0x20 62 1.3 mhitch #define FLSC_HB_IACT 0x40 63 1.3 mhitch #define FLSC_HB_MINT 0x80 64 1.3 mhitch 65 1.3 mhitch #define FLSC_PB_ESI 0x01 66 1.3 mhitch #define FLSC_PB_EDI 0x02 67 1.3 mhitch #define FLSC_PB_ENABLE_DMA 0x04 68 1.3 mhitch #define FLSC_PB_DISABLE_DMA 0x00 /* Symmetric reasons */ 69 1.3 mhitch #define FLSC_PB_DMA_WRITE 0x08 70 1.3 mhitch #define FLSC_PB_DMA_READ 0x00 /* Symmetric reasons */ 71 1.3 mhitch #define FLSC_PB_LED 0x10 72 1.1 chopps 73 1.3 mhitch #define FLSC_PB_INT_BITS (FLSC_PB_ESI | FLSC_PB_EDI) 74 1.3 mhitch #define FLSC_PB_DMA_BITS (FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_WRITE) 75
Indexes created Mon Sep 22 05:09:51 GMT 2025