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      1 /*	$NetBSD: flscvar.h,v 1.7 2009/10/21 23:53:38 snj Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1997 Michael L. Hitch.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     21  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     22  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     23  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     25  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 
     28 struct flsc_softc {
     29 	struct ncr53c9x_softc	sc_ncr53c9x;	/* glue to MI code */
     30 
     31 	struct isr	sc_isr;			/* Interrupt chain struct */
     32 
     33 	volatile uint8_t *sc_reg;		/* the registers */
     34 	volatile uint8_t *sc_dmabase;
     35 
     36 	int		sc_active;		/* Pseudo-DMA state vars */
     37 	int		sc_piomode;
     38 	int		sc_datain;
     39 	int		sc_tc;
     40 	size_t		sc_dmasize;
     41 	size_t		sc_dmatrans;
     42 	uint8_t		**sc_dmaaddr;
     43 	size_t		*sc_pdmalen;
     44 	paddr_t		sc_pa;
     45 
     46 	uint8_t		*sc_alignbuf;
     47 	uint8_t		sc_pad1[2];		/* XXX */
     48 	uint8_t		sc_unalignbuf[256];
     49 	uint8_t		sc_pad2[16];
     50 	uint8_t		sc_hardbits;
     51 	uint8_t		sc_portbits;
     52 	uint8_t		sc_csr;
     53 	uint8_t		sc_xfr_align;
     54 };
     55 
     56 #define FLSC_HB_DISABLED	0x01
     57 #define FLSC_HB_BUSID6		0x02
     58 #define FLSC_HB_SEAGATE		0x04
     59 #define FLSC_HB_SLOW		0x08
     60 #define FLSC_HB_SYNCHRON	0x10
     61 #define FLSC_HB_CREQ		0x20
     62 #define FLSC_HB_IACT		0x40
     63 #define FLSC_HB_MINT		0x80
     64 
     65 #define FLSC_PB_ESI		0x01
     66 #define FLSC_PB_EDI		0x02
     67 #define FLSC_PB_ENABLE_DMA	0x04
     68 #define FLSC_PB_DISABLE_DMA	0x00	/* Symmetric reasons */
     69 #define FLSC_PB_DMA_WRITE	0x08
     70 #define FLSC_PB_DMA_READ	0x00	/* Symmetric reasons */
     71 #define FLSC_PB_LED		0x10
     72 
     73 #define FLSC_PB_INT_BITS (FLSC_PB_ESI | FLSC_PB_EDI)
     74 #define FLSC_PB_DMA_BITS (FLSC_PB_ENABLE_DMA | FLSC_PB_DMA_WRITE)
     75