1 /* $NetBSD: if_qnreg.h,v 1.2 1995/11/30 00:57:04 jtc Exp $ */ 2 3 /* 4 * Copyright (c) 1995 Mika Kortelainen 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Mika Kortelainen 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * Thanks for Aspecs Oy (Finland) for the data book for the NIC used 33 * in this card and also many thanks for the Resource Management Force 34 * (QuickNet card manufacturer) and especially Daniel Koch for providing 35 * me with the necessary 'inside' information to write the driver. 36 * 37 */ 38 39 /* 40 * The QuickNet card uses the Fujitsu's MB86950B NIC (Network Interface 41 * Controller) chip, located at card base address + 0xff00. NIC registers 42 * are accessible only at even byte addresses, so the register offsets must 43 * be multiplied by two. Actually, these registers are read/written as words. 44 * 45 * As the card doesn't use DMA, data is input/output at FIFO register 46 * (base address + 0xff20). The card has 64K buffer memory and is pretty 47 * fast despite the lack of DMA. 48 * 49 * The FIFO register MUST be accessed as a word (16 bits). 50 * 51 */ 52 53 #define QUICKNET_NIC_BASE 0xff00 54 55 56 #define NIC_DLCR0 ( 0 ) /* Transmit status */ 57 #define NIC_DLCR1 ( 1 * 2) /* Transmit masks */ 58 #define NIC_DLCR2 ( 2 * 2) /* Receive status */ 59 #define NIC_DLCR3 ( 3 * 2) /* Receive masks */ 60 #define NIC_DLCR4 ( 4 * 2) /* Transmit mode */ 61 #define NIC_DLCR5 ( 5 * 2) /* Receive mode */ 62 #define NIC_DLCR6 ( 6 * 2) /* Software reset */ 63 #define NIC_DLCR7 ( 7 * 2) /* TDR (LSB) */ 64 #define NIC_DLCR8 ( 8 * 2) /* Node ID0 */ 65 #define NIC_DLCR9 ( 9 * 2) /* Node ID1 */ 66 #define NIC_DLCR10 (10 * 2) /* Node ID2 */ 67 #define NIC_DLCR11 (11 * 2) /* Node ID3 */ 68 #define NIC_DLCR12 (12 * 2) /* Node ID4 */ 69 #define NIC_DLCR13 (13 * 2) /* Node ID5 */ 70 #define NIC_DLCR15 (15 * 2) /* TDR (MSB) */ 71 #define NIC_BMPR0 (16 * 2) /* Buffer memory port (FIFO) */ 72 #define NIC_BMPR2 (18 * 2) /* Packet length */ 73 #define NIC_BMPR4 (20 * 2) /* DMA enable */ 74 75 #define QNET_MAGIC 0x30 /* GAL magic */ 76 77 78 /* DLCR0 - Transmit Status */ 79 #define BUS_WRITE_ERROR 0x0101 /* Bus write error */ 80 #define T_SIXTEEN_COL 0x0202 /* 16 collision */ 81 #define T_COL 0x0404 /* Collision */ 82 #define T_UNDERFLOW 0x0808 /* Underflow */ 83 #define T_TMT_OK 0x8080 /* Transmit okay */ 84 #define CLEAR_T_ERR 0x0f0f /* Clear transmit errors */ 85 86 /* DLCR1 - Transmit Interrupt Masks */ 87 #define INT_SIXTEEN_COL 0x0202 /* 16 Collision */ 88 #define INT_TMT_OK 0x8080 /* Transmit okay */ 89 #define CLEAR_T_MASK 0x0000 /* Clear transmit interrupt masks */ 90 91 /* DLCR2 - Receive Status */ 92 #define R_BUS_RD_ERR 0x4040 /* Bus read error */ 93 #define R_PKT_RDY 0x8080 /* Packet ready */ 94 #define CLEAR_R_ERR 0xcfcf /* Clear receive errors */ 95 96 /* DLCR3 - Receive Interrupt Masks */ 97 #define R_INT_OVR_FLO 0x0101 /* Receive buf overflow */ 98 #define R_INT_CRC_ERR 0x0202 /* CRC error */ 99 #define R_INT_ALG_ERR 0x0404 /* Alignment error */ 100 #define R_INT_SRT_PKT 0x0808 /* Short packet */ 101 #define R_INT_PKT_RDY 0x8080 /* Packet ready */ 102 #define CLEAR_R_MASK 0x0000 /* Clear receive intr masks */ 103 104 /* DLCR4 - Transmit Mode */ 105 #define NO_LOOPBACK 0x0202 /* Loopback control */ 106 107 /* DLCR5 - Receive Mode */ 108 /* Normal mode: accept physical address, multicast group addresses 109 * which match the 1st three bytes and broadcast address. 110 */ 111 #define NORMAL_MODE 0x0101 112 #define PROMISCUOUS_MODE 0x0303 /* Accept all packets */ 113 #define RM_BUF_EMP 0x4040 /* Buffer empty */ 114 115 /* DLCR6 - Enable Data Link Controller */ 116 #define DISABLE_DLC 0x8080 /* Disable data link controller */ 117 #define ENABLE_DLC 0x0000 /* Enable data link controller */ 118 119 /* DLCR8:DLCR13 - Node ID Registers */ 120 #define QNET_HARDWARE_ADDRESS NIC_DLCR8 121 122 /* BMPR3:BMPR2 - Packet Length Registers (Write-only) */ 123 #define TRANSMIT_START 0x0080 124
Indexes created Sun Sep 21 18:09:52 GMT 2025