wstsc.c revision 1.11
1 /* $NetBSD: wstsc.c,v 1.11 1996/04/21 21:12:43 veego Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)supradma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <scsi/scsi_all.h> 43 #include <scsi/scsiconf.h> 44 #include <amiga/amiga/device.h> 45 #include <amiga/amiga/isr.h> 46 #include <amiga/dev/scireg.h> 47 #include <amiga/dev/scivar.h> 48 #include <amiga/dev/zbusvar.h> 49 50 int wstscprint __P((void *auxp, char *)); 51 void wstscattach __P((struct device *, struct device *, void *)); 52 int wstscmatch __P((struct device *, void *, void *)); 53 54 int wstsc_dma_xfer_in __P((struct sci_softc *dev, int len, 55 register u_char *buf, int phase)); 56 int wstsc_dma_xfer_out __P((struct sci_softc *dev, int len, 57 register u_char *buf, int phase)); 58 int wstsc_dma_xfer_in2 __P((struct sci_softc *dev, int len, 59 register u_short *buf, int phase)); 60 int wstsc_dma_xfer_out2 __P((struct sci_softc *dev, int len, 61 register u_short *buf, int phase)); 62 int wstsc_intr __P((void *)); 63 64 struct scsi_adapter wstsc_scsiswitch = { 65 sci_scsicmd, 66 sci_minphys, 67 0, /* no lun support */ 68 0, /* no lun support */ 69 }; 70 71 struct scsi_device wstsc_scsidev = { 72 NULL, /* use default error handler */ 73 NULL, /* do not have a start functio */ 74 NULL, /* have no async handler */ 75 NULL, /* Use default done routine */ 76 }; 77 78 #ifdef DEBUG 79 extern int sci_debug; 80 #define QPRINTF(a) if (sci_debug > 1) printf a 81 #else 82 #define QPRINTF(a) 83 #endif 84 85 extern int sci_data_wait; 86 87 int supradma_pseudo = 0; /* 0=none, 1=byte, 2=word */ 88 89 struct cfattach wstsc_ca = { 90 sizeof(struct sci_softc), wstscmatch, wstscattach 91 }; 92 93 struct cfdriver wstsc_cd = { 94 NULL, "wstsc", DV_DULL, NULL, 0 95 }; 96 97 /* 98 * if this a Supra WordSync board 99 */ 100 int 101 wstscmatch(pdp, match, auxp) 102 struct device *pdp; 103 void *match, *auxp; 104 { 105 struct zbus_args *zap; 106 107 zap = auxp; 108 109 /* 110 * Check manufacturer and product id. 111 */ 112 if (zap->manid == 1056 && ( 113 zap->prodid == 12 || /* WordSync */ 114 zap->prodid == 13)) /* ByteSync */ 115 return(1); 116 else 117 return(0); 118 } 119 120 void 121 wstscattach(pdp, dp, auxp) 122 struct device *pdp, *dp; 123 void *auxp; 124 { 125 volatile u_char *rp; 126 struct sci_softc *sc; 127 struct zbus_args *zap; 128 129 printf("\n"); 130 131 zap = auxp; 132 133 sc = (struct sci_softc *)dp; 134 rp = zap->va; 135 /* 136 * set up 5380 register pointers 137 * (Needs check on which Supra board this is - for now, 138 * just do the WordSync) 139 */ 140 sc->sci_data = rp + 0; 141 sc->sci_odata = rp + 0; 142 sc->sci_icmd = rp + 2; 143 sc->sci_mode = rp + 4; 144 sc->sci_tcmd = rp + 6; 145 sc->sci_bus_csr = rp + 8; 146 sc->sci_sel_enb = rp + 8; 147 sc->sci_csr = rp + 10; 148 sc->sci_dma_send = rp + 10; 149 sc->sci_idata = rp + 12; 150 sc->sci_trecv = rp + 12; 151 sc->sci_iack = rp + 14; 152 sc->sci_irecv = rp + 14; 153 154 if (supradma_pseudo == 2) { 155 sc->dma_xfer_in = wstsc_dma_xfer_in2; 156 sc->dma_xfer_out = wstsc_dma_xfer_out2; 157 } 158 else if (supradma_pseudo == 1) { 159 sc->dma_xfer_in = wstsc_dma_xfer_in; 160 sc->dma_xfer_out = wstsc_dma_xfer_out; 161 } 162 163 sc->sc_isr.isr_intr = wstsc_intr; 164 sc->sc_isr.isr_arg = sc; 165 sc->sc_isr.isr_ipl = 2; 166 add_isr(&sc->sc_isr); 167 168 scireset(sc); 169 170 sc->sc_link.adapter_softc = sc; 171 sc->sc_link.adapter_target = 7; 172 sc->sc_link.adapter = &wstsc_scsiswitch; 173 sc->sc_link.device = &wstsc_scsidev; 174 sc->sc_link.openings = 1; 175 TAILQ_INIT(&sc->sc_xslist); 176 177 /* 178 * attach all scsi units on us 179 */ 180 config_found(dp, &sc->sc_link, wstscprint); 181 } 182 183 /* 184 * print diag if pnp is NULL else just extra 185 */ 186 int 187 wstscprint(auxp, pnp) 188 void *auxp; 189 char *pnp; 190 { 191 if (pnp == NULL) 192 return(UNCONF); 193 return(QUIET); 194 } 195 196 int 197 wstsc_dma_xfer_in (dev, len, buf, phase) 198 struct sci_softc *dev; 199 int len; 200 register u_char *buf; 201 int phase; 202 { 203 int wait = sci_data_wait; 204 volatile register u_char *sci_dma = dev->sci_idata; 205 volatile register u_char *sci_csr = dev->sci_csr; 206 #ifdef DEBUG 207 u_char *obp = (u_char *) buf; 208 #endif 209 210 QPRINTF(("supradma_in %d, csr=%02x\n", len, *dev->sci_bus_csr)); 211 212 *dev->sci_tcmd = phase; 213 *dev->sci_icmd = 0; 214 *dev->sci_mode = SCI_MODE_DMA; 215 *dev->sci_irecv = 0; 216 217 while (len >= 128) { 218 wait = sci_data_wait; 219 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 220 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 221 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 222 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 223 || --wait < 0) { 224 #ifdef DEBUG 225 if (sci_debug | 1) 226 printf("supradma2_in fail: l%d i%x w%d\n", 227 len, *dev->sci_bus_csr, wait); 228 #endif 229 *dev->sci_mode = 0; 230 return 0; 231 } 232 } 233 234 #define R1 (*buf++ = *sci_dma) 235 R1; R1; R1; R1; R1; R1; R1; R1; 236 R1; R1; R1; R1; R1; R1; R1; R1; 237 R1; R1; R1; R1; R1; R1; R1; R1; 238 R1; R1; R1; R1; R1; R1; R1; R1; 239 R1; R1; R1; R1; R1; R1; R1; R1; 240 R1; R1; R1; R1; R1; R1; R1; R1; 241 R1; R1; R1; R1; R1; R1; R1; R1; 242 R1; R1; R1; R1; R1; R1; R1; R1; 243 R1; R1; R1; R1; R1; R1; R1; R1; 244 R1; R1; R1; R1; R1; R1; R1; R1; 245 R1; R1; R1; R1; R1; R1; R1; R1; 246 R1; R1; R1; R1; R1; R1; R1; R1; 247 R1; R1; R1; R1; R1; R1; R1; R1; 248 R1; R1; R1; R1; R1; R1; R1; R1; 249 R1; R1; R1; R1; R1; R1; R1; R1; 250 R1; R1; R1; R1; R1; R1; R1; R1; 251 len -= 128; 252 } 253 254 while (len > 0) { 255 wait = sci_data_wait; 256 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 257 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 258 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 259 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 260 || --wait < 0) { 261 #ifdef DEBUG 262 if (sci_debug | 1) 263 printf("supradma1_in fail: l%d i%x w%d\n", 264 len, *dev->sci_bus_csr, wait); 265 #endif 266 *dev->sci_mode = 0; 267 return 0; 268 } 269 } 270 271 *buf++ = *sci_dma; 272 len--; 273 } 274 275 QPRINTF(("supradma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 276 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 277 obp[6], obp[7], obp[8], obp[9])); 278 279 *dev->sci_mode = 0; 280 return 0; 281 } 282 283 int 284 wstsc_dma_xfer_out (dev, len, buf, phase) 285 struct sci_softc *dev; 286 int len; 287 register u_char *buf; 288 int phase; 289 { 290 int wait = sci_data_wait; 291 volatile register u_char *sci_dma = dev->sci_data; 292 volatile register u_char *sci_csr = dev->sci_csr; 293 294 QPRINTF(("supradma_out %d, csr=%02x\n", len, *dev->sci_bus_csr)); 295 296 QPRINTF(("supradma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 297 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 298 buf[6], buf[7], buf[8], buf[9])); 299 300 *dev->sci_tcmd = phase; 301 *dev->sci_mode = SCI_MODE_DMA; 302 *dev->sci_icmd = SCI_ICMD_DATA; 303 *dev->sci_dma_send = 0; 304 while (len > 0) { 305 wait = sci_data_wait; 306 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 307 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 308 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 309 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 310 || --wait < 0) { 311 #ifdef DEBUG 312 if (sci_debug) 313 printf("supradma_out fail: l%d i%x w%d\n", 314 len, *dev->sci_bus_csr, wait); 315 #endif 316 *dev->sci_mode = 0; 317 return 0; 318 } 319 } 320 321 *sci_dma = *buf++; 322 len--; 323 } 324 325 wait = sci_data_wait; 326 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 327 SCI_CSR_PHASE_MATCH && --wait); 328 329 330 *dev->sci_mode = 0; 331 *dev->sci_icmd = 0; 332 return 0; 333 } 334 335 336 int 337 wstsc_dma_xfer_in2 (dev, len, buf, phase) 338 struct sci_softc *dev; 339 int len; 340 register u_short *buf; 341 int phase; 342 { 343 volatile register u_short *sci_dma = (u_short *)(dev->sci_idata + 0x10); 344 volatile register u_char *sci_csr = dev->sci_csr + 0x10; 345 #ifdef DEBUG 346 u_char *obp = (u_char *) buf; 347 #endif 348 #if 0 349 int wait = sci_data_wait; 350 #endif 351 352 QPRINTF(("supradma_in2 %d, csr=%02x\n", len, *dev->sci_bus_csr)); 353 354 *dev->sci_tcmd = phase; 355 *dev->sci_mode = SCI_MODE_DMA; 356 *dev->sci_icmd = 0; 357 *(dev->sci_irecv + 16) = 0; 358 while (len >= 128) { 359 #if 0 360 wait = sci_data_wait; 361 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 362 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 363 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 364 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 365 || --wait < 0) { 366 #ifdef DEBUG 367 if (sci_debug | 1) 368 printf("supradma2_in2 fail: l%d i%x w%d\n", 369 len, *dev->sci_bus_csr, wait); 370 #endif 371 *dev->sci_mode &= ~SCI_MODE_DMA; 372 return 0; 373 } 374 } 375 #else 376 while (!(*sci_csr & SCI_CSR_DREQ)) 377 ; 378 #endif 379 380 #define R2 (*buf++ = *sci_dma) 381 R2; R2; R2; R2; R2; R2; R2; R2; 382 R2; R2; R2; R2; R2; R2; R2; R2; 383 R2; R2; R2; R2; R2; R2; R2; R2; 384 R2; R2; R2; R2; R2; R2; R2; R2; 385 R2; R2; R2; R2; R2; R2; R2; R2; 386 R2; R2; R2; R2; R2; R2; R2; R2; 387 R2; R2; R2; R2; R2; R2; R2; R2; 388 R2; R2; R2; R2; R2; R2; R2; R2; 389 len -= 128; 390 } 391 while (len > 0) { 392 #if 0 393 wait = sci_data_wait; 394 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 395 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 396 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 397 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 398 || --wait < 0) { 399 #ifdef DEBUG 400 if (sci_debug | 1) 401 printf("supradma1_in2 fail: l%d i%x w%d\n", 402 len, *dev->sci_bus_csr, wait); 403 #endif 404 *dev->sci_mode &= ~SCI_MODE_DMA; 405 return 0; 406 } 407 } 408 #else 409 while (!(*sci_csr * SCI_CSR_DREQ)) 410 ; 411 #endif 412 413 *buf++ = *sci_dma; 414 len -= 2; 415 } 416 417 QPRINTF(("supradma_in2 {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 418 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 419 obp[6], obp[7], obp[8], obp[9])); 420 421 *dev->sci_irecv = 0; 422 *dev->sci_mode = 0; 423 return 0; 424 } 425 426 int 427 wstsc_dma_xfer_out2 (dev, len, buf, phase) 428 struct sci_softc *dev; 429 int len; 430 register u_short *buf; 431 int phase; 432 { 433 volatile register u_short *sci_dma = (ushort *)(dev->sci_data + 0x10); 434 volatile register u_char *sci_bus_csr = dev->sci_bus_csr; 435 #ifdef DEBUG 436 u_char *obp = (u_char *) buf; 437 #endif 438 #if 0 439 int wait = sci_data_wait; 440 #endif 441 442 QPRINTF(("supradma_out2 %d, csr=%02x\n", len, *dev->sci_bus_csr)); 443 444 QPRINTF(("supradma_out2 {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 445 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 446 obp[6], obp[7], obp[8], obp[9])); 447 448 *dev->sci_tcmd = phase; 449 *dev->sci_mode = SCI_MODE_DMA; 450 *dev->sci_icmd = SCI_ICMD_DATA; 451 *dev->sci_dma_send = 0; 452 while (len > 64) { 453 #if 0 454 wait = sci_data_wait; 455 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 456 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 457 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 458 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 459 || --wait < 0) { 460 #ifdef DEBUG 461 if (sci_debug) 462 printf("supradma_out2 fail: l%d i%x w%d\n", 463 len, csr, wait); 464 #endif 465 *dev->sci_mode = 0; 466 return 0; 467 } 468 } 469 #else 470 *dev->sci_mode = 0; 471 *dev->sci_icmd &= ~SCI_ICMD_ACK; 472 while (!(*sci_bus_csr & SCI_BUS_REQ)) 473 ; 474 *dev->sci_mode = SCI_MODE_DMA; 475 *dev->sci_dma_send = 0; 476 #endif 477 478 #define W2 (*sci_dma = *buf++) 479 W2; W2; W2; W2; W2; W2; W2; W2; 480 W2; W2; W2; W2; W2; W2; W2; W2; 481 if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ) 482 ; 483 len -= 64; 484 } 485 486 while (len > 0) { 487 #if 0 488 wait = sci_data_wait; 489 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 490 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 491 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 492 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 493 || --wait < 0) { 494 #ifdef DEBUG 495 if (sci_debug) 496 printf("supradma_out2 fail: l%d i%x w%d\n", 497 len, csr, wait); 498 #endif 499 *dev->sci_mode = 0; 500 return 0; 501 } 502 } 503 #else 504 *dev->sci_mode = 0; 505 *dev->sci_icmd &= ~SCI_ICMD_ACK; 506 while (!(*sci_bus_csr & SCI_BUS_REQ)) 507 ; 508 *dev->sci_mode = SCI_MODE_DMA; 509 *dev->sci_dma_send = 0; 510 #endif 511 512 *sci_dma = *buf++; 513 if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ) 514 ; 515 len -= 2; 516 } 517 518 #if 0 519 wait = sci_data_wait; 520 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 521 SCI_CSR_PHASE_MATCH && --wait); 522 #endif 523 524 525 *dev->sci_irecv = 0; 526 *dev->sci_icmd &= ~SCI_ICMD_ACK; 527 *dev->sci_mode = 0; 528 *dev->sci_icmd = 0; 529 return 0; 530 } 531 532 int 533 wstsc_intr(arg) 534 void *arg; 535 { 536 struct sci_softc *dev = arg; 537 u_char stat; 538 539 if ((*(dev->sci_csr + 0x10) & SCI_CSR_INT) == 0) 540 return (0); 541 stat = *(dev->sci_iack + 0x10); 542 return (1); 543 } 544
Indexes created Wed Sep 24 15:09:51 GMT 2025