wstsc.c revision 1.20
1 /* $NetBSD: wstsc.c,v 1.20 1998/01/12 10:40:14 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)supradma.c 37 */ 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/kernel.h> 41 #include <sys/device.h> 42 #include <dev/scsipi/scsi_all.h> 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/scsiconf.h> 45 #include <amiga/amiga/device.h> 46 #include <amiga/amiga/isr.h> 47 #include <amiga/dev/scireg.h> 48 #include <amiga/dev/scivar.h> 49 #include <amiga/dev/zbusvar.h> 50 51 void wstscattach __P((struct device *, struct device *, void *)); 52 int wstscmatch __P((struct device *, struct cfdata *, void *)); 53 54 int wstsc_dma_xfer_in __P((struct sci_softc *dev, int len, 55 register u_char *buf, int phase)); 56 int wstsc_dma_xfer_out __P((struct sci_softc *dev, int len, 57 register u_char *buf, int phase)); 58 int wstsc_dma_xfer_in2 __P((struct sci_softc *dev, int len, 59 register u_short *buf, int phase)); 60 int wstsc_dma_xfer_out2 __P((struct sci_softc *dev, int len, 61 register u_short *buf, int phase)); 62 int wstsc_intr __P((void *)); 63 64 struct scsipi_adapter wstsc_scsiswitch = { 65 sci_scsicmd, 66 sci_minphys, 67 0, /* no lun support */ 68 0, /* no lun support */ 69 }; 70 71 struct scsipi_device wstsc_scsidev = { 72 NULL, /* use default error handler */ 73 NULL, /* do not have a start functio */ 74 NULL, /* have no async handler */ 75 NULL, /* Use default done routine */ 76 }; 77 78 #ifdef DEBUG 79 extern int sci_debug; 80 #define QPRINTF(a) if (sci_debug > 1) printf a 81 #else 82 #define QPRINTF(a) 83 #endif 84 85 extern int sci_data_wait; 86 87 int supradma_pseudo = 0; /* 0=none, 1=byte, 2=word */ 88 89 struct cfattach wstsc_ca = { 90 sizeof(struct sci_softc), wstscmatch, wstscattach 91 }; 92 93 /* 94 * if this a Supra WordSync board 95 */ 96 int 97 wstscmatch(pdp, cfp, auxp) 98 struct device *pdp; 99 struct cfdata *cfp; 100 void *auxp; 101 { 102 struct zbus_args *zap; 103 104 zap = auxp; 105 106 /* 107 * Check manufacturer and product id. 108 */ 109 if (zap->manid == 1056 && ( 110 zap->prodid == 12 || /* WordSync */ 111 zap->prodid == 13)) /* ByteSync */ 112 return(1); 113 else 114 return(0); 115 } 116 117 void 118 wstscattach(pdp, dp, auxp) 119 struct device *pdp, *dp; 120 void *auxp; 121 { 122 volatile u_char *rp; 123 struct sci_softc *sc; 124 struct zbus_args *zap; 125 126 printf("\n"); 127 128 zap = auxp; 129 130 sc = (struct sci_softc *)dp; 131 rp = zap->va; 132 /* 133 * set up 5380 register pointers 134 * (Needs check on which Supra board this is - for now, 135 * just do the WordSync) 136 */ 137 sc->sci_data = rp + 0; 138 sc->sci_odata = rp + 0; 139 sc->sci_icmd = rp + 2; 140 sc->sci_mode = rp + 4; 141 sc->sci_tcmd = rp + 6; 142 sc->sci_bus_csr = rp + 8; 143 sc->sci_sel_enb = rp + 8; 144 sc->sci_csr = rp + 10; 145 sc->sci_dma_send = rp + 10; 146 sc->sci_idata = rp + 12; 147 sc->sci_trecv = rp + 12; 148 sc->sci_iack = rp + 14; 149 sc->sci_irecv = rp + 14; 150 151 if (supradma_pseudo == 2) { 152 sc->dma_xfer_in = (int(*)(struct sci_softc *, int, u_char *, int))wstsc_dma_xfer_in2; 153 sc->dma_xfer_out = (int(*)(struct sci_softc *, int, u_char *, int))wstsc_dma_xfer_out2; 154 } 155 else if (supradma_pseudo == 1) { 156 sc->dma_xfer_in = wstsc_dma_xfer_in; 157 sc->dma_xfer_out = wstsc_dma_xfer_out; 158 } 159 160 sc->sc_isr.isr_intr = wstsc_intr; 161 sc->sc_isr.isr_arg = sc; 162 sc->sc_isr.isr_ipl = 2; 163 add_isr(&sc->sc_isr); 164 165 scireset(sc); 166 167 sc->sc_link.scsipi_scsi.channel = SCSI_CHANNEL_ONLY_ONE; 168 sc->sc_link.adapter_softc = sc; 169 sc->sc_link.scsipi_scsi.adapter_target = 7; 170 sc->sc_link.adapter = &wstsc_scsiswitch; 171 sc->sc_link.device = &wstsc_scsidev; 172 sc->sc_link.openings = 1; 173 sc->sc_link.scsipi_scsi.max_target = 7; 174 sc->sc_link.type = BUS_SCSI; 175 TAILQ_INIT(&sc->sc_xslist); 176 177 /* 178 * attach all scsi units on us 179 */ 180 config_found(dp, &sc->sc_link, scsiprint); 181 } 182 183 int 184 wstsc_dma_xfer_in (dev, len, buf, phase) 185 struct sci_softc *dev; 186 int len; 187 register u_char *buf; 188 int phase; 189 { 190 int wait = sci_data_wait; 191 volatile register u_char *sci_dma = dev->sci_idata; 192 volatile register u_char *sci_csr = dev->sci_csr; 193 #ifdef DEBUG 194 u_char *obp = (u_char *) buf; 195 #endif 196 197 QPRINTF(("supradma_in %d, csr=%02x\n", len, *dev->sci_bus_csr)); 198 199 *dev->sci_tcmd = phase; 200 *dev->sci_icmd = 0; 201 *dev->sci_mode = SCI_MODE_DMA; 202 *dev->sci_irecv = 0; 203 204 while (len >= 128) { 205 wait = sci_data_wait; 206 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 207 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 208 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 209 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 210 || --wait < 0) { 211 #ifdef DEBUG 212 if (sci_debug | 1) 213 printf("supradma2_in fail: l%d i%x w%d\n", 214 len, *dev->sci_bus_csr, wait); 215 #endif 216 *dev->sci_mode = 0; 217 return 0; 218 } 219 } 220 221 #define R1 (*buf++ = *sci_dma) 222 R1; R1; R1; R1; R1; R1; R1; R1; 223 R1; R1; R1; R1; R1; R1; R1; R1; 224 R1; R1; R1; R1; R1; R1; R1; R1; 225 R1; R1; R1; R1; R1; R1; R1; R1; 226 R1; R1; R1; R1; R1; R1; R1; R1; 227 R1; R1; R1; R1; R1; R1; R1; R1; 228 R1; R1; R1; R1; R1; R1; R1; R1; 229 R1; R1; R1; R1; R1; R1; R1; R1; 230 R1; R1; R1; R1; R1; R1; R1; R1; 231 R1; R1; R1; R1; R1; R1; R1; R1; 232 R1; R1; R1; R1; R1; R1; R1; R1; 233 R1; R1; R1; R1; R1; R1; R1; R1; 234 R1; R1; R1; R1; R1; R1; R1; R1; 235 R1; R1; R1; R1; R1; R1; R1; R1; 236 R1; R1; R1; R1; R1; R1; R1; R1; 237 R1; R1; R1; R1; R1; R1; R1; R1; 238 len -= 128; 239 } 240 241 while (len > 0) { 242 wait = sci_data_wait; 243 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 244 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 245 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 246 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 247 || --wait < 0) { 248 #ifdef DEBUG 249 if (sci_debug | 1) 250 printf("supradma1_in fail: l%d i%x w%d\n", 251 len, *dev->sci_bus_csr, wait); 252 #endif 253 *dev->sci_mode = 0; 254 return 0; 255 } 256 } 257 258 *buf++ = *sci_dma; 259 len--; 260 } 261 262 QPRINTF(("supradma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 263 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 264 obp[6], obp[7], obp[8], obp[9])); 265 266 *dev->sci_mode = 0; 267 return 0; 268 } 269 270 int 271 wstsc_dma_xfer_out (dev, len, buf, phase) 272 struct sci_softc *dev; 273 int len; 274 register u_char *buf; 275 int phase; 276 { 277 int wait = sci_data_wait; 278 volatile register u_char *sci_dma = dev->sci_data; 279 volatile register u_char *sci_csr = dev->sci_csr; 280 281 QPRINTF(("supradma_out %d, csr=%02x\n", len, *dev->sci_bus_csr)); 282 283 QPRINTF(("supradma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 284 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 285 buf[6], buf[7], buf[8], buf[9])); 286 287 *dev->sci_tcmd = phase; 288 *dev->sci_mode = SCI_MODE_DMA; 289 *dev->sci_icmd = SCI_ICMD_DATA; 290 *dev->sci_dma_send = 0; 291 while (len > 0) { 292 wait = sci_data_wait; 293 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 294 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 295 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 296 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 297 || --wait < 0) { 298 #ifdef DEBUG 299 if (sci_debug) 300 printf("supradma_out fail: l%d i%x w%d\n", 301 len, *dev->sci_bus_csr, wait); 302 #endif 303 *dev->sci_mode = 0; 304 return 0; 305 } 306 } 307 308 *sci_dma = *buf++; 309 len--; 310 } 311 312 wait = sci_data_wait; 313 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 314 SCI_CSR_PHASE_MATCH && --wait); 315 316 317 *dev->sci_mode = 0; 318 *dev->sci_icmd = 0; 319 return 0; 320 } 321 322 323 int 324 wstsc_dma_xfer_in2 (dev, len, buf, phase) 325 struct sci_softc *dev; 326 int len; 327 register u_short *buf; 328 int phase; 329 { 330 volatile register u_short *sci_dma = (u_short *)(dev->sci_idata + 0x10); 331 volatile register u_char *sci_csr = dev->sci_csr + 0x10; 332 #ifdef DEBUG 333 u_char *obp = (u_char *) buf; 334 #endif 335 #if 0 336 int wait = sci_data_wait; 337 #endif 338 339 QPRINTF(("supradma_in2 %d, csr=%02x\n", len, *dev->sci_bus_csr)); 340 341 *dev->sci_tcmd = phase; 342 *dev->sci_mode = SCI_MODE_DMA; 343 *dev->sci_icmd = 0; 344 *(dev->sci_irecv + 16) = 0; 345 while (len >= 128) { 346 #if 0 347 wait = sci_data_wait; 348 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 349 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 350 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 351 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 352 || --wait < 0) { 353 #ifdef DEBUG 354 if (sci_debug | 1) 355 printf("supradma2_in2 fail: l%d i%x w%d\n", 356 len, *dev->sci_bus_csr, wait); 357 #endif 358 *dev->sci_mode &= ~SCI_MODE_DMA; 359 return 0; 360 } 361 } 362 #else 363 while (!(*sci_csr & SCI_CSR_DREQ)) 364 ; 365 #endif 366 367 #define R2 (*buf++ = *sci_dma) 368 R2; R2; R2; R2; R2; R2; R2; R2; 369 R2; R2; R2; R2; R2; R2; R2; R2; 370 R2; R2; R2; R2; R2; R2; R2; R2; 371 R2; R2; R2; R2; R2; R2; R2; R2; 372 R2; R2; R2; R2; R2; R2; R2; R2; 373 R2; R2; R2; R2; R2; R2; R2; R2; 374 R2; R2; R2; R2; R2; R2; R2; R2; 375 R2; R2; R2; R2; R2; R2; R2; R2; 376 len -= 128; 377 } 378 while (len > 0) { 379 #if 0 380 wait = sci_data_wait; 381 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 382 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 383 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 384 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 385 || --wait < 0) { 386 #ifdef DEBUG 387 if (sci_debug | 1) 388 printf("supradma1_in2 fail: l%d i%x w%d\n", 389 len, *dev->sci_bus_csr, wait); 390 #endif 391 *dev->sci_mode &= ~SCI_MODE_DMA; 392 return 0; 393 } 394 } 395 #else 396 while (!(*sci_csr * SCI_CSR_DREQ)) 397 ; 398 #endif 399 400 *buf++ = *sci_dma; 401 len -= 2; 402 } 403 404 QPRINTF(("supradma_in2 {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 405 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 406 obp[6], obp[7], obp[8], obp[9])); 407 408 *dev->sci_irecv = 0; 409 *dev->sci_mode = 0; 410 return 0; 411 } 412 413 int 414 wstsc_dma_xfer_out2 (dev, len, buf, phase) 415 struct sci_softc *dev; 416 int len; 417 register u_short *buf; 418 int phase; 419 { 420 volatile register u_short *sci_dma = (ushort *)(dev->sci_data + 0x10); 421 volatile register u_char *sci_bus_csr = dev->sci_bus_csr; 422 #ifdef DEBUG 423 u_char *obp = (u_char *) buf; 424 #endif 425 #if 0 426 int wait = sci_data_wait; 427 #endif 428 429 QPRINTF(("supradma_out2 %d, csr=%02x\n", len, *dev->sci_bus_csr)); 430 431 QPRINTF(("supradma_out2 {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 432 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 433 obp[6], obp[7], obp[8], obp[9])); 434 435 *dev->sci_tcmd = phase; 436 *dev->sci_mode = SCI_MODE_DMA; 437 *dev->sci_icmd = SCI_ICMD_DATA; 438 *dev->sci_dma_send = 0; 439 while (len > 64) { 440 #if 0 441 wait = sci_data_wait; 442 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 443 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 444 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 445 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 446 || --wait < 0) { 447 #ifdef DEBUG 448 if (sci_debug) 449 printf("supradma_out2 fail: l%d i%x w%d\n", 450 len, csr, wait); 451 #endif 452 *dev->sci_mode = 0; 453 return 0; 454 } 455 } 456 #else 457 *dev->sci_mode = 0; 458 *dev->sci_icmd &= ~SCI_ICMD_ACK; 459 while (!(*sci_bus_csr & SCI_BUS_REQ)) 460 ; 461 *dev->sci_mode = SCI_MODE_DMA; 462 *dev->sci_dma_send = 0; 463 #endif 464 465 #define W2 (*sci_dma = *buf++) 466 W2; W2; W2; W2; W2; W2; W2; W2; 467 W2; W2; W2; W2; W2; W2; W2; W2; 468 if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ) 469 ; 470 len -= 64; 471 } 472 473 while (len > 0) { 474 #if 0 475 wait = sci_data_wait; 476 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 477 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 478 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 479 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 480 || --wait < 0) { 481 #ifdef DEBUG 482 if (sci_debug) 483 printf("supradma_out2 fail: l%d i%x w%d\n", 484 len, csr, wait); 485 #endif 486 *dev->sci_mode = 0; 487 return 0; 488 } 489 } 490 #else 491 *dev->sci_mode = 0; 492 *dev->sci_icmd &= ~SCI_ICMD_ACK; 493 while (!(*sci_bus_csr & SCI_BUS_REQ)) 494 ; 495 *dev->sci_mode = SCI_MODE_DMA; 496 *dev->sci_dma_send = 0; 497 #endif 498 499 *sci_dma = *buf++; 500 if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ) 501 ; 502 len -= 2; 503 } 504 505 #if 0 506 wait = sci_data_wait; 507 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 508 SCI_CSR_PHASE_MATCH && --wait); 509 #endif 510 511 512 *dev->sci_irecv = 0; 513 *dev->sci_icmd &= ~SCI_ICMD_ACK; 514 *dev->sci_mode = 0; 515 *dev->sci_icmd = 0; 516 return 0; 517 } 518 519 int 520 wstsc_intr(arg) 521 void *arg; 522 { 523 struct sci_softc *dev = arg; 524 u_char stat; 525 526 if ((*(dev->sci_csr + 0x10) & SCI_CSR_INT) == 0) 527 return (0); 528 stat = *(dev->sci_iack + 0x10); 529 return (1); 530 } 531
Indexes created Sun Oct 12 05:10:08 GMT 2025