wstsc.c revision 1.28
1 /* $NetBSD: wstsc.c,v 1.28 2002/10/02 04:55:53 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Michael L. Hitch 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)supradma.c 37 */ 38 39 #include <sys/cdefs.h> 40 __KERNEL_RCSID(0, "$NetBSD: wstsc.c,v 1.28 2002/10/02 04:55:53 thorpej Exp $"); 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/kernel.h> 45 #include <sys/device.h> 46 #include <dev/scsipi/scsi_all.h> 47 #include <dev/scsipi/scsipi_all.h> 48 #include <dev/scsipi/scsiconf.h> 49 #include <amiga/amiga/device.h> 50 #include <amiga/amiga/isr.h> 51 #include <amiga/dev/scireg.h> 52 #include <amiga/dev/scivar.h> 53 #include <amiga/dev/zbusvar.h> 54 55 void wstscattach(struct device *, struct device *, void *); 56 int wstscmatch(struct device *, struct cfdata *, void *); 57 58 int wstsc_dma_xfer_in(struct sci_softc *dev, int len, 59 register u_char *buf, int phase); 60 int wstsc_dma_xfer_out(struct sci_softc *dev, int len, 61 register u_char *buf, int phase); 62 int wstsc_dma_xfer_in2(struct sci_softc *dev, int len, 63 register u_short *buf, int phase); 64 int wstsc_dma_xfer_out2(struct sci_softc *dev, int len, 65 register u_short *buf, int phase); 66 int wstsc_intr(void *); 67 68 #ifdef DEBUG 69 extern int sci_debug; 70 #define QPRINTF(a) if (sci_debug > 1) printf a 71 #else 72 #define QPRINTF(a) 73 #endif 74 75 extern int sci_data_wait; 76 77 int supradma_pseudo = 0; /* 0=none, 1=byte, 2=word */ 78 79 CFATTACH_DECL(wstsc, sizeof(struct sci_softc), 80 wstscmatch, wstscattach, NULL, NULL); 81 82 /* 83 * if this a Supra WordSync board 84 */ 85 int 86 wstscmatch(struct device *pdp, struct cfdata *cfp, void *auxp) 87 { 88 struct zbus_args *zap; 89 90 zap = auxp; 91 92 /* 93 * Check manufacturer and product id. 94 */ 95 if (zap->manid == 1056 && ( 96 zap->prodid == 12 || /* WordSync */ 97 zap->prodid == 13)) /* ByteSync */ 98 return(1); 99 else 100 return(0); 101 } 102 103 void 104 wstscattach(struct device *pdp, struct device *dp, void *auxp) 105 { 106 volatile u_char *rp; 107 struct sci_softc *sc = (struct sci_softc *)dp; 108 struct zbus_args *zap; 109 struct scsipi_adapter *adapt = &sc->sc_adapter; 110 struct scsipi_channel *chan = &sc->sc_channel; 111 112 printf("\n"); 113 114 zap = auxp; 115 116 rp = zap->va; 117 /* 118 * set up 5380 register pointers 119 * (Needs check on which Supra board this is - for now, 120 * just do the WordSync) 121 */ 122 sc->sci_data = rp + 0; 123 sc->sci_odata = rp + 0; 124 sc->sci_icmd = rp + 2; 125 sc->sci_mode = rp + 4; 126 sc->sci_tcmd = rp + 6; 127 sc->sci_bus_csr = rp + 8; 128 sc->sci_sel_enb = rp + 8; 129 sc->sci_csr = rp + 10; 130 sc->sci_dma_send = rp + 10; 131 sc->sci_idata = rp + 12; 132 sc->sci_trecv = rp + 12; 133 sc->sci_iack = rp + 14; 134 sc->sci_irecv = rp + 14; 135 136 if (supradma_pseudo == 2) { 137 sc->dma_xfer_in = (int(*)(struct sci_softc *, int, u_char *, int))wstsc_dma_xfer_in2; 138 sc->dma_xfer_out = (int(*)(struct sci_softc *, int, u_char *, int))wstsc_dma_xfer_out2; 139 } 140 else if (supradma_pseudo == 1) { 141 sc->dma_xfer_in = wstsc_dma_xfer_in; 142 sc->dma_xfer_out = wstsc_dma_xfer_out; 143 } 144 145 sc->sc_isr.isr_intr = wstsc_intr; 146 sc->sc_isr.isr_arg = sc; 147 sc->sc_isr.isr_ipl = 2; 148 add_isr(&sc->sc_isr); 149 150 scireset(sc); 151 152 /* 153 * Fill in the scsipi_adapter. 154 */ 155 memset(adapt, 0, sizeof(*adapt)); 156 adapt->adapt_dev = &sc->sc_dev; 157 adapt->adapt_nchannels = 1; 158 adapt->adapt_openings = 7; 159 adapt->adapt_max_periph = 1; 160 adapt->adapt_request = sci_scsipi_request; 161 adapt->adapt_minphys = sci_minphys; 162 163 /* 164 * Fill in the scsipi_channel. 165 */ 166 memset(chan, 0, sizeof(*chan)); 167 chan->chan_adapter = adapt; 168 chan->chan_bustype = &scsi_bustype; 169 chan->chan_channel = 0; 170 chan->chan_ntargets = 8; 171 chan->chan_nluns = 8; 172 chan->chan_id = 7; 173 174 /* 175 * attach all scsi units on us 176 */ 177 config_found(dp, chan, scsiprint); 178 } 179 180 int 181 wstsc_dma_xfer_in(struct sci_softc *dev, int len, register u_char *buf, 182 int phase) 183 { 184 int wait = sci_data_wait; 185 volatile register u_char *sci_dma = dev->sci_idata; 186 volatile register u_char *sci_csr = dev->sci_csr; 187 #ifdef DEBUG 188 u_char *obp = (u_char *) buf; 189 #endif 190 191 QPRINTF(("supradma_in %d, csr=%02x\n", len, *dev->sci_bus_csr)); 192 193 *dev->sci_tcmd = phase; 194 *dev->sci_icmd = 0; 195 *dev->sci_mode = SCI_MODE_DMA; 196 *dev->sci_irecv = 0; 197 198 while (len >= 128) { 199 wait = sci_data_wait; 200 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 201 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 202 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 203 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 204 || --wait < 0) { 205 #ifdef DEBUG 206 if (sci_debug | 1) 207 printf("supradma2_in fail: l%d i%x w%d\n", 208 len, *dev->sci_bus_csr, wait); 209 #endif 210 *dev->sci_mode = 0; 211 return 0; 212 } 213 } 214 215 #define R1 (*buf++ = *sci_dma) 216 R1; R1; R1; R1; R1; R1; R1; R1; 217 R1; R1; R1; R1; R1; R1; R1; R1; 218 R1; R1; R1; R1; R1; R1; R1; R1; 219 R1; R1; R1; R1; R1; R1; R1; R1; 220 R1; R1; R1; R1; R1; R1; R1; R1; 221 R1; R1; R1; R1; R1; R1; R1; R1; 222 R1; R1; R1; R1; R1; R1; R1; R1; 223 R1; R1; R1; R1; R1; R1; R1; R1; 224 R1; R1; R1; R1; R1; R1; R1; R1; 225 R1; R1; R1; R1; R1; R1; R1; R1; 226 R1; R1; R1; R1; R1; R1; R1; R1; 227 R1; R1; R1; R1; R1; R1; R1; R1; 228 R1; R1; R1; R1; R1; R1; R1; R1; 229 R1; R1; R1; R1; R1; R1; R1; R1; 230 R1; R1; R1; R1; R1; R1; R1; R1; 231 R1; R1; R1; R1; R1; R1; R1; R1; 232 len -= 128; 233 } 234 235 while (len > 0) { 236 wait = sci_data_wait; 237 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 238 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 239 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 240 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 241 || --wait < 0) { 242 #ifdef DEBUG 243 if (sci_debug | 1) 244 printf("supradma1_in fail: l%d i%x w%d\n", 245 len, *dev->sci_bus_csr, wait); 246 #endif 247 *dev->sci_mode = 0; 248 return 0; 249 } 250 } 251 252 *buf++ = *sci_dma; 253 len--; 254 } 255 256 QPRINTF(("supradma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 257 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 258 obp[6], obp[7], obp[8], obp[9])); 259 260 *dev->sci_mode = 0; 261 return 0; 262 } 263 264 int 265 wstsc_dma_xfer_out(struct sci_softc *dev, int len, register u_char *buf, 266 int phase) 267 { 268 int wait = sci_data_wait; 269 volatile register u_char *sci_dma = dev->sci_data; 270 volatile register u_char *sci_csr = dev->sci_csr; 271 272 QPRINTF(("supradma_out %d, csr=%02x\n", len, *dev->sci_bus_csr)); 273 274 QPRINTF(("supradma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 275 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], 276 buf[6], buf[7], buf[8], buf[9])); 277 278 *dev->sci_tcmd = phase; 279 *dev->sci_mode = SCI_MODE_DMA; 280 *dev->sci_icmd = SCI_ICMD_DATA; 281 *dev->sci_dma_send = 0; 282 while (len > 0) { 283 wait = sci_data_wait; 284 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 285 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 286 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 287 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 288 || --wait < 0) { 289 #ifdef DEBUG 290 if (sci_debug) 291 printf("supradma_out fail: l%d i%x w%d\n", 292 len, *dev->sci_bus_csr, wait); 293 #endif 294 *dev->sci_mode = 0; 295 return 0; 296 } 297 } 298 299 *sci_dma = *buf++; 300 len--; 301 } 302 303 wait = sci_data_wait; 304 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 305 SCI_CSR_PHASE_MATCH && --wait); 306 307 308 *dev->sci_mode = 0; 309 *dev->sci_icmd = 0; 310 return 0; 311 } 312 313 314 int 315 wstsc_dma_xfer_in2(struct sci_softc *dev, int len, register u_short *buf, 316 int phase) 317 { 318 volatile register u_short *sci_dma = (u_short *)(dev->sci_idata + 0x10); 319 volatile register u_char *sci_csr = dev->sci_csr + 0x10; 320 #ifdef DEBUG 321 u_char *obp = (u_char *) buf; 322 #endif 323 #if 0 324 int wait = sci_data_wait; 325 #endif 326 327 QPRINTF(("supradma_in2 %d, csr=%02x\n", len, *dev->sci_bus_csr)); 328 329 *dev->sci_tcmd = phase; 330 *dev->sci_mode = SCI_MODE_DMA; 331 *dev->sci_icmd = 0; 332 *(dev->sci_irecv + 16) = 0; 333 while (len >= 128) { 334 #if 0 335 wait = sci_data_wait; 336 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 337 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 338 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 339 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 340 || --wait < 0) { 341 #ifdef DEBUG 342 if (sci_debug | 1) 343 printf("supradma2_in2 fail: l%d i%x w%d\n", 344 len, *dev->sci_bus_csr, wait); 345 #endif 346 *dev->sci_mode &= ~SCI_MODE_DMA; 347 return 0; 348 } 349 } 350 #else 351 while (!(*sci_csr & SCI_CSR_DREQ)) 352 ; 353 #endif 354 355 #define R2 (*buf++ = *sci_dma) 356 R2; R2; R2; R2; R2; R2; R2; R2; 357 R2; R2; R2; R2; R2; R2; R2; R2; 358 R2; R2; R2; R2; R2; R2; R2; R2; 359 R2; R2; R2; R2; R2; R2; R2; R2; 360 R2; R2; R2; R2; R2; R2; R2; R2; 361 R2; R2; R2; R2; R2; R2; R2; R2; 362 R2; R2; R2; R2; R2; R2; R2; R2; 363 R2; R2; R2; R2; R2; R2; R2; R2; 364 len -= 128; 365 } 366 while (len > 0) { 367 #if 0 368 wait = sci_data_wait; 369 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 370 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 371 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 372 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 373 || --wait < 0) { 374 #ifdef DEBUG 375 if (sci_debug | 1) 376 printf("supradma1_in2 fail: l%d i%x w%d\n", 377 len, *dev->sci_bus_csr, wait); 378 #endif 379 *dev->sci_mode &= ~SCI_MODE_DMA; 380 return 0; 381 } 382 } 383 #else 384 while (!(*sci_csr * SCI_CSR_DREQ)) 385 ; 386 #endif 387 388 *buf++ = *sci_dma; 389 len -= 2; 390 } 391 392 QPRINTF(("supradma_in2 {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 393 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 394 obp[6], obp[7], obp[8], obp[9])); 395 396 *dev->sci_irecv = 0; 397 *dev->sci_mode = 0; 398 return 0; 399 } 400 401 int 402 wstsc_dma_xfer_out2(struct sci_softc *dev, int len, register u_short *buf, 403 int phase) 404 { 405 volatile register u_short *sci_dma = (ushort *)(dev->sci_data + 0x10); 406 volatile register u_char *sci_bus_csr = dev->sci_bus_csr; 407 #ifdef DEBUG 408 u_char *obp = (u_char *) buf; 409 #endif 410 #if 0 411 int wait = sci_data_wait; 412 #endif 413 414 QPRINTF(("supradma_out2 %d, csr=%02x\n", len, *dev->sci_bus_csr)); 415 416 QPRINTF(("supradma_out2 {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", 417 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5], 418 obp[6], obp[7], obp[8], obp[9])); 419 420 *dev->sci_tcmd = phase; 421 *dev->sci_mode = SCI_MODE_DMA; 422 *dev->sci_icmd = SCI_ICMD_DATA; 423 *dev->sci_dma_send = 0; 424 while (len > 64) { 425 #if 0 426 wait = sci_data_wait; 427 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 428 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 429 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 430 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 431 || --wait < 0) { 432 #ifdef DEBUG 433 if (sci_debug) 434 printf("supradma_out2 fail: l%d i%x w%d\n", 435 len, csr, wait); 436 #endif 437 *dev->sci_mode = 0; 438 return 0; 439 } 440 } 441 #else 442 *dev->sci_mode = 0; 443 *dev->sci_icmd &= ~SCI_ICMD_ACK; 444 while (!(*sci_bus_csr & SCI_BUS_REQ)) 445 ; 446 *dev->sci_mode = SCI_MODE_DMA; 447 *dev->sci_dma_send = 0; 448 #endif 449 450 #define W2 (*sci_dma = *buf++) 451 W2; W2; W2; W2; W2; W2; W2; W2; 452 W2; W2; W2; W2; W2; W2; W2; W2; 453 if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ) 454 ; 455 len -= 64; 456 } 457 458 while (len > 0) { 459 #if 0 460 wait = sci_data_wait; 461 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) != 462 (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) { 463 if (!(*sci_csr & SCI_CSR_PHASE_MATCH) 464 || !(*dev->sci_bus_csr & SCI_BUS_BSY) 465 || --wait < 0) { 466 #ifdef DEBUG 467 if (sci_debug) 468 printf("supradma_out2 fail: l%d i%x w%d\n", 469 len, csr, wait); 470 #endif 471 *dev->sci_mode = 0; 472 return 0; 473 } 474 } 475 #else 476 *dev->sci_mode = 0; 477 *dev->sci_icmd &= ~SCI_ICMD_ACK; 478 while (!(*sci_bus_csr & SCI_BUS_REQ)) 479 ; 480 *dev->sci_mode = SCI_MODE_DMA; 481 *dev->sci_dma_send = 0; 482 #endif 483 484 *sci_dma = *buf++; 485 if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ) 486 ; 487 len -= 2; 488 } 489 490 #if 0 491 wait = sci_data_wait; 492 while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) == 493 SCI_CSR_PHASE_MATCH && --wait); 494 #endif 495 496 497 *dev->sci_irecv = 0; 498 *dev->sci_icmd &= ~SCI_ICMD_ACK; 499 *dev->sci_mode = 0; 500 *dev->sci_icmd = 0; 501 return 0; 502 } 503 504 int 505 wstsc_intr(void *arg) 506 { 507 struct sci_softc *dev = arg; 508 u_char stat; 509 510 if ((*(dev->sci_csr + 0x10) & SCI_CSR_INT) == 0) 511 return (0); 512 stat = *(dev->sci_iack + 0x10); 513 return (1); 514 } 515
Indexes created Sat Sep 27 22:09:54 GMT 2025