Home | History | Annotate | Line # | Download | only in dev
wstsc.c revision 1.3
      1 /*
      2  * Copyright (c) 1994 Michael L. Hitch
      3  * Copyright (c) 1982, 1990 The Regents of the University of California.
      4  * All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  * 3. All advertising materials mentioning features or use of this software
     15  *    must display the following acknowledgement:
     16  *	This product includes software developed by the University of
     17  *	California, Berkeley and its contributors.
     18  * 4. Neither the name of the University nor the names of its contributors
     19  *    may be used to endorse or promote products derived from this software
     20  *    without specific prior written permission.
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     23  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     24  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     25  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     26  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     27  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     28  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     29  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     31  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     32  * SUCH DAMAGE.
     33  *
     34  *	@(#)supradma.c
     35  *	$Id: wstsc.c,v 1.3 1994/06/13 08:13:09 chopps Exp $
     36  */
     37 #include <sys/param.h>
     38 #include <sys/systm.h>
     39 #include <sys/kernel.h>
     40 #include <sys/device.h>
     41 #include <scsi/scsi_all.h>
     42 #include <scsi/scsiconf.h>
     43 #include <amiga/amiga/device.h>
     44 #include <amiga/dev/scireg.h>
     45 #include <amiga/dev/scivar.h>
     46 #include <amiga/dev/ztwobusvar.h>
     47 
     48 int wstscprint __P((void *auxp, char *));
     49 void wstscattach __P((struct device *, struct device *, void *));
     50 int wstscmatch __P((struct device *, struct cfdata *, void *));
     51 
     52 int wstsc_dma_xfer_in __P((struct sci_softc *dev, int len,
     53     register u_char *buf, int phase));
     54 int wstsc_dma_xfer_out __P((struct sci_softc *dev, int len,
     55     register u_char *buf, int phase));
     56 int wstsc_dma_xfer_in2 __P((struct sci_softc *dev, int len,
     57     register u_short *buf, int phase));
     58 int wstsc_dma_xfer_out2 __P((struct sci_softc *dev, int len,
     59     register u_short *buf, int phase));
     60 
     61 struct scsi_adapter wstsc_scsiswitch = {
     62 	sci_scsicmd,
     63 	sci_minphys,
     64 	0,			/* no lun support */
     65 	0,			/* no lun support */
     66 	sci_adinfo,
     67 	"wstsc",
     68 };
     69 
     70 struct scsi_device wstsc_scsidev = {
     71 	NULL,		/* use default error handler */
     72 	NULL,		/* do not have a start functio */
     73 	NULL,		/* have no async handler */
     74 	NULL,		/* Use default done routine */
     75 	"wstsc",
     76 	0,
     77 };
     78 
     79 #define QPRINTF
     80 
     81 #ifdef DEBUG
     82 extern int sci_debug;
     83 #endif
     84 
     85 extern int sci_data_wait;
     86 
     87 int supradma_pseudo = 0;	/* 0=none, 1=byte, 2=word */
     88 
     89 struct cfdriver wstsccd = {
     90 	NULL, "wstsc", wstscmatch, wstscattach,
     91 	DV_DULL, sizeof(struct sci_softc), NULL, 0 };
     92 
     93 /*
     94  * if this a Supra WordSync board
     95  */
     96 int
     97 wstscmatch(pdp, cdp, auxp)
     98 	struct device *pdp;
     99 	struct cfdata *cdp;
    100 	void *auxp;
    101 {
    102 	struct ztwobus_args *zap;
    103 
    104 	zap = auxp;
    105 
    106 	/*
    107 	 * Check manufacturer and product id.
    108 	 */
    109 	if (zap->manid == 1056 && zap->prodid == 12)	/* add other boards? */
    110 		return(1);
    111 	else
    112 		return(0);
    113 }
    114 
    115 void
    116 wstscattach(pdp, dp, auxp)
    117 	struct device *pdp, *dp;
    118 	void *auxp;
    119 {
    120 	volatile u_char *rp;
    121 	struct sci_softc *sc;
    122 	struct ztwobus_args *zap;
    123 
    124 	printf("\n");
    125 
    126 	zap = auxp;
    127 
    128 	sc = (struct sci_softc *)dp;
    129 	rp = zap->va;
    130 	/*
    131 	 * set up 5380 register pointers
    132 	 * (Needs check on which Supra board this is - for now,
    133 	 *  just do the WordSync)
    134 	 */
    135 	sc->sci_data = rp + 0;
    136 	sc->sci_odata = rp + 0;
    137 	sc->sci_icmd = rp + 2;
    138 	sc->sci_mode = rp + 4;
    139 	sc->sci_tcmd = rp + 6;
    140 	sc->sci_bus_csr = rp + 8;
    141 	sc->sci_sel_enb = rp + 8;
    142 	sc->sci_csr = rp + 10;
    143 	sc->sci_dma_send = rp + 10;
    144 	sc->sci_idata = rp + 12;
    145 	sc->sci_trecv = rp + 12;
    146 	sc->sci_iack = rp + 14;
    147 	sc->sci_irecv = rp + 14;
    148 
    149 	if (supradma_pseudo == 2) {
    150 		sc->dma_xfer_in = wstsc_dma_xfer_in2;
    151 		sc->dma_xfer_out = wstsc_dma_xfer_out2;
    152 	}
    153 	else if (supradma_pseudo == 1) {
    154 		sc->dma_xfer_in = wstsc_dma_xfer_in;
    155 		sc->dma_xfer_out = wstsc_dma_xfer_out;
    156 	}
    157 
    158 	scireset(sc);
    159 
    160 	sc->sc_link.adapter_softc = sc;
    161 	sc->sc_link.adapter_targ = 7;
    162 	sc->sc_link.adapter = &wstsc_scsiswitch;
    163 	sc->sc_link.device = &wstsc_scsidev;
    164 	TAILQ_INIT(&sc->sc_xslist);
    165 
    166 	/*
    167 	 * attach all scsi units on us
    168 	 */
    169 	config_found(dp, &sc->sc_link, wstscprint);
    170 }
    171 
    172 /*
    173  * print diag if pnp is NULL else just extra
    174  */
    175 int
    176 wstscprint(auxp, pnp)
    177 	void *auxp;
    178 	char *pnp;
    179 {
    180 	if (pnp == NULL)
    181 		return(UNCONF);
    182 	return(QUIET);
    183 }
    184 
    185 int
    186 wstsc_dma_xfer_in (dev, len, buf, phase)
    187 	struct sci_softc *dev;
    188 	int len;
    189 	register u_char *buf;
    190 	int phase;
    191 {
    192 	int wait = sci_data_wait;
    193 	u_char csr;
    194 	u_char *obp = (u_char *) buf;
    195 	volatile register u_char *sci_dma = dev->sci_idata;
    196 	volatile register u_char *sci_csr = dev->sci_csr;
    197 
    198 	QPRINTF(("supradma_in %d, csr=%02x\n", len, *dev->sci_bus_csr));
    199 
    200 	*dev->sci_tcmd = phase;
    201 	*dev->sci_icmd = 0;
    202 	*dev->sci_mode = SCI_MODE_DMA;
    203 	*dev->sci_irecv = 0;
    204 
    205 	while (len >= 128) {
    206 		wait = sci_data_wait;
    207 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
    208 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
    209 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
    210 			  || !(*dev->sci_bus_csr & SCI_BUS_BSY)
    211 			  || --wait < 0) {
    212 #ifdef DEBUG
    213 				if (sci_debug | 1)
    214 					printf("supradma2_in fail: l%d i%x w%d\n",
    215 					len, *dev->sci_bus_csr, wait);
    216 #endif
    217 				*dev->sci_mode = 0;
    218 				return 0;
    219 			}
    220 		}
    221 
    222 #define R1	(*buf++ = *sci_dma)
    223 		R1; R1; R1; R1; R1; R1; R1; R1;
    224 		R1; R1; R1; R1; R1; R1; R1; R1;
    225 		R1; R1; R1; R1; R1; R1; R1; R1;
    226 		R1; R1; R1; R1; R1; R1; R1; R1;
    227 		R1; R1; R1; R1; R1; R1; R1; R1;
    228 		R1; R1; R1; R1; R1; R1; R1; R1;
    229 		R1; R1; R1; R1; R1; R1; R1; R1;
    230 		R1; R1; R1; R1; R1; R1; R1; R1;
    231 		R1; R1; R1; R1; R1; R1; R1; R1;
    232 		R1; R1; R1; R1; R1; R1; R1; R1;
    233 		R1; R1; R1; R1; R1; R1; R1; R1;
    234 		R1; R1; R1; R1; R1; R1; R1; R1;
    235 		R1; R1; R1; R1; R1; R1; R1; R1;
    236 		R1; R1; R1; R1; R1; R1; R1; R1;
    237 		R1; R1; R1; R1; R1; R1; R1; R1;
    238 		R1; R1; R1; R1; R1; R1; R1; R1;
    239 		len -= 128;
    240 	}
    241 
    242 	while (len > 0) {
    243 		wait = sci_data_wait;
    244 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
    245 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
    246 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
    247 			  || !(*dev->sci_bus_csr & SCI_BUS_BSY)
    248 			  || --wait < 0) {
    249 #ifdef DEBUG
    250 				if (sci_debug | 1)
    251 					printf("supradma1_in fail: l%d i%x w%d\n",
    252 					len, *dev->sci_bus_csr, wait);
    253 #endif
    254 				*dev->sci_mode = 0;
    255 				return 0;
    256 			}
    257 		}
    258 
    259 		*buf++ = *sci_dma;
    260 		len--;
    261 	}
    262 
    263 	QPRINTF(("supradma_in {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
    264 	  len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5],
    265 	  obp[6], obp[7], obp[8], obp[9]));
    266 
    267 	*dev->sci_mode = 0;
    268 	return 0;
    269 }
    270 
    271 int
    272 wstsc_dma_xfer_out (dev, len, buf, phase)
    273 	struct sci_softc *dev;
    274 	int len;
    275 	register u_char *buf;
    276 	int phase;
    277 {
    278 	int wait = sci_data_wait;
    279 	u_char csr;
    280 	u_char *obp = buf;
    281 	volatile register u_char *sci_dma = dev->sci_data;
    282 	volatile register u_char *sci_csr = dev->sci_csr;
    283 
    284 	QPRINTF(("supradma_out %d, csr=%02x\n", len, *dev->sci_bus_csr));
    285 
    286 	QPRINTF(("supradma_out {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
    287   	 len, buf[0], buf[1], buf[2], buf[3], buf[4], buf[5],
    288 	 buf[6], buf[7], buf[8], buf[9]));
    289 
    290 	*dev->sci_tcmd = phase;
    291 	*dev->sci_mode = SCI_MODE_DMA;
    292 	*dev->sci_icmd = SCI_ICMD_DATA;
    293 	*dev->sci_dma_send = 0;
    294 	while (len > 0) {
    295 		wait = sci_data_wait;
    296 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
    297 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
    298 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
    299 			  || !(*dev->sci_bus_csr & SCI_BUS_BSY)
    300 			  || --wait < 0) {
    301 #ifdef DEBUG
    302 				if (sci_debug)
    303 					printf("supradma_out fail: l%d i%x w%d\n",
    304 					len, csr, wait);
    305 #endif
    306 				*dev->sci_mode = 0;
    307 				return 0;
    308 			}
    309 		}
    310 
    311 		*sci_dma = *buf++;
    312 		len--;
    313 	}
    314 
    315 	wait = sci_data_wait;
    316 	while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==
    317 	  SCI_CSR_PHASE_MATCH && --wait);
    318 
    319 
    320 	*dev->sci_mode = 0;
    321 	*dev->sci_icmd = 0;
    322 	return 0;
    323 }
    324 
    325 
    326 int
    327 wstsc_dma_xfer_in2 (dev, len, buf, phase)
    328 	struct sci_softc *dev;
    329 	int len;
    330 	register u_short *buf;
    331 	int phase;
    332 {
    333 	int wait = sci_data_wait;
    334 	u_char csr;
    335 	u_char *obp = (u_char *) buf;
    336 	volatile register u_short *sci_dma = (u_short *)(dev->sci_idata + 0x10);
    337 	volatile register u_char *sci_csr = dev->sci_csr + 0x10;
    338 
    339 	QPRINTF(("supradma_in2 %d, csr=%02x\n", len, *dev->sci_bus_csr));
    340 
    341 	*dev->sci_tcmd = phase;
    342 	*dev->sci_mode = SCI_MODE_DMA;
    343 	*dev->sci_icmd = 0;
    344 	*(dev->sci_irecv + 16) = 0;
    345 	while (len >= 128) {
    346 #if 0
    347 		wait = sci_data_wait;
    348 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
    349 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
    350 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
    351 			  || !(*dev->sci_bus_csr & SCI_BUS_BSY)
    352 			  || --wait < 0) {
    353 #ifdef DEBUG
    354 				if (sci_debug | 1)
    355 					printf("supradma2_in2 fail: l%d i%x w%d\n",
    356 					len, *dev->sci_bus_csr, wait);
    357 #endif
    358 				*dev->sci_mode &= ~SCI_MODE_DMA;
    359 				return 0;
    360 			}
    361 		}
    362 #else
    363 		while (!(*sci_csr & SCI_CSR_DREQ))
    364 			;
    365 #endif
    366 
    367 #define R2	(*buf++ = *sci_dma)
    368 		R2; R2; R2; R2; R2; R2; R2; R2;
    369 		R2; R2; R2; R2; R2; R2; R2; R2;
    370 		R2; R2; R2; R2; R2; R2; R2; R2;
    371 		R2; R2; R2; R2; R2; R2; R2; R2;
    372 		R2; R2; R2; R2; R2; R2; R2; R2;
    373 		R2; R2; R2; R2; R2; R2; R2; R2;
    374 		R2; R2; R2; R2; R2; R2; R2; R2;
    375 		R2; R2; R2; R2; R2; R2; R2; R2;
    376 		len -= 128;
    377 	}
    378 	while (len > 0) {
    379 #if 0
    380 		wait = sci_data_wait;
    381 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
    382 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
    383 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
    384 			  || !(*dev->sci_bus_csr & SCI_BUS_BSY)
    385 			  || --wait < 0) {
    386 #ifdef DEBUG
    387 				if (sci_debug | 1)
    388 					printf("supradma1_in2 fail: l%d i%x w%d\n",
    389 					len, *dev->sci_bus_csr, wait);
    390 #endif
    391 				*dev->sci_mode &= ~SCI_MODE_DMA;
    392 				return 0;
    393 			}
    394 		}
    395 #else
    396 		while (!(*sci_csr * SCI_CSR_DREQ))
    397 			;
    398 #endif
    399 
    400 		*buf++ = *sci_dma;
    401 		len -= 2;
    402 	}
    403 
    404 	QPRINTF(("supradma_in2 {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
    405 	  len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5],
    406 	  obp[6], obp[7], obp[8], obp[9]));
    407 
    408 	*dev->sci_irecv = 0;
    409 	*dev->sci_mode = 0;
    410 	return 0;
    411 }
    412 
    413 int
    414 wstsc_dma_xfer_out2 (dev, len, buf, phase)
    415 	struct sci_softc *dev;
    416 	int len;
    417 	register u_short *buf;
    418 	int phase;
    419 {
    420 	int wait = sci_data_wait;
    421 	u_char csr;
    422 	u_char *obp = (u_char *) buf;
    423 	volatile register u_short *sci_dma = (ushort *)(dev->sci_data + 0x10);
    424 	volatile register u_char *sci_bus_csr = dev->sci_bus_csr;
    425 
    426 	QPRINTF(("supradma_out2 %d, csr=%02x\n", len, *dev->sci_bus_csr));
    427 
    428 	QPRINTF(("supradma_out2 {%d} %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n",
    429   	 len, obp[0], obp[1], obp[2], obp[3], obp[4], obp[5],
    430 	 obp[6], obp[7], obp[8], obp[9]));
    431 
    432 	*dev->sci_tcmd = phase;
    433 	*dev->sci_mode = SCI_MODE_DMA;
    434 	*dev->sci_icmd = SCI_ICMD_DATA;
    435 	*dev->sci_dma_send = 0;
    436 	while (len > 64) {
    437 #if 0
    438 		wait = sci_data_wait;
    439 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
    440 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
    441 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
    442 			  || !(*dev->sci_bus_csr & SCI_BUS_BSY)
    443 			  || --wait < 0) {
    444 #ifdef DEBUG
    445 				if (sci_debug)
    446 					printf("supradma_out2 fail: l%d i%x w%d\n",
    447 					len, csr, wait);
    448 #endif
    449 				*dev->sci_mode = 0;
    450 				return 0;
    451 			}
    452 		}
    453 #else
    454 		*dev->sci_mode = 0;
    455 		*dev->sci_icmd &= ~SCI_ICMD_ACK;
    456 		while (!(*sci_bus_csr & SCI_BUS_REQ))
    457 			;
    458 		*dev->sci_mode = SCI_MODE_DMA;
    459 		*dev->sci_dma_send = 0;
    460 #endif
    461 
    462 #define W2	(*sci_dma = *buf++)
    463 		W2; W2; W2; W2; W2; W2; W2; W2;
    464 		W2; W2; W2; W2; W2; W2; W2; W2;
    465 		if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ)
    466 			;
    467 		len -= 64;
    468 	}
    469 
    470 	while (len > 0) {
    471 #if 0
    472 		wait = sci_data_wait;
    473 		while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) !=
    474 		  (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) {
    475 			if (!(*sci_csr & SCI_CSR_PHASE_MATCH)
    476 			  || !(*dev->sci_bus_csr & SCI_BUS_BSY)
    477 			  || --wait < 0) {
    478 #ifdef DEBUG
    479 				if (sci_debug)
    480 					printf("supradma_out2 fail: l%d i%x w%d\n",
    481 					len, csr, wait);
    482 #endif
    483 				*dev->sci_mode = 0;
    484 				return 0;
    485 			}
    486 		}
    487 #else
    488 		*dev->sci_mode = 0;
    489 		*dev->sci_icmd &= ~SCI_ICMD_ACK;
    490 		while (!(*sci_bus_csr & SCI_BUS_REQ))
    491 			;
    492 		*dev->sci_mode = SCI_MODE_DMA;
    493 		*dev->sci_dma_send = 0;
    494 #endif
    495 
    496 		*sci_dma = *buf++;
    497 		if (*(sci_bus_csr + 0x10) & SCI_BUS_REQ)
    498 			;
    499 		len -= 2;
    500 	}
    501 
    502 #if 0
    503 	wait = sci_data_wait;
    504 	while ((*sci_csr & (SCI_CSR_DREQ|SCI_CSR_PHASE_MATCH)) ==
    505 	  SCI_CSR_PHASE_MATCH && --wait);
    506 #endif
    507 
    508 
    509 	*dev->sci_irecv = 0;
    510 	*dev->sci_icmd &= ~SCI_ICMD_ACK;
    511 	*dev->sci_mode = 0;
    512 	*dev->sci_icmd = 0;
    513 	return 0;
    514 }
    515 
    516 int
    517 wstsc_intr()
    518 {
    519 	struct sci_softc *dev;
    520 	int i, found;
    521 	u_char stat;
    522 
    523 	found = 0;
    524 	for (i = 0; i < wstsccd.cd_ndevs; i++) {
    525 		dev = wstsccd.cd_devs[i];
    526 		if (dev == NULL)
    527 			continue;
    528 		if ((*(dev->sci_csr + 0x10) & SCI_CSR_INT) == 0)
    529 			continue;
    530 		++found;
    531 		stat = *(dev->sci_iack + 0x10);
    532 	}
    533 	return (found);
    534 }
    535